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ad9122: register map updates

main
Rejeesh Kutty 2014-07-30 11:30:43 -04:00
parent 663588eeaf
commit b97bdcdc23
2 changed files with 175 additions and 63 deletions
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50
library/axi_ad9122/axi_ad9122.v
View File

@ -54,15 +54,18 @@ module axi_ad9122 (
// master/slave
dac_enable_out,
dac_enable_in,
dac_sync_out,
dac_sync_in,
// dma interface
dac_div_clk,
dac_drd,
dac_ddata,
dac_ddata_64,
dac_valid_0,
dac_enable_0,
dac_ddata_0,
dac_valid_1,
dac_enable_1,
dac_ddata_1,
dac_dovf,
dac_dunf,
@ -97,8 +100,8 @@ module axi_ad9122 (
parameter PCORE_DAC_DP_DISABLE = 0;
parameter PCORE_IODELAY_GROUP = "dev_if_delay_group";
parameter C_S_AXI_MIN_SIZE = 32'hffff;
parameter C_BASEADDR = 32'hffffffff;
parameter C_HIGHADDR = 32'h00000000;
parameter C_HIGHADDR = 32'hffffffff;
parameter C_BASEADDR = 32'h00000000;
// dac interface
@ -113,15 +116,18 @@ module axi_ad9122 (
// master/slave
output dac_enable_out;
input dac_enable_in;
output dac_sync_out;
input dac_sync_in;
// dma interface
output dac_div_clk;
output dac_drd;
input [127:0] dac_ddata;
input [63:0] dac_ddata_64;
output dac_valid_0;
output dac_enable_0;
input [63:0] dac_ddata_0;
output dac_valid_1;
output dac_enable_1;
input [63:0] dac_ddata_1;
input dac_dovf;
input dac_dunf;
@ -157,7 +163,6 @@ module axi_ad9122 (
// internal signals
wire [127:0] dac_ddata_s;
wire dac_frame_i0_s;
wire [15:0] dac_data_i0_s;
wire dac_frame_i1_s;
@ -189,13 +194,6 @@ module axi_ad9122 (
wire [31:0] up_rdata_s;
wire up_ack_s;
// dac dma data - requires 128bits.
// however, it can be sourced either from a 128bit bus or a 64bit bus.
// 64bit interface is for low bandwidth designs.
// only one of the source can be used at a time and the other one must be tied to 0x0.
assign dac_ddata_s = dac_ddata | {{2{dac_ddata_64[63:32]}}, {2{dac_ddata_64[31:0]}}};
// signal name changes
assign up_clk = s_axi_aclk;
@ -269,10 +267,14 @@ module axi_ad9122 (
.dac_frame_q3 (dac_frame_q3_s),
.dac_data_q3 (dac_data_q3_s),
.dac_status (dac_status_s),
.dac_enable_out (dac_enable_out),
.dac_enable_in (dac_enable_in),
.dac_drd (dac_drd),
.dac_ddata (dac_ddata_s),
.dac_sync_out (dac_sync_out),
.dac_sync_in (dac_sync_in),
.dac_valid_0 (dac_valid_0),
.dac_enable_0 (dac_enable_0),
.dac_ddata_0 (dac_ddata_0),
.dac_valid_1 (dac_valid_1),
.dac_enable_1 (dac_enable_1),
.dac_ddata_1 (dac_ddata_1),
.dac_dovf (dac_dovf),
.dac_dunf (dac_dunf),
.mmcm_rst (mmcm_rst),

188
library/axi_ad9122/axi_ad9122_channel.v
View File

@ -45,16 +45,16 @@ module axi_ad9122_channel (
dac_div_clk,
dac_rst,
dac_dds_data_0,
dac_dds_data_1,
dac_dds_data_2,
dac_dds_data_3,
dac_enable,
dac_data,
dac_frame,
dma_data,
// processor interface
dac_dds_enable,
dac_data_frame,
dac_data_sync,
dac_dds_format,
dac_dds_pattenb,
// bus interface
@ -76,16 +76,16 @@ module axi_ad9122_channel (
input dac_div_clk;
input dac_rst;
output [15:0] dac_dds_data_0;
output [15:0] dac_dds_data_1;
output [15:0] dac_dds_data_2;
output [15:0] dac_dds_data_3;
output dac_enable;
output [63:0] dac_data;
output [ 3:0] dac_frame;
input [63:0] dma_data;
// processor interface
input dac_dds_enable;
input dac_data_frame;
input dac_data_sync;
input dac_dds_format;
input dac_dds_pattenb;
// bus interface
@ -98,38 +98,147 @@ module axi_ad9122_channel (
output [31:0] up_rdata;
output up_ack;
// internal registers
reg dac_enable = 'd0;
reg [63:0] dac_data = 'd0;
reg [ 3:0] dac_frame = 'd0;
reg [15:0] dac_dds_phase_0_0 = 'd0;
reg [15:0] dac_dds_phase_0_1 = 'd0;
reg [15:0] dac_dds_phase_1_0 = 'd0;
reg [15:0] dac_dds_phase_1_1 = 'd0;
reg [15:0] dac_dds_phase_2_0 = 'd0;
reg [15:0] dac_dds_phase_2_1 = 'd0;
reg [15:0] dac_dds_phase_3_0 = 'd0;
reg [15:0] dac_dds_phase_3_1 = 'd0;
reg [15:0] dac_dds_incr_0 = 'd0;
reg [15:0] dac_dds_incr_1 = 'd0;
reg [63:0] dac_dds_data = 'd0;
// internal signals
wire [15:0] dac_dds_patt_1_s;
wire [15:0] dac_dds_data_0_s;
wire [15:0] dac_dds_data_1_s;
wire [15:0] dac_dds_data_2_s;
wire [15:0] dac_dds_data_3_s;
wire [15:0] dac_dds_scale_1_s;
wire [15:0] dac_dds_init_1_s;
wire [15:0] dac_dds_incr_1_s;
wire [15:0] dac_dds_scale_1_s;
wire [15:0] dac_dds_patt_2_s;
wire [15:0] dac_dds_scale_2_s;
wire [15:0] dac_dds_init_2_s;
wire [15:0] dac_dds_incr_2_s;
wire [15:0] dac_dds_scale_2_s;
wire [15:0] dac_pat_data_1_s;
wire [15:0] dac_pat_data_2_s;
wire [ 3:0] dac_data_sel_s;
// dac data select
always @(posedge dac_div_clk) begin
dac_enable <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0;
case (dac_data_sel_s)
4'h2: dac_data <= dma_data;
4'h1: dac_data <= { dac_pat_data_2_s, dac_pat_data_1_s,
dac_pat_data_2_s, dac_pat_data_1_s};
default: dac_data <= dac_dds_data;
endcase
if (dac_data_sel_s == 4'h1) begin
dac_frame <= 4'b0101;
end else begin
dac_frame <= {3'd0, dac_data_frame};
end
end
// single channel dds
axi_ad9122_dds #(.DP_DISABLE(DP_DISABLE)) i_dds (
.dac_div_clk (dac_div_clk),
.dac_rst (dac_rst),
.dac_dds_data_0 (dac_dds_data_0),
.dac_dds_data_1 (dac_dds_data_1),
.dac_dds_data_2 (dac_dds_data_2),
.dac_dds_data_3 (dac_dds_data_3),
.dac_dds_enable (dac_dds_enable),
.dac_dds_format (dac_dds_format),
.dac_dds_pattenb (dac_dds_pattenb),
.dac_dds_patt_1 (dac_dds_patt_1_s),
.dac_dds_init_1 (dac_dds_init_1_s),
.dac_dds_incr_1 (dac_dds_incr_1_s),
.dac_dds_scale_1 (dac_dds_scale_1_s),
.dac_dds_patt_2 (dac_dds_patt_2_s),
.dac_dds_init_2 (dac_dds_init_2_s),
.dac_dds_incr_2 (dac_dds_incr_2_s),
.dac_dds_scale_2 (dac_dds_scale_2_s));
always @(posedge dac_div_clk) begin
if (dac_data_sync == 1'b1) begin
dac_dds_phase_0_0 <= dac_dds_init_1_s;
dac_dds_phase_0_1 <= dac_dds_init_2_s;
dac_dds_phase_1_0 <= dac_dds_phase_0_0 + dac_dds_incr_1_s;
dac_dds_phase_1_1 <= dac_dds_phase_0_1 + dac_dds_incr_2_s;
dac_dds_phase_2_0 <= dac_dds_phase_1_0 + dac_dds_incr_1_s;
dac_dds_phase_2_1 <= dac_dds_phase_1_1 + dac_dds_incr_2_s;
dac_dds_phase_3_0 <= dac_dds_phase_2_0 + dac_dds_incr_1_s;
dac_dds_phase_3_1 <= dac_dds_phase_2_1 + dac_dds_incr_2_s;
dac_dds_incr_0 <= {dac_dds_incr_1_s[13:0], 2'd0};
dac_dds_incr_1 <= {dac_dds_incr_2_s[13:0], 2'd0};
dac_dds_data <= 64'd0;
end else begin
dac_dds_phase_0_0 <= dac_dds_phase_0_0 + dac_dds_incr_0;
dac_dds_phase_0_1 <= dac_dds_phase_0_1 + dac_dds_incr_1;
dac_dds_phase_1_0 <= dac_dds_phase_1_0 + dac_dds_incr_0;
dac_dds_phase_1_1 <= dac_dds_phase_1_1 + dac_dds_incr_1;
dac_dds_phase_2_0 <= dac_dds_phase_2_0 + dac_dds_incr_0;
dac_dds_phase_2_1 <= dac_dds_phase_2_1 + dac_dds_incr_1;
dac_dds_phase_3_0 <= dac_dds_phase_3_0 + dac_dds_incr_0;
dac_dds_phase_3_1 <= dac_dds_phase_3_1 + dac_dds_incr_1;
dac_dds_incr_0 <= dac_dds_incr_0;
dac_dds_incr_1 <= dac_dds_incr_1;
dac_dds_data <= { dac_dds_data_3_s, dac_dds_data_2_s,
dac_dds_data_1_s, dac_dds_data_0_s};
end
end
generate
if (DP_DISABLE == 1) begin
assign dac_dds_data_0_s = 16'd0;
end else begin
ad_dds i_dds_0 (
.clk (dac_div_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_0_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_0_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_0_s));
end
endgenerate
generate
if (DP_DISABLE == 1) begin
assign dac_dds_data_1_s = 16'd0;
end else begin
ad_dds i_dds_1 (
.clk (dac_div_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_1_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_1_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_1_s));
end
endgenerate
generate
if (DP_DISABLE == 1) begin
assign dac_dds_data_2_s = 16'd0;
end else begin
ad_dds i_dds_2 (
.clk (dac_div_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_2_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_2_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_2_s));
end
endgenerate
generate
if (DP_DISABLE == 1) begin
assign dac_dds_data_3_s = 16'd0;
end else begin
ad_dds i_dds_3 (
.clk (dac_div_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_3_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_3_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_3_s));
end
endgenerate
// single channel processor
up_dac_channel #(.PCORE_DAC_CHID(CHID)) i_up_dac_channel (
@ -141,11 +250,12 @@ module axi_ad9122_channel (
.dac_dds_scale_2 (dac_dds_scale_2_s),
.dac_dds_init_2 (dac_dds_init_2_s),
.dac_dds_incr_2 (dac_dds_incr_2_s),
.dac_dds_patt_1 (dac_dds_patt_1_s),
.dac_dds_patt_2 (dac_dds_patt_2_s),
.dac_dds_sel (),
.dac_lb_enb (),
.dac_pn_enb (),
.dac_pat_data_1 (dac_pat_data_1_s),
.dac_pat_data_2 (dac_pat_data_2_s),
.dac_data_sel (dac_data_sel_s),
.dac_iqcor_enb (),
.dac_iqcor_coeff_1 (),
.dac_iqcor_coeff_2 (),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),