fmcomms1: updated common project
- increased the DMA FIFOs to 64 - added axi slices to the source and destination for DMAs - for microblaze systems, increade the ad9643 dma data width at destination - removed sys_fmc_dma_clk and used the sys_200m_clk instead for DMA data transfermain
Adrian Costina
parent
2bd154ad59
commit
b8ab2ff847
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@ -60,8 +60,11 @@
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set axi_ad9122_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9122_dma]
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set_property -dict [list CONFIG.C_DMA_TYPE_SRC {0}] $axi_ad9122_dma
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set_property -dict [list CONFIG.C_DMA_TYPE_DEST {2}] $axi_ad9122_dma
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set_property -dict [list CONFIG.C_FIFO_SIZE {64}] $axi_ad9122_dma
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set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9122_dma
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set_property -dict [list CONFIG.C_CYCLIC {1}] $axi_ad9122_dma
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set_property -dict [list CONFIG.C_AXI_SLICE_DEST {1}] $axi_ad9122_dma
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set_property -dict [list CONFIG.C_AXI_SLICE_SRC {1}] $axi_ad9122_dma
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9122_dma
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if {$sys_zynq == 1} {
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@ -75,14 +78,21 @@ if {$sys_zynq == 1} {
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set axi_ad9643_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9643_dma]
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set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9643_dma
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set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9643_dma
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set_property -dict [list CONFIG.C_FIFO_SIZE {64}] $axi_ad9643_dma
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set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9643_dma
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set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9643_dma
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set_property -dict [list CONFIG.C_AXI_SLICE_DEST {1}] $axi_ad9643_dma
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set_property -dict [list CONFIG.C_AXI_SLICE_SRC {1}] $axi_ad9643_dma
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9643_dma
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if {$sys_zynq == 1} {
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set_property -dict [list CONFIG.C_DMA_AXI_PROTOCOL_DEST {1}] $axi_ad9643_dma
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}
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if {$sys_zynq == 0} {
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9643_dma
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}
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# additions to default configuration
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set_property -dict [list CONFIG.NUM_MI {11}] $axi_cpu_interconnect
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@ -94,9 +104,6 @@ if {$sys_zynq == 0} {
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if {$sys_zynq == 1} {
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set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {125.0}] $sys_ps7
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}
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# reference clock shared with audio clock
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@ -106,7 +113,8 @@ if {$sys_zynq == 1} {
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# connections (dac)
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connect_bd_net -net dac_div_clk [get_bd_ports dac_clk] [get_bd_pins axi_ad9122/dac_div_clk] [get_bd_pins axi_ad9122_dma/fifo_rd_clk]
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connect_bd_net -net dac_div_clk [get_bd_ports dac_clk] [get_bd_pins axi_ad9122/dac_div_clk]
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connect_bd_net -net dac_div_clk [get_bd_pins axi_ad9122_dma/fifo_rd_clk]
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connect_bd_net -net axi_ad9122_dac_clk_in_p [get_bd_ports dac_clk_in_p] [get_bd_pins axi_ad9122/dac_clk_in_p]
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connect_bd_net -net axi_ad9122_dac_clk_in_n [get_bd_ports dac_clk_in_n] [get_bd_pins axi_ad9122/dac_clk_in_n]
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@ -184,13 +192,6 @@ if {$sys_zynq == 1} {
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9643/s_axi_aresetn]
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9643_dma/s_axi_aresetn]
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# memory interconnects share the same clock (fclk2)
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if {$sys_zynq == 1} {
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set sys_fmc_dma_clk_source [get_bd_pins sys_ps7/FCLK_CLK2]
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connect_bd_net -net sys_fmc_dma_clk $sys_fmc_dma_clk_source
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}
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# interconnect (mem/dac)
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if {$sys_zynq == 0 } {
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@ -201,8 +202,8 @@ if {$sys_zynq == 0 } {
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9122_dma/m_src_axi_aresetn]
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} else {
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connect_bd_intf_net -intf_net axi_ad9122_dma_axi [get_bd_intf_pins sys_ps7/S_AXI_HP2] [get_bd_intf_pins axi_ad9122_dma/m_src_axi]
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connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9122_dma/m_src_axi_aclk]
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connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP2_ACLK]
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connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9122_dma/m_src_axi_aclk]
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connect_bd_net -net sys_200m_clk [get_bd_pins sys_ps7/S_AXI_HP2_ACLK]
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9122_dma/m_src_axi_aresetn]
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}
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@ -216,8 +217,8 @@ if {$sys_zynq == 0 } {
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9643_dma/m_dest_axi_aresetn]
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} else {
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connect_bd_intf_net -intf_net axi_ad9643_dma_axi [get_bd_intf_pins sys_ps7/S_AXI_HP1] [get_bd_intf_pins axi_ad9643_dma/m_dest_axi]
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connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9643_dma/m_dest_axi_aclk]
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connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP1_ACLK]
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connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9643_dma/m_dest_axi_aclk]
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connect_bd_net -net sys_200m_clk [get_bd_pins sys_ps7/S_AXI_HP1_ACLK]
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9643_dma/m_dest_axi_aresetn]
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}
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