axi_generic_adc: infer clock for input adc_clk

2019-08-21 10:10:53 -04:00 · 2019-08-21 10:10:53 -04:00 · b77f922de0
parent 78afe38a3f
commit b77f922de0
1 changed files with 2 additions and 0 deletions
--- a/library/axi_generic_adc/axi_generic_adc_ip.tcl
+++ b/library/axi_generic_adc/axi_generic_adc_ip.tcl
@ -17,6 +17,8 @@ adi_ip_files axi_generic_adc [list \

 adi_ip_properties axi_generic_adc

+ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+
 ipx::save_core [ipx::current_core]