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axi_jesd_gt: Split the constraint file 

-split axi_jesd_gt_constr.xdc file in rx, tx and common constraint files
-updated tcl script
main
AndreiGrozav 2016-05-04 19:32:06 +03:00
parent 3ca3414522
commit b6b68e9ab7
4 changed files with 42 additions and 30 deletions
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30
library/axi_jesd_gt/axi_jesd_gt_constr.xdc
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@ -1,35 +1,5 @@
set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_rst_done*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_pll_locked*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_status*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_rst_done*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_pll_locked*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_status*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/rx_sysref_sel*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/rx_up_sysref*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/rx_up_sync*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/tx_sysref_sel*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/tx_up_sysref*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/tx_up_sync*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *ad_rst_sync*}] set_property shreg_extract no [get_cells -hier -filter {name =~ *ad_rst_sync*}]
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_rst_done_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_rst_done_m_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_pll_locked_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_pll_locked_m_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_status_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_rst_done_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_rst_done_m_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_pll_locked_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_pll_locked_m_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_status_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/rx_sysref_sel_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/rx_up_sysref_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/rx_up_sync_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/tx_sysref_sel_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/tx_up_sysref_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/tx_up_sync_m1_reg && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *up_rx_preset_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *ad_rst_sync_m1_reg && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *up_tx_preset_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *ad_rst_sync_m1_reg && IS_SEQUENTIAL}]

4
library/axi_jesd_gt/axi_jesd_gt_ip.tcl
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@ -16,12 +16,16 @@ adi_ip_files axi_jesd_gt [list \
"$ad_hdl_dir/library/common/up_axi.v" \ "$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/common/up_gt_channel.v" \ "$ad_hdl_dir/library/common/up_gt_channel.v" \
"$ad_hdl_dir/library/common/up_gt.v" \ "$ad_hdl_dir/library/common/up_gt.v" \
"axi_jesd_gt_tx_constr.xdc" \
"axi_jesd_gt_rx_constr.xdc" \
"axi_jesd_gt_constr.xdc" \ "axi_jesd_gt_constr.xdc" \
"axi_jesd_gt.v" ] "axi_jesd_gt.v" ]
adi_ip_properties axi_jesd_gt adi_ip_properties axi_jesd_gt
adi_ip_constraints axi_jesd_gt [list \ adi_ip_constraints axi_jesd_gt [list \
"axi_jesd_gt_tx_constr.xdc" \
"axi_jesd_gt_rx_constr.xdc" \
"axi_jesd_gt_constr.xdc" ] "axi_jesd_gt_constr.xdc" ]
ipx::associate_bus_interfaces -busif m_axi -clock s_axi_aclk [ipx::current_core] ipx::associate_bus_interfaces -busif m_axi -clock s_axi_aclk [ipx::current_core]

19
library/axi_jesd_gt/axi_jesd_gt_rx_constr.xdc Normal file
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@ -0,0 +1,19 @@
set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_rst_done*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_pll_locked*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_status*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/rx_sysref_sel*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/rx_up_sysref*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/rx_up_sync*}]
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_rst_done_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_rst_done_m_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_pll_locked_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_pll_locked_m_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_status_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/rx_sysref_sel_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/rx_up_sysref_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/rx_up_sync_m1_reg && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *up_rx_preset_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *ad_rst_sync_m1_reg && IS_SEQUENTIAL}]

19
library/axi_jesd_gt/axi_jesd_gt_tx_constr.xdc Normal file
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@ -0,0 +1,19 @@
set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_rst_done*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_pll_locked*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_status*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/tx_sysref_sel*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/tx_up_sysref*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/tx_up_sync*}]
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_rst_done_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_rst_done_m_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_pll_locked_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_pll_locked_m_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_status_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/tx_sysref_sel_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/tx_up_sysref_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/tx_up_sync_m1_reg && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *up_tx_preset_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *ad_rst_sync_m1_reg && IS_SEQUENTIAL}]