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Merge branch 'hdl_2014_r2' 

Conflicts:
	library/axi_ad9234/axi_ad9234.v
	library/axi_ad9234/axi_ad9234_channel.v
	library/axi_ad9234/axi_ad9234_constr.xdc
	library/axi_ad9234/axi_ad9234_if.v
	library/axi_ad9234/axi_ad9234_ip.tcl
	library/axi_ad9234/axi_ad9234_pnmon.v
	library/axi_ad9434/axi_ad9434.v
	library/axi_ad9434/axi_ad9434_core.v
	projects/ad9434_fmc/common/ad9434_bd.tcl
	projects/ad9467_fmc/common/ad9467_bd.tcl
	projects/common/kc705/kc705_system_bd.tcl
	projects/common/kcu105/kcu105_system_bd.tcl
	projects/common/mitx045/mitx045_system_bd.tcl
	projects/common/vc707/vc707_system_bd.tcl
	projects/common/zc706/zc706_system_bd.tcl
	projects/daq1/common/daq1_bd.tcl
	projects/daq1/zc706/system_top.v
	projects/fmcomms1/ac701/system_top.v
	projects/fmcomms1/common/fmcomms1_bd.tcl
	projects/fmcomms2/ac701/system_constr.xdc
	projects/fmcomms2/common/fmcomms2_bd.tcl
	projects/fmcomms2/zc702/system_constr.xdc
	projects/usdrx1/common/usdrx1_bd.tcl
main
Rejeesh Kutty 2014-12-08 14:25:00 -05:00
parent c54fc0758f 82b9ebe23d
commit b6b5759662
345 changed files with 27514 additions and 8084 deletions
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336
library/axi_ad6676/axi_ad6676.v Executable file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad6676 (
// jesd interface
// rx_clk is (line-rate/40)
rx_clk,
rx_data,
// dma interface
adc_clk,
adc_valid_a,
adc_enable_a,
adc_data_a,
adc_valid_b,
adc_enable_b,
adc_data_b,
adc_dovf,
adc_dunf,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_rvalid,
s_axi_rresp,
s_axi_rdata,
s_axi_rready);
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
parameter C_S_AXI_MIN_SIZE = 32'hffff;
// jesd interface
// rx_clk is (line-rate/40)
input rx_clk;
input [63:0] rx_data;
// dma interface
output adc_clk;
output adc_valid_a;
output adc_enable_a;
output [31:0] adc_data_a;
output adc_valid_b;
output adc_enable_b;
output [31:0] adc_data_b;
input adc_dovf;
input adc_dunf;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata;
input s_axi_rready;
// internal registers
reg up_status_pn_err = 'd0;
reg up_status_pn_oos = 'd0;
reg up_status_or = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_rack = 'd0;
reg up_wack = 'd0;
// internal clocks & resets
wire adc_rst;
wire up_rstn;
wire up_clk;
// internal signals
wire [31:0] adc_data_a_s;
wire [31:0] adc_data_b_s;
wire adc_or_a_s;
wire adc_or_b_s;
wire adc_status_s;
wire [ 1:0] up_status_pn_err_s;
wire [ 1:0] up_status_pn_oos_s;
wire [ 1:0] up_status_or_s;
wire [31:0] up_rdata_s[0:2];
wire up_rack_s[0:2];
wire up_wack_s[0:2];
wire up_wreq_s;
wire [13:0] up_waddr_s;
wire [31:0] up_wdata_s;
wire up_rreq_s;
wire [13:0] up_raddr_s;
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_status_pn_err <= 'd0;
up_status_pn_oos <= 'd0;
up_status_or <= 'd0;
up_rdata <= 'd0;
up_rack <= 'd0;
up_wack <= 'd0;
end else begin
up_status_pn_err <= | up_status_pn_err_s;
up_status_pn_oos <= | up_status_pn_oos_s;
up_status_or <= | up_status_or_s;
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2];
up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2];
up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2];
end
end
// adc valid
assign adc_valid_a = 1'b1;
assign adc_valid_b = 1'b1;
// main (device interface)
axi_ad6676_if i_if (
.rx_clk (rx_clk),
.rx_data (rx_data),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data_a (adc_data_a_s),
.adc_data_b (adc_data_b_s),
.adc_or_a (adc_or_a_s),
.adc_or_b (adc_or_b_s),
.adc_status (adc_status_s));
// channel
axi_ad6676_channel #(.IQSEL(0), .CHID(0)) i_channel_0 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data (adc_data_a_s),
.adc_or (adc_or_a_s),
.adc_dfmt_data (adc_data_a),
.adc_enable (adc_enable_a),
.up_adc_pn_err (up_status_pn_err_s[0]),
.up_adc_pn_oos (up_status_pn_oos_s[0]),
.up_adc_or (up_status_or_s[0]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[0]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[0]),
.up_rack (up_rack_s[0]));
// channel
axi_ad6676_channel #(.IQSEL(1), .CHID(1)) i_channel_1 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data (adc_data_b_s),
.adc_or (adc_or_b_s),
.adc_dfmt_data (adc_data_b),
.adc_enable (adc_enable_b),
.up_adc_pn_err (up_status_pn_err_s[1]),
.up_adc_pn_oos (up_status_pn_oos_s[1]),
.up_adc_or (up_status_or_s[1]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[1]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[1]),
.up_rack (up_rack_s[1]));
// common processor control
up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common (
.mmcm_rst (),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_r1_mode (),
.adc_ddr_edgesel (),
.adc_pin_mode (),
.adc_status (adc_status_s),
.adc_status_ovf (adc_dovf),
.adc_status_unf (adc_dunf),
.adc_clk_ratio (32'd1),
.up_status_pn_err (up_status_pn_err),
.up_status_pn_oos (up_status_pn_oos),
.up_status_or (up_status_or),
.delay_clk (1'b0),
.delay_rst (),
.delay_sel (),
.delay_rwn (),
.delay_addr (),
.delay_wdata (),
.delay_rdata (5'd0),
.delay_ack_t (1'b0),
.delay_locked (1'b1),
.drp_clk (1'd0),
.drp_rst (),
.drp_sel (),
.drp_wr (),
.drp_addr (),
.drp_wdata (),
.drp_rdata (16'd0),
.drp_ready (1'd0),
.drp_locked (1'd1),
.up_usr_chanmax (),
.adc_usr_chanmax (8'd1),
.up_adc_gpio_in (32'd0),
.up_adc_gpio_out (),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[2]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[2]),
.up_rack (up_rack_s[2]));
// up bus interface
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ADC channel-
`timescale 1ns/100ps
module axi_ad6676_channel (
// adc interface
adc_clk,
adc_rst,
adc_data,
adc_or,
// channel interface
adc_dfmt_data,
adc_enable,
up_adc_pn_err,
up_adc_pn_oos,
up_adc_or,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
parameter IQSEL = 0;
parameter CHID = 0;
// adc interface
input adc_clk;
input adc_rst;
input [31:0] adc_data;
input adc_or;
// channel interface
output [31:0] adc_dfmt_data;
output adc_enable;
output up_adc_pn_err;
output up_adc_pn_oos;
output up_adc_or;
// processor interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal signals
wire adc_pn_oos_s;
wire adc_pn_err_s;
wire [ 3:0] adc_pnseq_sel_s;
// instantiations
axi_ad6676_pnmon i_pnmon (
.adc_clk (adc_clk),
.adc_data (adc_data),
.adc_pn_oos (adc_pn_oos_s),
.adc_pn_err (adc_pn_err_s),
.adc_pnseq_sel (adc_pnseq_sel_s));
assign adc_dfmt_data = adc_data;
up_adc_channel #(.PCORE_ADC_CHID(CHID)) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),
.adc_iqcor_enb (),
.adc_dcfilt_enb (),
.adc_dfmt_se (),
.adc_dfmt_type (),
.adc_dfmt_enable (),
.adc_dcfilt_offset (),
.adc_dcfilt_coeff (),
.adc_iqcor_coeff_1 (),
.adc_iqcor_coeff_2 (),
.adc_pnseq_sel (adc_pnseq_sel_s),
.adc_data_sel (),
.adc_pn_err (adc_pn_err_s),
.adc_pn_oos (adc_pn_oos_s),
.adc_or (adc_or),
.up_adc_pn_err (up_adc_pn_err),
.up_adc_pn_oos (up_adc_pn_oos),
.up_adc_or (up_adc_or),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),
.up_usr_datatype_total_bits (),
.up_usr_datatype_bits (),
.up_usr_decimation_m (),
.up_usr_decimation_n (),
.adc_usr_datatype_be (1'b0),
.adc_usr_datatype_signed (1'b1),
.adc_usr_datatype_shift (8'd0),
.adc_usr_datatype_total_bits (8'd16),
.adc_usr_datatype_bits (8'd16),
.adc_usr_decimation_m (16'd1),
.adc_usr_decimation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************

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library/axi_ad6676/axi_ad6676_if.v Executable file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// This is the LVDS/DDR interface
`timescale 1ns/100ps
module axi_ad6676_if (
// jesd interface
// rx_clk is (line-rate/40)
rx_clk,
rx_data,
// adc data output
adc_clk,
adc_rst,
adc_data_a,
adc_data_b,
adc_or_a,
adc_or_b,
adc_status);
// jesd interface
// rx_clk is (line-rate/40)
input rx_clk;
input [63:0] rx_data;
// adc data output
output adc_clk;
input adc_rst;
output [31:0] adc_data_a;
output [31:0] adc_data_b;
output adc_or_a;
output adc_or_b;
output adc_status;
// internal registers
reg adc_status = 'd0;
// internal signals
wire [15:0] adc_data_a_s1_s;
wire [15:0] adc_data_a_s0_s;
wire [15:0] adc_data_b_s1_s;
wire [15:0] adc_data_b_s0_s;
// adc clock is the reference clock
assign adc_clk = rx_clk;
assign adc_or_a = 1'b0;
assign adc_or_b = 1'b0;
// adc channels
assign adc_data_a = {adc_data_a_s1_s, adc_data_a_s0_s};
assign adc_data_b = {adc_data_b_s1_s, adc_data_b_s0_s};
// data multiplex
assign adc_data_a_s1_s = {rx_data[23:16], rx_data[31:24]};
assign adc_data_a_s0_s = {rx_data[ 7: 0], rx_data[15: 8]};
assign adc_data_b_s1_s = {rx_data[55:48], rx_data[63:56]};
assign adc_data_b_s0_s = {rx_data[39:32], rx_data[47:40]};
// status
always @(posedge rx_clk) begin
if (adc_rst == 1'b1) begin
adc_status <= 1'b0;
end else begin
adc_status <= 1'b1;
end
end
endmodule
// ***************************************************************************
// ***************************************************************************

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# ip
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_ad6676
adi_ip_files axi_ad6676 [list \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/ad_pnmon.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_drp_cntrl.v" \
"$ad_hdl_dir/library/common/up_delay_cntrl.v" \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"axi_ad6676_pnmon.v" \
"axi_ad6676_channel.v" \
"axi_ad6676_if.v" \
"axi_ad6676.v" \
"axi_ad6676_constr.xdc" ]
adi_ip_properties axi_ad6676
adi_ip_constraints axi_ad6676 [list \
"axi_ad6676_constr.xdc" ]
ipx::save_core [ipx::current_core]

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library/axi_ad6676/axi_ad6676_pnmon.v Executable file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// PN monitors
`timescale 1ns/100ps
module axi_ad6676_pnmon (
// adc interface
adc_clk,
adc_data,
// pn out of sync and error
adc_pn_oos,
adc_pn_err,
// processor interface
adc_pnseq_sel);
// adc interface
input adc_clk;
input [31:0] adc_data;
// pn out of sync and error
output adc_pn_oos;
output adc_pn_err;
// processor interface PN9 (0x0), PN23 (0x1)
input [ 3:0] adc_pnseq_sel;
// internal registers
reg [31:0] adc_pn_data_in = 'd0;
reg [31:0] adc_pn_data_pn = 'd0;
// internal signals
wire [31:0] adc_pn_data_pn_s;
// PN23 function
function [31:0] pn23;
input [31:0] din;
reg [31:0] dout;
begin
dout[31] = din[22] ^ din[17];
dout[30] = din[21] ^ din[16];
dout[29] = din[20] ^ din[15];
dout[28] = din[19] ^ din[14];
dout[27] = din[18] ^ din[13];
dout[26] = din[17] ^ din[12];
dout[25] = din[16] ^ din[11];
dout[24] = din[15] ^ din[10];
dout[23] = din[14] ^ din[ 9];
dout[22] = din[13] ^ din[ 8];
dout[21] = din[12] ^ din[ 7];
dout[20] = din[11] ^ din[ 6];
dout[19] = din[10] ^ din[ 5];
dout[18] = din[ 9] ^ din[ 4];
dout[17] = din[ 8] ^ din[ 3];
dout[16] = din[ 7] ^ din[ 2];
dout[15] = din[ 6] ^ din[ 1];
dout[14] = din[ 5] ^ din[ 0];
dout[13] = din[ 4] ^ din[22] ^ din[17];
dout[12] = din[ 3] ^ din[21] ^ din[16];
dout[11] = din[ 2] ^ din[20] ^ din[15];
dout[10] = din[ 1] ^ din[19] ^ din[14];
dout[ 9] = din[ 0] ^ din[18] ^ din[13];
dout[ 8] = din[22] ^ din[12];
dout[ 7] = din[21] ^ din[11];
dout[ 6] = din[20] ^ din[10];
dout[ 5] = din[19] ^ din[ 9];
dout[ 4] = din[18] ^ din[ 8];
dout[ 3] = din[17] ^ din[ 7];
dout[ 2] = din[16] ^ din[ 6];
dout[ 1] = din[15] ^ din[ 5];
dout[ 0] = din[14] ^ din[ 4];
pn23 = dout;
end
endfunction
// PN9 function
function [31:0] pn9;
input [31:0] din;
reg [31:0] dout;
begin
dout[31] = din[ 8] ^ din[ 4];
dout[30] = din[ 7] ^ din[ 3];
dout[29] = din[ 6] ^ din[ 2];
dout[28] = din[ 5] ^ din[ 1];
dout[27] = din[ 4] ^ din[ 0];
dout[26] = din[ 3] ^ din[ 8] ^ din[ 4];
dout[25] = din[ 2] ^ din[ 7] ^ din[ 3];
dout[24] = din[ 1] ^ din[ 6] ^ din[ 2];
dout[23] = din[ 0] ^ din[ 5] ^ din[ 1];
dout[22] = din[ 8] ^ din[ 0];
dout[21] = din[ 7] ^ din[ 8] ^ din[ 4];
dout[20] = din[ 6] ^ din[ 7] ^ din[ 3];
dout[19] = din[ 5] ^ din[ 6] ^ din[ 2];
dout[18] = din[ 4] ^ din[ 5] ^ din[ 1];
dout[17] = din[ 3] ^ din[ 4] ^ din[ 0];
dout[16] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4];
dout[15] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3];
dout[14] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2];
dout[13] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1];
dout[12] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0];
dout[11] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4];
dout[10] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3];
dout[ 9] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2];
dout[ 8] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1];
dout[ 7] = din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 0];
dout[ 6] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 4];
dout[ 5] = din[ 0] ^ din[ 2] ^ din[ 5] ^ din[ 7] ^ din[ 3];
dout[ 4] = din[ 8] ^ din[ 1] ^ din[ 6] ^ din[ 2];
dout[ 3] = din[ 7] ^ din[ 0] ^ din[ 5] ^ din[ 1];
dout[ 2] = din[ 6] ^ din[ 8] ^ din[ 0];
dout[ 1] = din[ 5] ^ din[ 7] ^ din[ 8] ^ din[ 4];
dout[ 0] = din[ 4] ^ din[ 6] ^ din[ 7] ^ din[ 3];
pn9 = dout;
end
endfunction
// pn sequence select
assign adc_pn_data_pn_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in : adc_pn_data_pn;
always @(posedge adc_clk) begin
adc_pn_data_in <= {adc_data[15:0], adc_data[31:16]};
if (adc_pnseq_sel == 4'd0) begin
adc_pn_data_pn <= pn9(adc_pn_data_pn_s);
end else begin
adc_pn_data_pn <= pn23(adc_pn_data_pn_s);
end
end
// pn oos & pn err
ad_pnmon #(.DATA_WIDTH(32)) i_pnmon (
.adc_clk (adc_clk),
.adc_valid_in (1'b1),
.adc_data_in (adc_pn_data_in),
.adc_data_pn (adc_pn_data_pn),
.adc_pn_oos (adc_pn_oos),
.adc_pn_err (adc_pn_err));
endmodule
// ***************************************************************************
// ***************************************************************************

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
//------------------------------------------------------------------------------
//----------- Module Declaration -----------------------------------------------
//------------------------------------------------------------------------------
module ad7175_if
(
// Clock and Reset signals
input fpga_clk_i,
input adc_clk_i,
input reset_n_i,
// Conversion control signals
input start_conversion_i,
output [31:0] dma_data_o,
output dma_data_rdy_o,
// Transmit data on request signals
input start_transmission_i,
input [31:0] tx_data_i,
output tx_data_rdy_o,
// Read data on request signals
input start_read_i,
output [31:0] rx_data_o,
output rx_data_rdy_o,
// AD7175 IC control signals
input adc_sdo_i,
output adc_sdi_o,
output adc_cs_o,
output adc_sclk_o,
// ADC status
output reg adc_status_o
);
//------------------------------------------------------------------------------
//----------- Registers Declarations -------------------------------------------
//------------------------------------------------------------------------------
// State Machine Registers
reg [10:0] present_state; // Present FSM State
reg [10:0] next_state; // Next FSM State
reg [10:0] present_state_m1; // Used to synchronise FSM States between different clock domains
// SCLK Registers
reg [7:0] sclk_cnt; // Used to count SCLK Ticks
reg [7:0] sclk_demand; // Used to set number of SCLK Ticks
// Transmit Data Registers
reg [47:0] tx_data_reg; // Used to shift data out
reg [47:0] tx_data_reg_switch; // Used to select data that is being sent
reg tx_data_rdy_int; // Used to signal the end of a transmit cycle
// Receive Data Registers
reg [47:0] rx_data_reg; // Used to shift data in
reg [31:0] rx_read_data_reg; // Used to store read data
reg rx_data_rdy_int; // Used to signal the end of a read cycle
// Conversion Data Registers
reg [31:0] dma_rx_data_reg; // Used to store conversion result (STATUS_REG[31:24] + DATA_REG[23:0])
reg dma_rdy_int; // Used to signal the end of a conversion read
// Internal registers used for external ports
reg adc_sdi_o_int; // Used for adc_sdi_o
reg cs_int; // Used for adc_cs_o
//------------------------------------------------------------------------------
//----------- Wires Declarations -----------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//----------- Local Parameters -------------------------------------------------
//------------------------------------------------------------------------------
// ADC Controller State Machine States
parameter ADC_IDLE_STATE = 11'b00000000001; // Waits for Start Conversion / Start Transmission / Start Read
parameter ADC_WAIT_FOR_DATA_STATE = 11'b00000000010; // Waits for adc_sdo_i to go low (signals new data is available)
parameter ADC_PREP_READ_RESULT_STATE = 11'b00000000100; // Prepares data to perform Status + Data Register Read
parameter ADC_READ_RESULT_STATE = 11'b00000001000; // Reads Status + Data Register
parameter ADC_READ_RESULT_DONE_STATE = 11'b00000010000; // Signals completion of Status + Data Register Read
parameter ADC_PREP_SEND_DATA_STATE = 11'b00000100000; // Prepares data to perform Data Transmit
parameter ADC_SEND_DATA_STATE = 11'b00001000000; // Transmit Data
parameter ADC_SEND_DATA_DONE_STATE = 11'b00010000000; // Signals completion of Data Transmission
parameter ADC_PREP_READ_DATA_STATE = 11'b00100000000; // Prepares data to perform Data Read
parameter ADC_READ_DATA_STATE = 11'b01000000000; // Reads Data
parameter ADC_READ_DATA_DONE_STATE = 11'b10000000000; // Signals completion of Data Read
// Number of SCLK Periods required for Status + Data Read
parameter ADC_SCLK_PERIODS = 8'd48;
//------------------------------------------------------------------------------
//----------- Assign/Always Blocks ---------------------------------------------
//------------------------------------------------------------------------------
assign adc_sdi_o = adc_sdi_o_int;
assign adc_sclk_o = (((present_state_m1 == ADC_READ_RESULT_STATE)||(present_state_m1 == ADC_SEND_DATA_STATE)||(present_state_m1 == ADC_READ_DATA_STATE))&&(sclk_cnt != 8'd0)) ? adc_clk_i : 1'b1;
assign dma_data_o = dma_rx_data_reg;
assign dma_data_rdy_o = dma_rdy_int;
assign adc_cs_o = cs_int;
assign tx_data_rdy_o = tx_data_rdy_int;
assign rx_data_o = rx_read_data_reg;
assign rx_data_rdy_o = rx_data_rdy_int;
// Register States
always @(posedge fpga_clk_i)
begin
if(reset_n_i == 1'b0)
begin
present_state <= ADC_IDLE_STATE;
adc_status_o <= 1'b0;
end
else
begin
present_state <= next_state;
adc_status_o <= 1'b1;
end
end
// State switch logic
always @(posedge fpga_clk_i)
begin
next_state <= present_state;
case(present_state)
ADC_IDLE_STATE:
begin
// If transmit data is required
if(start_transmission_i == 1'b1)
begin
next_state <= ADC_PREP_SEND_DATA_STATE;
end
// If read data is required
else if(start_read_i == 1'b1)
begin
next_state <= ADC_PREP_READ_DATA_STATE;
end
// If start conversion has been requested
else if(start_conversion_i == 1'b1)
begin
next_state <= ADC_WAIT_FOR_DATA_STATE;
end
end
ADC_WAIT_FOR_DATA_STATE:
begin
// If new data is available
if(adc_sdo_i == 1'b0)
begin
next_state <= ADC_PREP_READ_RESULT_STATE;
end
// If transmit data is required
else if(start_transmission_i == 1'b1)
begin
next_state <= ADC_PREP_SEND_DATA_STATE;
end
// If read data is required
else if(start_read_i == 1'b1)
begin
next_state <= ADC_PREP_READ_DATA_STATE;
end
// If transmit data is not required anymore
else if(start_conversion_i == 1'b0)
begin
next_state <= ADC_IDLE_STATE;
end
end
ADC_PREP_READ_RESULT_STATE:
begin
if(present_state_m1 == ADC_PREP_READ_RESULT_STATE)
begin
next_state <= ADC_READ_RESULT_STATE;
end
end
ADC_READ_RESULT_STATE:
begin
// If data has been sent
if(sclk_cnt == 8'd0)
begin
next_state <= ADC_READ_RESULT_DONE_STATE;
end
end
ADC_READ_RESULT_DONE_STATE:
begin
next_state <= ADC_IDLE_STATE;
end
ADC_PREP_SEND_DATA_STATE:
begin
if(present_state_m1 == ADC_PREP_SEND_DATA_STATE)
begin
next_state <= ADC_SEND_DATA_STATE;
end
end
ADC_SEND_DATA_STATE:
begin
// If data has been sent
if(sclk_cnt == 8'd0)
begin
next_state <= ADC_SEND_DATA_DONE_STATE;
end
end
ADC_SEND_DATA_DONE_STATE:
begin
next_state <= ADC_IDLE_STATE;
end
ADC_PREP_READ_DATA_STATE:
begin
if(present_state_m1 == ADC_PREP_READ_DATA_STATE)
begin
next_state <= ADC_READ_DATA_STATE;
end
end
ADC_READ_DATA_STATE:
begin
// If data has been sent
if(sclk_cnt == 8'd0)
begin
next_state <= ADC_READ_DATA_DONE_STATE;
end
end
ADC_READ_DATA_DONE_STATE:
begin
next_state <= ADC_IDLE_STATE;
end
default:
begin
next_state <= ADC_IDLE_STATE;
end
endcase
end
// State output logic
always @(posedge fpga_clk_i)
begin
if(reset_n_i == 1'b0)
begin
dma_rdy_int <= 1'b0;
cs_int <= 1'b1;
tx_data_rdy_int <= 1'b0;
rx_data_rdy_int <= 1'b0;
end
else
begin
case(present_state)
ADC_IDLE_STATE:
begin
dma_rdy_int <= 1'b0;
tx_data_rdy_int <= 1'b0;
rx_data_rdy_int <= 1'b0;
cs_int <= 1'b1;
end
ADC_WAIT_FOR_DATA_STATE:
begin
cs_int <= 1'b0;
end
ADC_PREP_READ_RESULT_STATE:
begin
dma_rdy_int <= 1'b0;
tx_data_reg_switch <= 48'h400044000000;
cs_int <= 1'b0;
end
ADC_READ_RESULT_STATE:
begin
dma_rdy_int <= 1'b0;
cs_int <= 1'b0;
end
ADC_READ_RESULT_DONE_STATE:
begin
// Final data = Status Reg + Data Reg
dma_rx_data_reg <= {rx_data_reg[39:32], rx_data_reg[23:0]};
dma_rdy_int <= 1'b1;
cs_int <= 1'b1;
end
ADC_PREP_SEND_DATA_STATE:
begin
// Maximum 32 bits transmission (that is why I add 16'd0 to the LSB)
tx_data_rdy_int <= 1'b1;
cs_int <= 1'b1;
tx_data_reg_switch <= {tx_data_i, 16'd0};
end
ADC_SEND_DATA_STATE:
begin
tx_data_rdy_int <= 1'b0;
cs_int <= 1'b0;
end
ADC_SEND_DATA_DONE_STATE:
begin
tx_data_rdy_int <= 1'b1;
cs_int <= 1'b1;
end
ADC_PREP_READ_DATA_STATE:
begin
// Maximum 32 bits transmission (that is why I add 16'd0 to the LSB)
cs_int <= 1'b1;
rx_data_rdy_int <= 1'b1;
tx_data_reg_switch <= {2'b01, tx_data_i[29:0], 16'd0};
end
ADC_READ_DATA_STATE:
begin
cs_int <= 1'b0;
rx_data_rdy_int <= 1'b0;
end
ADC_READ_DATA_DONE_STATE:
begin
rx_read_data_reg <= rx_data_reg[31:0];
cs_int <= 1'b1;
rx_data_rdy_int <= 1'b1;
end
default:
begin
tx_data_rdy_int <= 1'b0;
rx_data_rdy_int <= 1'b0;
dma_rdy_int <= 1'b0;
cs_int <= 1'b1;
end
endcase
end
end
// Synchronise States between different clock domains
always @(posedge adc_clk_i)
begin
present_state_m1 <= present_state;
end
// Select size of transfered data according to desired registers (see AD7176_2 Datasheet for details)
always @(posedge fpga_clk_i)
begin
case(tx_data_i[29:24])
6'h00:
begin
sclk_demand <= 8'd16;
end
6'h01, 6'h02, 6'h06, 6'h07, 6'h10, 6'h11, 6'h12, 6'h13, 6'h20, 6'h21, 6'h22, 6'h23, 6'h28, 6'h29, 6'h2a, 6'h2b:
begin
sclk_demand <= 8'd24;
end
6'h03, 6'h04, 6'h30, 6'h31, 6'h32, 6'h33, 6'h38, 6'h39, 6'h3a, 6'h3b:
begin
sclk_demand <= 8'd32;
end
default:
begin
sclk_demand <= 8'd16;
end
endcase
end
// Serial Data In
always @(posedge adc_clk_i)
begin
if((present_state_m1 == ADC_READ_RESULT_STATE)||(present_state_m1 == ADC_SEND_DATA_STATE)||(present_state_m1 == ADC_READ_DATA_STATE))
begin
sclk_cnt <= sclk_cnt - 8'd1;
rx_data_reg <= {rx_data_reg[46:0], adc_sdo_i};
end
else
begin
if((present_state_m1 == ADC_PREP_SEND_DATA_STATE)||(present_state_m1 == ADC_PREP_READ_DATA_STATE))
begin
sclk_cnt <= sclk_demand;
end
else
begin
sclk_cnt <= ADC_SCLK_PERIODS;
end
if(present_state_m1 == ADC_IDLE_STATE)
begin
rx_data_reg <= 48'd0;
end
end
end
// Serial Data Out
always @(negedge adc_clk_i)
begin
if((present_state_m1 == ADC_READ_RESULT_STATE)||(present_state_m1 == ADC_SEND_DATA_STATE)||(present_state_m1 == ADC_READ_DATA_STATE))
begin
adc_sdi_o_int <= tx_data_reg[47];
tx_data_reg <= {tx_data_reg[46:0], 1'b0};
end
else
begin
tx_data_reg <= tx_data_reg_switch;
end
end
endmodule

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// data format (offset binary or 2's complement only)
`timescale 1ps/1ps
module ad_datafmt (
// data path
clk,
valid,
data,
valid_out,
data_out,
// control signals
dfmt_enable,
dfmt_type,
dfmt_se);
// delayed data bus width
parameter DATA_WIDTH = 16;
parameter DATA_WIDTH_OUT = 16;
localparam DW = DATA_WIDTH - 1;
localparam DW1 = DATA_WIDTH_OUT - 1;
// data path
input clk;
input valid;
input [ DW:0] data;
output valid_out;
output [DW1:0] data_out;
// control signals
input dfmt_enable;
input dfmt_type;
input dfmt_se;
// internal registers
reg valid_out = 'd0;
reg [DW1:0] data_out = 'd0;
// internal signals
wire type_s;
wire signext_s;
wire [ DW:0] data_s;
wire [DW1:0] sign_s;
wire [DW1:0] data_out_s;
// if offset-binary convert to 2's complement first
assign type_s = dfmt_enable & dfmt_type;
assign signext_s = dfmt_enable & dfmt_se;
assign data_s = (type_s == 1'b1) ? {~data[DW], data[(DW-1):0]} : data;
assign sign_s = (signext_s == 1'b1) ? {{DW1{data_s[DW]}}} : 0;
generate
if (DW == DW1) begin
assign data_out_s = data_s;
end else begin
assign data_out_s = {sign_s[DW1:(DW+1)], data_s};
end
endgenerate
always @(posedge clk) begin
valid_out <= valid;
data_out <= valid ? data_out_s[DW1:0] : data_out;
end
endmodule
// ***************************************************************************
// ***************************************************************************

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad7175 (
// adc interface (clk, data, over-range)
adc_sdo_i,
adc_sdi_o,
adc_cs_o,
adc_sclk_o,
adc_clk_i,
led_clk_o,
// dma interface
adc_clk,
adc_enable_0,
adc_data_0,
adc_enable_1,
adc_data_1,
adc_enable_2,
adc_data_2,
adc_enable_3,
adc_data_3,
adc_valid_o,
adc_dovf,
adc_dunf,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_rvalid,
s_axi_rresp,
s_axi_rdata,
s_axi_rready);
// parameters
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_ADC_DP_DISABLE = 0;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
parameter C_S_AXI_MIN_SIZE = 32'hffff;
// adc interface (clk, data, over-range)
input adc_sdo_i;
output adc_sdi_o;
output adc_cs_o;
output adc_sclk_o;
input adc_clk_i;
output led_clk_o;
// dma interface
output adc_clk;
output adc_enable_0;
output [31:0] adc_data_0;
output adc_enable_1;
output [31:0] adc_data_1;
output adc_enable_2;
output [31:0] adc_data_2;
output adc_enable_3;
output [31:0] adc_data_3;
output adc_valid_o;
input adc_dovf;
input adc_dunf;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata;
input s_axi_rready;
// internal registers
reg [31:0] up_rdata = 'd0;
reg up_rack = 'd0;
reg up_wack = 'd0;
wire adc_valid_s;
reg adc_valid_d1;
// internal clocks & resets
wire adc_rst;
wire up_rstn;
wire up_clk;
wire [13:0] up_waddr_s;
wire [13:0] up_raddr_s;
// internal signals
wire adc_status_s;
wire up_sel_s;
wire up_wr_s;
wire [13:0] up_addr_s;
wire [31:0] up_wdata_s;
wire [31:0] up_rdata_s[0:4];
wire up_rack_s[0:4];
wire up_wack_s[0:4];
wire [31:0] adc_data_s;
wire [ 1:0] adc_reg_rw_s;
wire [31:0] adc_reg_address_s;
wire [31:0] adc_reg_data_w_s;
wire [31:0] adc_rx_data_s;
wire adc_rx_data_rdy_s;
wire adc_tx_data_rdy_s;
wire [31:0] adc_gpio_out;
wire clk_div_update_rdy_s;
wire [31:0] phase_data_s;
// signal name changes
assign adc_clk = s_axi_aclk;
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
assign adc_valid_o = adc_valid_s & ~adc_valid_d1;
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rdata <= 'd0;
up_rack <= 'd0;
up_wack <= 'd0;
end else begin
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | up_rdata_s[3] | up_rdata_s[4];
up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2] | up_rack_s[3] | up_rack_s[4];
up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2] | up_wack_s[3] | up_wack_s[4];
adc_valid_d1 <= adc_valid_s;
end
end
// channel
axi_ad7175_channel #(
.CHID(0),
.DP_DISABLE (PCORE_ADC_DP_DISABLE))
i_channel_0 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data ({8'b0, adc_data_s[23:0]}),
.adc_valid_in(data_rd_ready_s && (adc_data_s[25:24] == 2'b0)),
.adc_data_out (adc_data_0),
.adc_valid (),
.adc_enable (adc_enable_0),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[0]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[0]),
.up_rack (up_rack_s[0]));
// channel
axi_ad7175_channel #(
.CHID(1),
.DP_DISABLE (PCORE_ADC_DP_DISABLE))
i_channel_1 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data (phase_data_s),
.adc_valid_in(data_rd_ready_s && (adc_data_s[25:24] == 2'b0)),
.adc_data_out (adc_data_1),
.adc_valid (),
.adc_enable (adc_enable_1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[1]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[1]),
.up_rack (up_rack_s[1]));
// channel
axi_ad7175_channel #(
.CHID(3),
.DP_DISABLE (PCORE_ADC_DP_DISABLE))
i_channel_2 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data ({8'b0, adc_data_s[23:0]}),
.adc_valid_in(data_rd_ready_s && (adc_data_s[25:24] == 2'b1)),
.adc_data_out (adc_data_2),
.adc_valid (),
.adc_enable (adc_enable_2),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[2]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[2]),
.up_rack (up_rack_s[2]));
axi_ad7175_channel #(
.CHID(4),
.DP_DISABLE (PCORE_ADC_DP_DISABLE))
i_channel_3 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data (phase_data_s),
.adc_valid_in(data_rd_ready_s && (adc_data_s[25:24] == 2'b1)),
.adc_data_out (adc_data_3),
.adc_valid (adc_valid_s),
.adc_enable (adc_enable_3),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[3]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[3]),
.up_rack (up_rack_s[3]));
// clock divider
clk_div clk_div_i (
.clk_i(s_axi_aclk),
.reset_n_i(up_rstn),
.new_div_i(adc_reg_rw_s[1] && (adc_reg_address_s[7:0] == 8'h40)),
.div_i(adc_reg_data_w_s[31:0]),
.new_phase_inc_i(adc_reg_rw_s[1] && (adc_reg_address_s[7:0] == 8'h41)),
.phase_inc_i(adc_reg_data_w_s[31:0]),
.reg_update_rdy_o(clk_div_update_rdy_s),
.clk_o(led_clk_o),
.phase_o(phase_data_s));
// main (device interface)
ad7175_if ad7175_if_i(
.fpga_clk_i(s_axi_aclk),
.adc_clk_i(adc_clk_i),
.reset_n_i(~adc_rst),
.start_conversion_i(adc_gpio_out[0]),
.dma_data_o(adc_data_s),
.dma_data_rdy_o(data_rd_ready_s),
.start_transmission_i(adc_reg_rw_s[1] && (adc_reg_address_s[7:0] < 8'h39)),
.tx_data_i({adc_reg_address_s[7:0], adc_reg_data_w_s[23:0]}),
.tx_data_rdy_o(adc_tx_data_rdy_s),
.start_read_i(adc_reg_rw_s[0] && (adc_reg_address_s[7:0] < 8'h39)),
.rx_data_o(adc_rx_data_s),
.rx_data_rdy_o(adc_rx_data_rdy_s),
.adc_sdo_i(adc_sdo_i),
.adc_sdi_o(adc_sdi_o),
.adc_cs_o(adc_cs_o),
.adc_sclk_o(adc_sclk_o),
.adc_status_o(adc_status_s));
// common processor control
up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common (
.mmcm_rst (),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_r1_mode (),
.adc_ddr_edgesel (),
.adc_pin_mode (),
.adc_status (adc_status_s),
.adc_status_ovf (adc_dovf),
.adc_status_unf (adc_dunf),
.adc_clk_ratio (32'd1),
.adc_reg_address(adc_reg_address_s),
.adc_reg_data_r(adc_rx_data_s),
.adc_reg_data_w(adc_reg_data_w_s),
.adc_reg_rw(adc_reg_rw_s),
.adc_reg_done(adc_tx_data_rdy_s | adc_rx_data_rdy_s | clk_div_update_rdy_s),
.up_status_pn_err (1'b0),
.up_status_pn_oos (1'b0),
.up_status_or (1'b0),
.delay_clk (),
.delay_rst (),
.delay_sel (),
.delay_rwn (),
.delay_addr (),
.delay_wdata (),
.delay_rdata (),
.delay_ack_t (),
.delay_locked (),
.drp_clk (1'd0),
.drp_rst (),
.drp_sel (),
.drp_wr (),
.drp_addr (),
.drp_wdata (),
.drp_rdata (16'd0),
.drp_ready (1'd0),
.drp_locked (1'd1),
.up_usr_chanmax (),
.adc_usr_chanmax (8'd0),
.up_adc_gpio_in (),
.up_adc_gpio_out (adc_gpio_out),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[4]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[4]),
.up_rack (up_rack_s[4]));
// up bus interface
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ADC channel-
`timescale 1ns/100ps
module axi_ad7175_channel (
// adc interface
adc_clk,
adc_rst,
adc_data,
adc_valid_in,
// channel interface
adc_data_out,
adc_valid,
adc_enable,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
parameter CHID = 0;
parameter DP_DISABLE = 0;
// adc interface
input adc_clk;
input adc_rst;
input [31:0] adc_data;
input adc_valid_in;
// channel interface
output [31:0] adc_data_out;
output adc_valid;
output adc_enable;
// processor interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal signals
wire adc_dfmt_se_s;
wire adc_dfmt_type_s;
wire adc_dfmt_enable_s;
generate
if (DP_DISABLE == 1) begin
assign adc_valid = adc_valid_in;
assign adc_data_out = {8'b0, adc_data};
end else begin
ad_datafmt #(
.DATA_WIDTH(32),
.DATA_WIDTH_OUT(32))
i_ad_datafmt (
.clk (adc_clk),
.valid (adc_valid_in),
.data (adc_data),
.valid_out (adc_valid),
.data_out (adc_data_out),
.dfmt_enable (adc_dfmt_enable_s),
.dfmt_type (adc_dfmt_type_s),
.dfmt_se (adc_dfmt_se_s));
end
endgenerate
up_adc_channel #(.PCORE_ADC_CHID(CHID)) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),
.adc_iqcor_enb (),
.adc_dcfilt_enb (),
.adc_dfmt_se (adc_dfmt_se_s),
.adc_dfmt_type (adc_dfmt_type_s),
.adc_dfmt_enable (adc_dfmt_enable_s),
.adc_dcfilt_offset (),
.adc_dcfilt_coeff (),
.adc_iqcor_coeff_1 (),
.adc_iqcor_coeff_2 (),
.adc_pnseq_sel (),
.adc_data_sel (),
.adc_pn_err (),
.adc_pn_oos (),
.adc_or (),
.up_adc_pn_err (),
.up_adc_pn_oos (),
.up_adc_or (),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),
.up_usr_datatype_total_bits (),
.up_usr_datatype_bits (),
.up_usr_decimation_m (),
.up_usr_decimation_n (),
.adc_usr_datatype_be (1'b0),
.adc_usr_datatype_signed (1'b1),
.adc_usr_datatype_shift (8'd0),
.adc_usr_datatype_total_bits (8'd32),
.adc_usr_datatype_bits (8'd32),
.adc_usr_decimation_m (16'd1),
.adc_usr_decimation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************

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# ip
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_ad7175
adi_ip_files axi_ad7175 [list \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/common/up_delay_cntrl.v" \
"$ad_hdl_dir/library/common/up_drp_cntrl.v" \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"up_adc_common.v" \
"ad_datafmt.v" \
"ad7175_if.v" \
"axi_ad7175.v" \
"axi_ad7175_channel.v" \
"clk_div.v" ]
adi_ip_properties axi_ad7175
ipx::save_core [ipx::current_core]

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
//------------------------------------------------------------------------------
//----------- Module Declaration -----------------------------------------------
//------------------------------------------------------------------------------
module clk_div
(
// Clock and Reset signals
input clk_i,
input reset_n_i,
// Clock divider
input new_div_i,
input [31:0] div_i,
input new_phase_inc_i,
input [31:0] phase_inc_i,
// Divided clock output
output reg reg_update_rdy_o,
output clk_o,
output [31:0] phase_o
);
//------------------------------------------------------------------------------
//----------- Registers Declarations -------------------------------------------
//------------------------------------------------------------------------------
reg [31:0] div;
reg [31:0] div_cnt;
reg [31:0] phase;
reg [31:0] phase_inc;
reg clk_div;
//------------------------------------------------------------------------------
//----------- Assign/Always Blocks ---------------------------------------------
//------------------------------------------------------------------------------
assign clk_o = clk_div;
assign phase_o = phase;
// Register update logic
always @(posedge clk_i)
begin
if(reset_n_i == 1'b0)
begin
div <= 'd0;
phase_inc <= 'd0;
reg_update_rdy_o <= 1'b0;
end
else
begin
if(new_div_i == 1'b1)
begin
div <= div_i;
end
if(new_phase_inc_i == 1'b1)
begin
phase_inc <= phase_inc_i;
end
reg_update_rdy_o <= new_div_i | new_phase_inc_i;
end
end
// Clock division logic
always @(posedge clk_i)
begin
if(reset_n_i == 1'b0)
begin
clk_div <= 'd1;
phase <= 'd0;
end
else
begin
if(div_cnt < div)
begin
div_cnt <= div_cnt + 'd1;
end
else
begin
div_cnt <= 'd1;
//clk_div <= ~clk_div;
end
phase <= phase + phase_inc;
clk_div <= phase[31];
end
end
endmodule

518
library/axi_ad7175/up_adc_common.v Normal file
View File

@ -0,0 +1,518 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module up_adc_common (
// clock reset
mmcm_rst,
// adc interface
adc_clk,
adc_rst,
adc_r1_mode,
adc_ddr_edgesel,
adc_pin_mode,
adc_status,
adc_sync_status,
adc_status_ovf,
adc_status_unf,
adc_clk_ratio,
adc_start_code,
adc_sync,
adc_reg_address,
adc_reg_data_r,
adc_reg_data_w,
adc_reg_rw,
adc_reg_done,
// channel interface
up_status_pn_err,
up_status_pn_oos,
up_status_or,
// delay interface
delay_clk,
delay_rst,
delay_sel,
delay_rwn,
delay_addr,
delay_wdata,
delay_rdata,
delay_ack_t,
delay_locked,
// drp interface
drp_clk,
drp_rst,
drp_sel,
drp_wr,
drp_addr,
drp_wdata,
drp_rdata,
drp_ready,
drp_locked,
// user channel control
up_usr_chanmax,
adc_usr_chanmax,
up_adc_gpio_in,
up_adc_gpio_out,
// bus interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
localparam PCORE_VERSION = 32'h00080062;
parameter PCORE_ID = 0;
// clock reset
output mmcm_rst;
// adc interface
input adc_clk;
output adc_rst;
output adc_r1_mode;
output adc_ddr_edgesel;
output adc_pin_mode;
input adc_status;
input adc_sync_status;
input adc_status_ovf;
input adc_status_unf;
input [31:0] adc_clk_ratio;
output [31:0] adc_start_code;
output adc_sync;
output [31:0] adc_reg_address;
input [31:0] adc_reg_data_r;
output [31:0] adc_reg_data_w;
output [ 1:0] adc_reg_rw;
input adc_reg_done;
// channel interface
input up_status_pn_err;
input up_status_pn_oos;
input up_status_or;
// delay interface
input delay_clk;
output delay_rst;
output delay_sel;
output delay_rwn;
output [ 7:0] delay_addr;
output [ 4:0] delay_wdata;
input [ 4:0] delay_rdata;
input delay_ack_t;
input delay_locked;
// drp interface
input drp_clk;
output drp_rst;
output drp_sel;
output drp_wr;
output [11:0] drp_addr;
output [15:0] drp_wdata;
input [15:0] drp_rdata;
input drp_ready;
input drp_locked;
// user channel control
output [ 7:0] up_usr_chanmax;
input [ 7:0] adc_usr_chanmax;
input [31:0] up_adc_gpio_in;
output [31:0] up_adc_gpio_out;
// bus interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal registers
reg up_wack = 'd0;
reg [31:0] up_scratch = 'd0;
reg up_mmcm_resetn = 'd0;
reg up_resetn = 'd0;
reg up_adc_r1_mode = 'd0;
reg up_adc_ddr_edgesel = 'd0;
reg up_adc_pin_mode = 'd0;
reg up_delay_sel = 'd0;
reg up_delay_rwn = 'd0;
reg [ 7:0] up_delay_addr = 'd0;
reg [ 4:0] up_delay_wdata = 'd0;
reg up_drp_sel_t = 'd0;
reg up_drp_rwn = 'd0;
reg [11:0] up_drp_addr = 'd0;
reg [15:0] up_drp_wdata = 'd0;
reg up_status_ovf = 'd0;
reg up_status_unf = 'd0;
reg [ 7:0] up_usr_chanmax = 'd0;
reg [31:0] up_adc_gpio_out = 'd0;
reg [31:0] up_adc_start_code = 'd0;
reg up_adc_sync = 'd0;
reg up_rack = 'd0;
reg [31:0] up_rdata = 'd0;
reg [31:0] up_adc_reg_address = 'd0;
reg [31:0] up_adc_reg_data = 'd0;
reg up_adc_reg_write = 'd0;
reg up_adc_reg_read = 'd0;
// internal signals
wire up_wreq_s;
wire up_rreq_s;
wire up_preset_s;
wire up_mmcm_preset_s;
wire up_status_s;
wire up_sync_status_s;
wire up_status_ovf_s;
wire up_status_unf_s;
wire up_cntrl_xfer_done;
wire [31:0] up_adc_clk_count_s;
wire [ 4:0] up_delay_rdata_s;
wire up_delay_status_s;
wire up_delay_locked_s;
wire [15:0] up_drp_rdata_s;
wire up_drp_status_s;
wire up_drp_locked_s;
wire [31:0] up_adc_reg_data_s;
wire up_adc_reg_done_s;
// decode block select
assign up_wreq_s = (up_waddr[13:8] == 6'h00) ? up_wreq : 1'b0;
assign up_rreq_s = (up_raddr[13:8] == 6'h00) ? up_rreq : 1'b0;
assign up_preset_s = ~up_resetn;
assign up_mmcm_preset_s = ~up_mmcm_resetn;
// processor write interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_wack <= 'd0;
up_scratch <= 'd0;
up_mmcm_resetn <= 'd0;
up_resetn <= 'd0;
up_adc_r1_mode <= 'd0;
up_adc_ddr_edgesel <= 'd0;
up_adc_pin_mode <= 'd0;
up_delay_sel <= 'd0;
up_delay_rwn <= 'd0;
up_delay_addr <= 'd0;
up_delay_wdata <= 'd0;
up_drp_sel_t <= 'd0;
up_drp_rwn <= 'd0;
up_drp_addr <= 'd0;
up_drp_wdata <= 'd0;
up_status_ovf <= 'd0;
up_status_unf <= 'd0;
up_usr_chanmax <= 'd0;
up_adc_gpio_out <= 'd0;
up_adc_start_code <= 'd0;
up_adc_reg_address <= 'd0;
up_adc_reg_data <= 'd0;
up_adc_reg_read <= 'd0;
up_adc_reg_write <= 'd0;
end else begin
up_wack <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
up_scratch <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin
up_mmcm_resetn <= up_wdata[1];
up_resetn <= up_wdata[0];
end
if (up_adc_sync == 1'b1) begin
if (up_cntrl_xfer_done == 1'b1) begin
up_adc_sync <= 1'b0;
end
end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
up_adc_sync <= up_wdata[3];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
up_adc_r1_mode <= up_wdata[2];
up_adc_ddr_edgesel <= up_wdata[1];
up_adc_pin_mode <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h12)) begin
up_adc_reg_address <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h13)) begin
up_adc_reg_data <= up_wdata;
end
else if((up_adc_reg_done_s == 1'b1) && (up_adc_reg_read == 1'b1))
begin
up_adc_reg_data <= up_adc_reg_data_s;
end
if (up_adc_reg_read == 1'b1) begin
if (up_adc_reg_done_s == 1'b1) begin
up_adc_reg_read <= 1'b0;
end
end else if (up_adc_reg_write == 1'b1) begin
if (up_adc_reg_done_s == 1'b1) begin
up_adc_reg_write <= 1'b0;
end
end
else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h14)) begin
up_adc_reg_write <= up_wdata[1];
up_adc_reg_read <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h18)) begin
up_delay_sel <= up_wdata[17];
up_delay_rwn <= up_wdata[16];
up_delay_addr <= up_wdata[15:8];
up_delay_wdata <= up_wdata[4:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
up_drp_sel_t <= ~up_drp_sel_t;
up_drp_rwn <= up_wdata[28];
up_drp_addr <= up_wdata[27:16];
up_drp_wdata <= up_wdata[15:0];
end
if (up_status_ovf_s == 1'b1) begin
up_status_ovf <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin
up_status_ovf <= up_status_ovf & ~up_wdata[2];
end
if (up_status_unf_s == 1'b1) begin
up_status_unf <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin
up_status_unf <= up_status_unf & ~up_wdata[1];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h28)) begin
up_usr_chanmax <= up_wdata[7:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h29)) begin
up_adc_start_code <= up_wdata[31:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h2f)) begin
up_adc_gpio_out <= up_wdata;
end
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rack <= 'd0;
up_rdata <= 'd0;
end else begin
up_rack <= up_rreq_s;
if (up_rreq_s == 1'b1) begin
case (up_raddr[7:0])
8'h00: up_rdata <= PCORE_VERSION;
8'h01: up_rdata <= PCORE_ID;
8'h02: up_rdata <= up_scratch;
8'h10: up_rdata <= {30'd0, up_mmcm_resetn, up_resetn};
8'h11: up_rdata <= {28'd0, up_adc_sync, up_adc_r1_mode, up_adc_ddr_edgesel, up_adc_pin_mode};
8'h12: up_rdata <= up_adc_reg_address;
8'h13: up_rdata <= up_adc_reg_data;
8'h14: up_rdata <= {30'd0, up_adc_reg_write, up_adc_reg_read};
8'h15: up_rdata <= up_adc_clk_count_s;
8'h16: up_rdata <= adc_clk_ratio;
8'h17: up_rdata <= {28'd0, up_status_pn_err, up_status_pn_oos, up_status_or, up_status_s};
8'h18: up_rdata <= {14'd0, up_delay_sel, up_delay_rwn, up_delay_addr, 3'd0, up_delay_wdata};
8'h19: up_rdata <= {22'd0, up_delay_locked_s, up_delay_status_s, 3'd0, up_delay_rdata_s};
8'h1a: up_rdata <= {31'd0, up_sync_status_s};
8'h1c: up_rdata <= {3'd0, up_drp_rwn, up_drp_addr, up_drp_wdata};
8'h1d: up_rdata <= {14'd0, up_drp_locked_s, up_drp_status_s, up_drp_rdata_s};
8'h22: up_rdata <= {29'd0, up_status_ovf, up_status_unf, 1'b0};
8'h23: up_rdata <= 32'd8;
8'h28: up_rdata <= {24'd0, adc_usr_chanmax};
8'h29: up_rdata <= up_adc_start_code;
8'h2e: up_rdata <= up_adc_gpio_in;
8'h2f: up_rdata <= up_adc_gpio_out;
default: up_rdata <= 0;
endcase
end else begin
up_rdata <= 32'd0;
end
end
end
// resets
ad_rst i_mmcm_rst_reg (.preset(up_mmcm_preset_s), .clk(drp_clk), .rst(mmcm_rst));
ad_rst i_adc_rst_reg (.preset(up_preset_s), .clk(adc_clk), .rst(adc_rst));
ad_rst i_delay_rst_reg (.preset(up_preset_s), .clk(delay_clk), .rst(delay_rst));
ad_rst i_drp_rst_reg (.preset(up_preset_s), .clk(drp_clk), .rst(drp_rst));
// adc control & status
up_xfer_cntrl #(.DATA_WIDTH(70)) i_adc_xfer_cntrl (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_cntrl ({ up_adc_reg_address,
up_adc_reg_data,
up_adc_reg_write,
up_adc_reg_read,
up_adc_sync,
up_adc_r1_mode,
up_adc_ddr_edgesel,
up_adc_pin_mode}),
.up_xfer_done (up_cntrl_xfer_done),
.d_rst (adc_rst),
.d_clk (adc_clk),
.d_data_cntrl ({ adc_reg_address,
adc_reg_data_w,
adc_reg_rw[1],
adc_reg_rw[0],
adc_sync,
adc_r1_mode,
adc_ddr_edgesel,
adc_pin_mode}));
up_xfer_status #(.DATA_WIDTH(37)) i_adc_xfer_status (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_status ({up_adc_reg_data_s,
up_adc_reg_done_s,
up_sync_status_s,
up_status_s,
up_status_ovf_s,
up_status_unf_s}),
.d_rst (adc_rst),
.d_clk (adc_clk),
.d_data_status ({ adc_reg_data_r,
adc_reg_done,
adc_sync_status,
adc_status,
adc_status_ovf,
adc_status_unf}));
up_xfer_cntrl #(.DATA_WIDTH(32)) i_adc_xfer_start_code (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_cntrl (up_adc_start_code),
.up_xfer_done (),
.d_rst (adc_rst),
.d_clk (adc_clk),
.d_data_cntrl (adc_start_code));
// adc clock monitor
up_clock_mon i_adc_clock_mon (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_d_count (up_adc_clk_count_s),
.d_rst (adc_rst),
.d_clk (adc_clk));
// delay control & status
up_delay_cntrl i_delay_cntrl (
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_sel (delay_sel),
.delay_rwn (delay_rwn),
.delay_addr (delay_addr),
.delay_wdata (delay_wdata),
.delay_rdata (delay_rdata),
.delay_ack_t (delay_ack_t),
.delay_locked (delay_locked),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_delay_sel (up_delay_sel),
.up_delay_rwn (up_delay_rwn),
.up_delay_addr (up_delay_addr),
.up_delay_wdata (up_delay_wdata),
.up_delay_rdata (up_delay_rdata_s),
.up_delay_status (up_delay_status_s),
.up_delay_locked (up_delay_locked_s));
// drp control & status
up_drp_cntrl i_drp_cntrl (
.drp_clk (drp_clk),
.drp_rst (drp_rst),
.drp_sel (drp_sel),
.drp_wr (drp_wr),
.drp_addr (drp_addr),
.drp_wdata (drp_wdata),
.drp_rdata (drp_rdata),
.drp_ready (drp_ready),
.drp_locked (drp_locked),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_drp_sel_t (up_drp_sel_t),
.up_drp_rwn (up_drp_rwn),
.up_drp_addr (up_drp_addr),
.up_drp_wdata (up_drp_wdata),
.up_drp_rdata (up_drp_rdata_s),
.up_drp_status (up_drp_status_s),
.up_drp_locked (up_drp_locked_s));
endmodule
// ***************************************************************************
// ***************************************************************************

30
library/axi_ad9122/axi_ad9122.v
View File

@ -185,12 +185,14 @@ module axi_ad9122 (
wire [15:0] drp_rdata_s;
wire drp_ready_s;
wire drp_locked_s;
wire up_sel_s;
wire up_wr_s;
wire [13:0] up_addr_s;
wire up_wreq_s;
wire [13:0] up_waddr_s;
wire [31:0] up_wdata_s;
wire up_wack_s;
wire up_rreq_s;
wire [13:0] up_raddr_s;
wire [31:0] up_rdata_s;
wire up_ack_s;
wire up_rack_s;
// signal name changes
@ -286,12 +288,14 @@ module axi_ad9122 (
.drp_locked (drp_locked_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_ack (up_ack_s));
.up_rack (up_rack_s));
// up bus interface
@ -315,12 +319,14 @@ module axi_ad9122 (
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_ack (up_ack_s));
.up_rack (up_rack_s));
endmodule

30
library/axi_ad9122/axi_ad9122_channel.v
View File

@ -60,12 +60,14 @@ module axi_ad9122_channel (
up_rstn,
up_clk,
up_sel,
up_wr,
up_addr,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_ack);
up_rack);
// parameters
@ -91,12 +93,14 @@ module axi_ad9122_channel (
input up_rstn;
input up_clk;
input up_sel;
input up_wr;
input [13:0] up_addr;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_ack;
output up_rack;
// internal registers
@ -272,12 +276,14 @@ module axi_ad9122_channel (
.dac_usr_interpolation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),
.up_wr (up_wr),
.up_addr (up_addr),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_ack (up_ack));
.up_rack (up_rack));
endmodule

2
library/axi_ad9122/axi_ad9122_constr.xdc Executable file
View File

@ -0,0 +1,2 @@
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports dac_clk_in_p]]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports s_axi_aclk]]

70
library/axi_ad9122/axi_ad9122_core.v
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@ -98,12 +98,14 @@ module axi_ad9122_core (
up_rstn,
up_clk,
up_sel,
up_wr,
up_addr,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_ack);
up_rack);
// parameters
@ -167,17 +169,20 @@ module axi_ad9122_core (
input up_rstn;
input up_clk;
input up_sel;
input up_wr;
input [13:0] up_addr;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_ack;
output up_rack;
// internal registers
reg [31:0] up_rdata = 'd0;
reg up_ack = 'd0;
reg up_rack = 'd0;
reg up_wack = 'd0;
// internal signals
@ -185,11 +190,14 @@ module axi_ad9122_core (
wire dac_frame_s;
wire dac_datafmt_s;
wire [31:0] up_rdata_0_s;
wire up_ack_0_s;
wire up_rack_0_s;
wire up_wack_0_s;
wire [31:0] up_rdata_1_s;
wire up_ack_1_s;
wire up_rack_1_s;
wire up_wack_1_s;
wire [31:0] up_rdata_s;
wire up_ack_s;
wire up_rack_s;
wire up_wack_s;
// defaults
@ -205,10 +213,12 @@ module axi_ad9122_core (
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rdata <= 'd0;
up_ack <= 'd0;
up_rack <= 'd0;
up_wack <= 'd0;
end else begin
up_rdata <= up_rdata_s | up_rdata_0_s | up_rdata_1_s;
up_ack <= up_ack_s | up_ack_0_s | up_ack_1_s;
up_rack <= up_rack_s | up_rack_0_s | up_rack_1_s;
up_wack <= up_wack_s | up_wack_0_s | up_wack_1_s;
end
end
@ -229,12 +239,14 @@ module axi_ad9122_core (
.dac_dds_format (dac_datafmt_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),
.up_wr (up_wr),
.up_addr (up_addr),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_0_s),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_0_s),
.up_ack (up_ack_0_s));
.up_rack (up_rack_0_s));
// dac channel
@ -253,12 +265,14 @@ module axi_ad9122_core (
.dac_dds_format (dac_datafmt_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),
.up_wr (up_wr),
.up_addr (up_addr),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_1_s),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_1_s),
.up_ack (up_ack_1_s));
.up_rack (up_rack_1_s));
// dac common processor interface
@ -288,14 +302,18 @@ module axi_ad9122_core (
.drp_locked (drp_locked),
.up_usr_chanmax (),
.dac_usr_chanmax (8'd3),
.up_dac_gpio_in (32'd0),
.up_dac_gpio_out (),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),
.up_wr (up_wr),
.up_addr (up_addr),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s),
.up_ack (up_ack_s));
.up_rack (up_rack_s));
endmodule

3
library/axi_ad9122/axi_ad9122_ip.tcl
View File

@ -23,9 +23,12 @@ adi_ip_files axi_ad9122 [list \
"axi_ad9122_channel.v" \
"axi_ad9122_core.v" \
"axi_ad9122_if.v" \
"axi_ad9122_constr.xdc" \
"axi_ad9122.v" ]
adi_ip_properties axi_ad9122
adi_ip_constraints axi_ad9122 [list \
"axi_ad9122_constr.xdc" ]
ipx::save_core [ipx::current_core]

30
library/axi_ad9144/axi_ad9144.v
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@ -165,12 +165,14 @@ module axi_ad9144 (
wire [ 15:0] dac_data_3_1_s;
wire [ 15:0] dac_data_3_2_s;
wire [ 15:0] dac_data_3_3_s;
wire up_sel_s;
wire up_wr_s;
wire [ 13:0] up_addr_s;
wire up_wreq_s;
wire [ 13:0] up_waddr_s;
wire [ 31:0] up_wdata_s;
wire up_wack_s;
wire up_rreq_s;
wire [ 13:0] up_raddr_s;
wire [ 31:0] up_rdata_s;
wire up_ack_s;
wire up_rack_s;
// signal name changes
@ -242,12 +244,14 @@ module axi_ad9144 (
.dac_dunf (dac_dunf),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_ack (up_ack_s));
.up_rack (up_rack_s));
// up bus interface
@ -271,12 +275,14 @@ module axi_ad9144 (
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_ack (up_ack_s));
.up_rack (up_rack_s));
endmodule

30
library/axi_ad9144/axi_ad9144_channel.v
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@ -58,12 +58,14 @@ module axi_ad9144_channel (
up_rstn,
up_clk,
up_sel,
up_wr,
up_addr,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_ack);
up_rack);
// parameters
@ -87,12 +89,14 @@ module axi_ad9144_channel (
input up_rstn;
input up_clk;
input up_sel;
input up_wr;
input [13:0] up_addr;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_ack;
output up_rack;
// internal registers
@ -583,12 +587,14 @@ module axi_ad9144_channel (
.dac_usr_interpolation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),
.up_wr (up_wr),
.up_addr (up_addr),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_ack (up_ack));
.up_rack (up_rack));
endmodule

2
library/axi_ad9144/axi_ad9144_constr.xdc
View File

@ -1,5 +1,5 @@
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports dac_clk]]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports tx_clk]]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports s_axi_aclk]]

94
library/axi_ad9144/axi_ad9144_core.v
View File

@ -83,12 +83,14 @@ module axi_ad9144_core (
up_rstn,
up_clk,
up_sel,
up_wr,
up_addr,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_ack);
up_rack);
// parameters
@ -137,32 +139,40 @@ module axi_ad9144_core (
input up_rstn;
input up_clk;
input up_sel;
input up_wr;
input [13:0] up_addr;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_ack;
output up_rack;
// internal registers
reg [31:0] up_rdata = 'd0;
reg up_ack = 'd0;
reg up_rack = 'd0;
reg up_wack = 'd0;
// internal signals
wire dac_sync_s;
wire dac_datafmt_s;
wire [31:0] up_rdata_0_s;
wire up_ack_0_s;
wire up_rack_0_s;
wire up_wack_0_s;
wire [31:0] up_rdata_1_s;
wire up_ack_1_s;
wire up_rack_1_s;
wire up_wack_1_s;
wire [31:0] up_rdata_2_s;
wire up_ack_2_s;
wire up_rack_2_s;
wire up_wack_2_s;
wire [31:0] up_rdata_3_s;
wire up_ack_3_s;
wire up_rack_3_s;
wire up_wack_3_s;
wire [31:0] up_rdata_s;
wire up_ack_s;
wire up_rack_s;
wire up_wack_s;
// dac valid
@ -176,10 +186,12 @@ module axi_ad9144_core (
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rdata <= 'd0;
up_ack <= 'd0;
up_rack <= 'd0;
up_wack <= 'd0;
end else begin
up_rdata <= up_rdata_s | up_rdata_0_s | up_rdata_1_s | up_rdata_2_s | up_rdata_3_s;
up_ack <= up_ack_s | up_ack_0_s | up_ack_1_s | up_ack_2_s | up_ack_3_s;
up_rack <= up_rack_s | up_rack_0_s | up_rack_1_s | up_rack_2_s | up_rack_3_s;
up_wack <= up_wack_s | up_wack_0_s | up_wack_1_s | up_wack_2_s | up_wack_3_s;
end
end
@ -195,12 +207,14 @@ module axi_ad9144_core (
.dac_dds_format (dac_datafmt_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),
.up_wr (up_wr),
.up_addr (up_addr),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_0_s),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_0_s),
.up_ack (up_ack_0_s));
.up_rack (up_rack_0_s));
// dac channel
@ -214,12 +228,14 @@ module axi_ad9144_core (
.dac_dds_format (dac_datafmt_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),
.up_wr (up_wr),
.up_addr (up_addr),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_1_s),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_1_s),
.up_ack (up_ack_1_s));
.up_rack (up_rack_1_s));
// dac channel
@ -233,12 +249,14 @@ module axi_ad9144_core (
.dac_dds_format (dac_datafmt_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),
.up_wr (up_wr),
.up_addr (up_addr),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_2_s),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_2_s),
.up_ack (up_ack_2_s));
.up_rack (up_rack_2_s));
// dac channel
@ -252,12 +270,14 @@ module axi_ad9144_core (
.dac_dds_format (dac_datafmt_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),
.up_wr (up_wr),
.up_addr (up_addr),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_3_s),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_3_s),
.up_ack (up_ack_3_s));
.up_rack (up_rack_3_s));
// dac common processor interface
@ -291,12 +311,14 @@ module axi_ad9144_core (
.up_dac_gpio_out (),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),
.up_wr (up_wr),
.up_addr (up_addr),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s),
.up_ack (up_ack_s));
.up_rack (up_rack_s));
endmodule

3
library/axi_ad9144/axi_ad9144_ip.tcl
View File

@ -20,7 +20,8 @@ adi_ip_files axi_ad9144 [list \
"axi_ad9144_channel.v" \
"axi_ad9144_core.v" \
"axi_ad9144_if.v" \
"axi_ad9144.v" ]
"axi_ad9144.v" \
"axi_ad9144_constr.xdc" ]
adi_ip_properties axi_ad9144
adi_ip_constraints axi_ad9144 [list \

242
library/axi_ad9152/axi_ad9152.v Normal file
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@ -0,0 +1,242 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9152 (
// jesd interface
// tx_clk is (line-rate/40)
tx_clk,
tx_data,
// dma interface
dac_clk,
dac_valid_0,
dac_enable_0,
dac_ddata_0,
dac_valid_1,
dac_enable_1,
dac_ddata_1,
dac_dovf,
dac_dunf,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_rvalid,
s_axi_rdata,
s_axi_rresp,
s_axi_rready);
// parameters
parameter PCORE_ID = 0;
parameter PCORE_DAC_DP_DISABLE = 0;
parameter C_S_AXI_MIN_SIZE = 32'hffff;
// jesd interface
// tx_clk is (line-rate/40)
input tx_clk;
output [127:0] tx_data;
// dma interface
output dac_clk;
output dac_valid_0;
output dac_enable_0;
input [ 63:0] dac_ddata_0;
output dac_valid_1;
output dac_enable_1;
input [ 63:0] dac_ddata_1;
input dac_dovf;
input dac_dunf;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [ 31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [ 31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [ 31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [ 31:0] s_axi_rdata;
output [ 1:0] s_axi_rresp;
input s_axi_rready;
// internal clocks and resets
wire dac_rst;
wire up_clk;
wire up_rstn;
// internal signals
wire [ 15:0] dac_data_0_0_s;
wire [ 15:0] dac_data_0_1_s;
wire [ 15:0] dac_data_0_2_s;
wire [ 15:0] dac_data_0_3_s;
wire [ 15:0] dac_data_1_0_s;
wire [ 15:0] dac_data_1_1_s;
wire [ 15:0] dac_data_1_2_s;
wire [ 15:0] dac_data_1_3_s;
wire up_wreq_s;
wire [ 13:0] up_waddr_s;
wire [ 31:0] up_wdata_s;
wire up_wack_s;
wire up_rreq_s;
wire [ 13:0] up_raddr_s;
wire [ 31:0] up_rdata_s;
wire up_rack_s;
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
// device interface
axi_ad9152_if i_if (
.tx_clk (tx_clk),
.tx_data (tx_data),
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_data_0_0 (dac_data_0_0_s),
.dac_data_0_1 (dac_data_0_1_s),
.dac_data_0_2 (dac_data_0_2_s),
.dac_data_0_3 (dac_data_0_3_s),
.dac_data_1_0 (dac_data_1_0_s),
.dac_data_1_1 (dac_data_1_1_s),
.dac_data_1_2 (dac_data_1_2_s),
.dac_data_1_3 (dac_data_1_3_s));
// core
axi_ad9152_core #(.PCORE_ID(PCORE_ID), .DP_DISABLE(PCORE_DAC_DP_DISABLE)) i_core (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_data_0_0 (dac_data_0_0_s),
.dac_data_0_1 (dac_data_0_1_s),
.dac_data_0_2 (dac_data_0_2_s),
.dac_data_0_3 (dac_data_0_3_s),
.dac_data_1_0 (dac_data_1_0_s),
.dac_data_1_1 (dac_data_1_1_s),
.dac_data_1_2 (dac_data_1_2_s),
.dac_data_1_3 (dac_data_1_3_s),
.dac_valid_0 (dac_valid_0),
.dac_enable_0 (dac_enable_0),
.dac_ddata_0 (dac_ddata_0),
.dac_valid_1 (dac_valid_1),
.dac_enable_1 (dac_enable_1),
.dac_ddata_1 (dac_ddata_1),
.dac_dovf (dac_dovf),
.dac_dunf (dac_dunf),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_rack (up_rack_s));
// up bus interface
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_rack (up_rack_s));
endmodule
// ***************************************************************************
// ***************************************************************************

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library/axi_ad9152/axi_ad9152_channel.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9152_channel (
// dac interface
dac_clk,
dac_rst,
dac_enable,
dac_data,
dma_data,
// processor interface
dac_data_sync,
dac_dds_format,
// bus interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
parameter CHID = 32'h0;
parameter DP_DISABLE = 0;
// dac interface
input dac_clk;
input dac_rst;
output dac_enable;
output [63:0] dac_data;
input [63:0] dma_data;
// processor interface
input dac_data_sync;
input dac_dds_format;
// bus interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal registers
reg dac_enable = 'd0;
reg [63:0] dac_data = 'd0;
reg [63:0] dac_pn7_data = 'd0;
reg [63:0] dac_pn15_data = 'd0;
reg [63:0] dac_pn23_data = 'd0;
reg [63:0] dac_pn31_data = 'd0;
reg [15:0] dac_dds_phase_0_0 = 'd0;
reg [15:0] dac_dds_phase_0_1 = 'd0;
reg [15:0] dac_dds_phase_1_0 = 'd0;
reg [15:0] dac_dds_phase_1_1 = 'd0;
reg [15:0] dac_dds_phase_2_0 = 'd0;
reg [15:0] dac_dds_phase_2_1 = 'd0;
reg [15:0] dac_dds_phase_3_0 = 'd0;
reg [15:0] dac_dds_phase_3_1 = 'd0;
reg [15:0] dac_dds_incr_0 = 'd0;
reg [15:0] dac_dds_incr_1 = 'd0;
reg [63:0] dac_dds_data = 'd0;
// internal signals
wire [15:0] dac_dds_data_0_s;
wire [15:0] dac_dds_data_1_s;
wire [15:0] dac_dds_data_2_s;
wire [15:0] dac_dds_data_3_s;
wire [15:0] dac_dds_scale_1_s;
wire [15:0] dac_dds_init_1_s;
wire [15:0] dac_dds_incr_1_s;
wire [15:0] dac_dds_scale_2_s;
wire [15:0] dac_dds_init_2_s;
wire [15:0] dac_dds_incr_2_s;
wire [15:0] dac_pat_data_1_s;
wire [15:0] dac_pat_data_2_s;
wire [ 3:0] dac_data_sel_s;
// pn7 function
function [63:0] pn7;
input [63:0] din;
reg [63:0] dout;
begin
dout[63] = din[ 7] ^ din[ 6];
dout[62] = din[ 6] ^ din[ 5];
dout[61] = din[ 5] ^ din[ 4];
dout[60] = din[ 4] ^ din[ 3];
dout[59] = din[ 3] ^ din[ 2];
dout[58] = din[ 2] ^ din[ 1];
dout[57] = din[ 1] ^ din[ 0];
dout[56] = din[ 0] ^ din[ 7] ^ din[ 6];
dout[55] = din[ 7] ^ din[ 5];
dout[54] = din[ 6] ^ din[ 4];
dout[53] = din[ 5] ^ din[ 3];
dout[52] = din[ 4] ^ din[ 2];
dout[51] = din[ 3] ^ din[ 1];
dout[50] = din[ 2] ^ din[ 0];
dout[49] = din[ 1] ^ din[ 7] ^ din[ 6];
dout[48] = din[ 0] ^ din[ 6] ^ din[ 5];
dout[47] = din[ 7] ^ din[ 5] ^ din[ 6] ^ din[ 4];
dout[46] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 3];
dout[45] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 2];
dout[44] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 1];
dout[43] = din[ 3] ^ din[ 1] ^ din[ 2] ^ din[ 0];
dout[42] = din[ 2] ^ din[ 0] ^ din[ 1] ^ din[ 7] ^ din[ 6];
dout[41] = din[ 1] ^ din[ 7] ^ din[ 0] ^ din[ 5];
dout[40] = din[ 0] ^ din[ 7] ^ din[ 4];
dout[39] = din[ 7] ^ din[ 3];
dout[38] = din[ 6] ^ din[ 2];
dout[37] = din[ 5] ^ din[ 1];
dout[36] = din[ 4] ^ din[ 0];
dout[35] = din[ 3] ^ din[ 7] ^ din[ 6];
dout[34] = din[ 2] ^ din[ 6] ^ din[ 5];
dout[33] = din[ 1] ^ din[ 5] ^ din[ 4];
dout[32] = din[ 0] ^ din[ 4] ^ din[ 3];
dout[31] = din[ 7] ^ din[ 3] ^ din[ 6] ^ din[ 2];
dout[30] = din[ 6] ^ din[ 2] ^ din[ 5] ^ din[ 1];
dout[29] = din[ 5] ^ din[ 1] ^ din[ 4] ^ din[ 0];
dout[28] = din[ 4] ^ din[ 0] ^ din[ 3] ^ din[ 7] ^ din[ 6];
dout[27] = din[ 3] ^ din[ 7] ^ din[ 2] ^ din[ 5];
dout[26] = din[ 2] ^ din[ 6] ^ din[ 1] ^ din[ 4];
dout[25] = din[ 1] ^ din[ 5] ^ din[ 0] ^ din[ 3];
dout[24] = din[ 0] ^ din[ 4] ^ din[ 7] ^ din[ 6] ^ din[ 2];
dout[23] = din[ 7] ^ din[ 3] ^ din[ 5] ^ din[ 1];
dout[22] = din[ 6] ^ din[ 2] ^ din[ 4] ^ din[ 0];
dout[21] = din[ 5] ^ din[ 1] ^ din[ 3] ^ din[ 7] ^ din[ 6];
dout[20] = din[ 4] ^ din[ 0] ^ din[ 6] ^ din[ 2] ^ din[ 5];
dout[19] = din[ 3] ^ din[ 7] ^ din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 4];
dout[18] = din[ 2] ^ din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 3];
dout[17] = din[ 1] ^ din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 7] ^ din[ 6] ^ din[ 2];
dout[16] = din[ 0] ^ din[ 4] ^ din[ 6] ^ din[ 2] ^ din[ 3] ^ din[ 5] ^ din[ 1];
dout[15] = din[ 7] ^ din[ 3] ^ din[ 5] ^ din[ 1] ^ din[ 6] ^ din[ 2] ^ din[ 4] ^ din[ 0];
dout[14] = din[ 2] ^ din[ 4] ^ din[ 0] ^ din[ 5] ^ din[ 1] ^ din[ 3] ^ din[ 7];
dout[13] = din[ 1] ^ din[ 3] ^ din[ 7] ^ din[ 4] ^ din[ 0] ^ din[ 2];
dout[12] = din[ 0] ^ din[ 2] ^ din[ 3] ^ din[ 7] ^ din[ 1];
dout[11] = din[ 7] ^ din[ 1] ^ din[ 2] ^ din[ 0];
dout[10] = din[ 0] ^ din[ 1] ^ din[ 7];
dout[ 9] = din[ 7] ^ din[ 0];
dout[ 8] = din[ 7];
dout[ 7] = din[ 6];
dout[ 6] = din[ 5];
dout[ 5] = din[ 4];
dout[ 4] = din[ 3];
dout[ 3] = din[ 2];
dout[ 2] = din[ 1];
dout[ 1] = din[ 0];
dout[ 0] = din[ 7] ^ din[ 6];
pn7 = dout;
end
endfunction
// pn15 function
function [63:0] pn15;
input [63:0] din;
reg [63:0] dout;
begin
dout[63] = din[15] ^ din[14];
dout[62] = din[14] ^ din[13];
dout[61] = din[13] ^ din[12];
dout[60] = din[12] ^ din[11];
dout[59] = din[11] ^ din[10];
dout[58] = din[10] ^ din[ 9];
dout[57] = din[ 9] ^ din[ 8];
dout[56] = din[ 8] ^ din[ 7];
dout[55] = din[ 7] ^ din[ 6];
dout[54] = din[ 6] ^ din[ 5];
dout[53] = din[ 5] ^ din[ 4];
dout[52] = din[ 4] ^ din[ 3];
dout[51] = din[ 3] ^ din[ 2];
dout[50] = din[ 2] ^ din[ 1];
dout[49] = din[ 1] ^ din[ 0];
dout[48] = din[ 0] ^ din[15] ^ din[14];
dout[47] = din[15] ^ din[13];
dout[46] = din[14] ^ din[12];
dout[45] = din[13] ^ din[11];
dout[44] = din[12] ^ din[10];
dout[43] = din[11] ^ din[ 9];
dout[42] = din[10] ^ din[ 8];
dout[41] = din[ 9] ^ din[ 7];
dout[40] = din[ 8] ^ din[ 6];
dout[39] = din[ 7] ^ din[ 5];
dout[38] = din[ 6] ^ din[ 4];
dout[37] = din[ 5] ^ din[ 3];
dout[36] = din[ 4] ^ din[ 2];
dout[35] = din[ 3] ^ din[ 1];
dout[34] = din[ 2] ^ din[ 0];
dout[33] = din[ 1] ^ din[15] ^ din[14];
dout[32] = din[ 0] ^ din[14] ^ din[13];
dout[31] = din[15] ^ din[13] ^ din[14] ^ din[12];
dout[30] = din[14] ^ din[12] ^ din[13] ^ din[11];
dout[29] = din[13] ^ din[11] ^ din[12] ^ din[10];
dout[28] = din[12] ^ din[10] ^ din[11] ^ din[ 9];
dout[27] = din[11] ^ din[ 9] ^ din[10] ^ din[ 8];
dout[26] = din[10] ^ din[ 8] ^ din[ 9] ^ din[ 7];
dout[25] = din[ 9] ^ din[ 7] ^ din[ 8] ^ din[ 6];
dout[24] = din[ 8] ^ din[ 6] ^ din[ 7] ^ din[ 5];
dout[23] = din[ 7] ^ din[ 5] ^ din[ 6] ^ din[ 4];
dout[22] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 3];
dout[21] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 2];
dout[20] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 1];
dout[19] = din[ 3] ^ din[ 1] ^ din[ 2] ^ din[ 0];
dout[18] = din[ 2] ^ din[ 0] ^ din[ 1] ^ din[15] ^ din[14];
dout[17] = din[ 1] ^ din[15] ^ din[ 0] ^ din[13];
dout[16] = din[ 0] ^ din[15] ^ din[12];
dout[15] = din[15] ^ din[11];
dout[14] = din[14] ^ din[10];
dout[13] = din[13] ^ din[ 9];
dout[12] = din[12] ^ din[ 8];
dout[11] = din[11] ^ din[ 7];
dout[10] = din[10] ^ din[ 6];
dout[ 9] = din[ 9] ^ din[ 5];
dout[ 8] = din[ 8] ^ din[ 4];
dout[ 7] = din[ 7] ^ din[ 3];
dout[ 6] = din[ 6] ^ din[ 2];
dout[ 5] = din[ 5] ^ din[ 1];
dout[ 4] = din[ 4] ^ din[ 0];
dout[ 3] = din[ 3] ^ din[15] ^ din[14];
dout[ 2] = din[ 2] ^ din[14] ^ din[13];
dout[ 1] = din[ 1] ^ din[13] ^ din[12];
dout[ 0] = din[ 0] ^ din[12] ^ din[11];
pn15 = dout;
end
endfunction
// pn23 function
function [63:0] pn23;
input [63:0] din;
reg [63:0] dout;
begin
dout[63] = din[23] ^ din[18];
dout[62] = din[22] ^ din[17];
dout[61] = din[21] ^ din[16];
dout[60] = din[20] ^ din[15];
dout[59] = din[19] ^ din[14];
dout[58] = din[18] ^ din[13];
dout[57] = din[17] ^ din[12];
dout[56] = din[16] ^ din[11];
dout[55] = din[15] ^ din[10];
dout[54] = din[14] ^ din[ 9];
dout[53] = din[13] ^ din[ 8];
dout[52] = din[12] ^ din[ 7];
dout[51] = din[11] ^ din[ 6];
dout[50] = din[10] ^ din[ 5];
dout[49] = din[ 9] ^ din[ 4];
dout[48] = din[ 8] ^ din[ 3];
dout[47] = din[ 7] ^ din[ 2];
dout[46] = din[ 6] ^ din[ 1];
dout[45] = din[ 5] ^ din[ 0];
dout[44] = din[ 4] ^ din[23] ^ din[18];
dout[43] = din[ 3] ^ din[22] ^ din[17];
dout[42] = din[ 2] ^ din[21] ^ din[16];
dout[41] = din[ 1] ^ din[20] ^ din[15];
dout[40] = din[ 0] ^ din[19] ^ din[14];
dout[39] = din[23] ^ din[13];
dout[38] = din[22] ^ din[12];
dout[37] = din[21] ^ din[11];
dout[36] = din[20] ^ din[10];
dout[35] = din[19] ^ din[ 9];
dout[34] = din[18] ^ din[ 8];
dout[33] = din[17] ^ din[ 7];
dout[32] = din[16] ^ din[ 6];
dout[31] = din[15] ^ din[ 5];
dout[30] = din[14] ^ din[ 4];
dout[29] = din[13] ^ din[ 3];
dout[28] = din[12] ^ din[ 2];
dout[27] = din[11] ^ din[ 1];
dout[26] = din[10] ^ din[ 0];
dout[25] = din[ 9] ^ din[23] ^ din[18];
dout[24] = din[ 8] ^ din[22] ^ din[17];
dout[23] = din[ 7] ^ din[21] ^ din[16];
dout[22] = din[ 6] ^ din[20] ^ din[15];
dout[21] = din[ 5] ^ din[19] ^ din[14];
dout[20] = din[ 4] ^ din[18] ^ din[13];
dout[19] = din[ 3] ^ din[17] ^ din[12];
dout[18] = din[ 2] ^ din[16] ^ din[11];
dout[17] = din[ 1] ^ din[15] ^ din[10];
dout[16] = din[ 0] ^ din[14] ^ din[ 9];
dout[15] = din[23] ^ din[13] ^ din[18] ^ din[ 8];
dout[14] = din[22] ^ din[12] ^ din[17] ^ din[ 7];
dout[13] = din[21] ^ din[11] ^ din[16] ^ din[ 6];
dout[12] = din[20] ^ din[10] ^ din[15] ^ din[ 5];
dout[11] = din[19] ^ din[ 9] ^ din[14] ^ din[ 4];
dout[10] = din[18] ^ din[ 8] ^ din[13] ^ din[ 3];
dout[ 9] = din[17] ^ din[ 7] ^ din[12] ^ din[ 2];
dout[ 8] = din[16] ^ din[ 6] ^ din[11] ^ din[ 1];
dout[ 7] = din[15] ^ din[ 5] ^ din[10] ^ din[ 0];
dout[ 6] = din[14] ^ din[ 4] ^ din[ 9] ^ din[23] ^ din[18];
dout[ 5] = din[13] ^ din[ 3] ^ din[ 8] ^ din[22] ^ din[17];
dout[ 4] = din[12] ^ din[ 2] ^ din[ 7] ^ din[21] ^ din[16];
dout[ 3] = din[11] ^ din[ 1] ^ din[ 6] ^ din[20] ^ din[15];
dout[ 2] = din[10] ^ din[ 0] ^ din[ 5] ^ din[19] ^ din[14];
dout[ 1] = din[ 9] ^ din[23] ^ din[ 4] ^ din[13];
dout[ 0] = din[ 8] ^ din[22] ^ din[ 3] ^ din[12];
pn23 = dout;
end
endfunction
// pn31 function
function [63:0] pn31;
input [63:0] din;
reg [63:0] dout;
begin
dout[63] = din[31] ^ din[28];
dout[62] = din[30] ^ din[27];
dout[61] = din[29] ^ din[26];
dout[60] = din[28] ^ din[25];
dout[59] = din[27] ^ din[24];
dout[58] = din[26] ^ din[23];
dout[57] = din[25] ^ din[22];
dout[56] = din[24] ^ din[21];
dout[55] = din[23] ^ din[20];
dout[54] = din[22] ^ din[19];
dout[53] = din[21] ^ din[18];
dout[52] = din[20] ^ din[17];
dout[51] = din[19] ^ din[16];
dout[50] = din[18] ^ din[15];
dout[49] = din[17] ^ din[14];
dout[48] = din[16] ^ din[13];
dout[47] = din[15] ^ din[12];
dout[46] = din[14] ^ din[11];
dout[45] = din[13] ^ din[10];
dout[44] = din[12] ^ din[ 9];
dout[43] = din[11] ^ din[ 8];
dout[42] = din[10] ^ din[ 7];
dout[41] = din[ 9] ^ din[ 6];
dout[40] = din[ 8] ^ din[ 5];
dout[39] = din[ 7] ^ din[ 4];
dout[38] = din[ 6] ^ din[ 3];
dout[37] = din[ 5] ^ din[ 2];
dout[36] = din[ 4] ^ din[ 1];
dout[35] = din[ 3] ^ din[ 0];
dout[34] = din[ 2] ^ din[31] ^ din[28];
dout[33] = din[ 1] ^ din[30] ^ din[27];
dout[32] = din[ 0] ^ din[29] ^ din[26];
dout[31] = din[31] ^ din[25];
dout[30] = din[30] ^ din[24];
dout[29] = din[29] ^ din[23];
dout[28] = din[28] ^ din[22];
dout[27] = din[27] ^ din[21];
dout[26] = din[26] ^ din[20];
dout[25] = din[25] ^ din[19];
dout[24] = din[24] ^ din[18];
dout[23] = din[23] ^ din[17];
dout[22] = din[22] ^ din[16];
dout[21] = din[21] ^ din[15];
dout[20] = din[20] ^ din[14];
dout[19] = din[19] ^ din[13];
dout[18] = din[18] ^ din[12];
dout[17] = din[17] ^ din[11];
dout[16] = din[16] ^ din[10];
dout[15] = din[15] ^ din[ 9];
dout[14] = din[14] ^ din[ 8];
dout[13] = din[13] ^ din[ 7];
dout[12] = din[12] ^ din[ 6];
dout[11] = din[11] ^ din[ 5];
dout[10] = din[10] ^ din[ 4];
dout[ 9] = din[ 9] ^ din[ 3];
dout[ 8] = din[ 8] ^ din[ 2];
dout[ 7] = din[ 7] ^ din[ 1];
dout[ 6] = din[ 6] ^ din[ 0];
dout[ 5] = din[ 5] ^ din[31] ^ din[28];
dout[ 4] = din[ 4] ^ din[30] ^ din[27];
dout[ 3] = din[ 3] ^ din[29] ^ din[26];
dout[ 2] = din[ 2] ^ din[28] ^ din[25];
dout[ 1] = din[ 1] ^ din[27] ^ din[24];
dout[ 0] = din[ 0] ^ din[26] ^ din[23];
pn31 = dout;
end
endfunction
// dac data select
always @(posedge dac_clk) begin
dac_enable <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0;
case (dac_data_sel_s)
4'h7: dac_data <= dac_pn31_data;
4'h6: dac_data <= dac_pn23_data;
4'h5: dac_data <= dac_pn15_data;
4'h4: dac_data <= dac_pn7_data;
4'h3: dac_data <= 64'd0;
4'h2: dac_data <= dma_data;
4'h1: dac_data <= { dac_pat_data_2_s, dac_pat_data_1_s,
dac_pat_data_2_s, dac_pat_data_1_s};
default: dac_data <= dac_dds_data;
endcase
end
// pn registers
always @(posedge dac_clk) begin
if (dac_data_sync == 1'b1) begin
dac_pn7_data <= {64{1'd1}};
dac_pn15_data <= {64{1'd1}};
dac_pn23_data <= {64{1'd1}};
dac_pn31_data <= {64{1'd1}};
end else begin
dac_pn7_data <= pn7(dac_pn7_data);
dac_pn15_data <= pn15(dac_pn15_data);
dac_pn23_data <= pn23(dac_pn23_data);
dac_pn31_data <= pn31(dac_pn31_data);
end
end
// dds
always @(posedge dac_clk) begin
if (dac_data_sync == 1'b1) begin
dac_dds_phase_0_0 <= dac_dds_init_1_s;
dac_dds_phase_0_1 <= dac_dds_init_2_s;
dac_dds_phase_1_0 <= dac_dds_phase_0_0 + dac_dds_incr_1_s;
dac_dds_phase_1_1 <= dac_dds_phase_0_1 + dac_dds_incr_2_s;
dac_dds_phase_2_0 <= dac_dds_phase_1_0 + dac_dds_incr_1_s;
dac_dds_phase_2_1 <= dac_dds_phase_1_1 + dac_dds_incr_2_s;
dac_dds_phase_3_0 <= dac_dds_phase_2_0 + dac_dds_incr_1_s;
dac_dds_phase_3_1 <= dac_dds_phase_2_1 + dac_dds_incr_2_s;
dac_dds_incr_0 <= {dac_dds_incr_1_s[13:0], 2'd0};
dac_dds_incr_1 <= {dac_dds_incr_2_s[13:0], 2'd0};
dac_dds_data <= 64'd0;
end else begin
dac_dds_phase_0_0 <= dac_dds_phase_0_0 + dac_dds_incr_0;
dac_dds_phase_0_1 <= dac_dds_phase_0_1 + dac_dds_incr_1;
dac_dds_phase_1_0 <= dac_dds_phase_1_0 + dac_dds_incr_0;
dac_dds_phase_1_1 <= dac_dds_phase_1_1 + dac_dds_incr_1;
dac_dds_phase_2_0 <= dac_dds_phase_2_0 + dac_dds_incr_0;
dac_dds_phase_2_1 <= dac_dds_phase_2_1 + dac_dds_incr_1;
dac_dds_phase_3_0 <= dac_dds_phase_3_0 + dac_dds_incr_0;
dac_dds_phase_3_1 <= dac_dds_phase_3_1 + dac_dds_incr_1;
dac_dds_incr_0 <= dac_dds_incr_0;
dac_dds_incr_1 <= dac_dds_incr_1;
dac_dds_data <= { dac_dds_data_3_s, dac_dds_data_2_s,
dac_dds_data_1_s, dac_dds_data_0_s};
end
end
generate
if (DP_DISABLE == 1) begin
assign dac_dds_data_0_s = 16'd0;
end else begin
ad_dds i_dds_0 (
.clk (dac_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_0_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_0_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_0_s));
end
endgenerate
generate
if (DP_DISABLE == 1) begin
assign dac_dds_data_1_s = 16'd0;
end else begin
ad_dds i_dds_1 (
.clk (dac_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_1_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_1_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_1_s));
end
endgenerate
generate
if (DP_DISABLE == 1) begin
assign dac_dds_data_2_s = 16'd0;
end else begin
ad_dds i_dds_2 (
.clk (dac_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_2_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_2_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_2_s));
end
endgenerate
generate
if (DP_DISABLE == 1) begin
assign dac_dds_data_3_s = 16'd0;
end else begin
ad_dds i_dds_3 (
.clk (dac_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_3_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_3_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_3_s));
end
endgenerate
// single channel processor
up_dac_channel #(.PCORE_DAC_CHID(CHID)) i_up_dac_channel (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_dds_scale_1 (dac_dds_scale_1_s),
.dac_dds_init_1 (dac_dds_init_1_s),
.dac_dds_incr_1 (dac_dds_incr_1_s),
.dac_dds_scale_2 (dac_dds_scale_2_s),
.dac_dds_init_2 (dac_dds_init_2_s),
.dac_dds_incr_2 (dac_dds_incr_2_s),
.dac_pat_data_1 (dac_pat_data_1_s),
.dac_pat_data_2 (dac_pat_data_2_s),
.dac_data_sel (dac_data_sel_s),
.dac_iqcor_enb (),
.dac_iqcor_coeff_1 (),
.dac_iqcor_coeff_2 (),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),
.up_usr_datatype_total_bits (),
.up_usr_datatype_bits (),
.up_usr_interpolation_m (),
.up_usr_interpolation_n (),
.dac_usr_datatype_be (1'b0),
.dac_usr_datatype_signed (1'b1),
.dac_usr_datatype_shift (8'd0),
.dac_usr_datatype_total_bits (8'd16),
.dac_usr_datatype_bits (8'd16),
.dac_usr_interpolation_m (16'd1),
.dac_usr_interpolation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************

6
library/axi_ad9152/axi_ad9152_constr.xdc Normal file
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@ -0,0 +1,6 @@
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports tx_clk]]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports s_axi_aclk]]

250
library/axi_ad9152/axi_ad9152_core.v Normal file
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@ -0,0 +1,250 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9152_core (
// dac interface
dac_clk,
dac_rst,
dac_data_0_0,
dac_data_0_1,
dac_data_0_2,
dac_data_0_3,
dac_data_1_0,
dac_data_1_1,
dac_data_1_2,
dac_data_1_3,
// dma interface
dac_valid_0,
dac_enable_0,
dac_ddata_0,
dac_valid_1,
dac_enable_1,
dac_ddata_1,
dac_dovf,
dac_dunf,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
parameter PCORE_ID = 0;
parameter DP_DISABLE = 0;
// dac interface
input dac_clk;
output dac_rst;
output [15:0] dac_data_0_0;
output [15:0] dac_data_0_1;
output [15:0] dac_data_0_2;
output [15:0] dac_data_0_3;
output [15:0] dac_data_1_0;
output [15:0] dac_data_1_1;
output [15:0] dac_data_1_2;
output [15:0] dac_data_1_3;
// dma interface
output dac_valid_0;
output dac_enable_0;
input [63:0] dac_ddata_0;
output dac_valid_1;
output dac_enable_1;
input [63:0] dac_ddata_1;
input dac_dovf;
input dac_dunf;
// processor interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal registers
reg [31:0] up_rdata = 'd0;
reg up_rack = 'd0;
reg up_wack = 'd0;
// internal signals
wire dac_sync_s;
wire dac_datafmt_s;
wire [31:0] up_rdata_0_s;
wire up_rack_0_s;
wire up_wack_0_s;
wire [31:0] up_rdata_1_s;
wire up_rack_1_s;
wire up_wack_1_s;
wire [31:0] up_rdata_s;
wire up_rack_s;
wire up_wack_s;
// dac valid
assign dac_valid_0 = 1'b1;
assign dac_valid_1 = 1'b1;
assign dac_valid_2 = 1'b1;
assign dac_valid_3 = 1'b1;
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rdata <= 'd0;
up_rack <= 'd0;
up_wack <= 'd0;
end else begin
up_rdata <= up_rdata_s | up_rdata_0_s | up_rdata_1_s;
up_rack <= up_rack_s | up_rack_0_s | up_rack_1_s;
up_wack <= up_wack_s | up_wack_0_s | up_wack_1_s;
end
end
// dac channel
axi_ad9152_channel #(.CHID(0), .DP_DISABLE(DP_DISABLE)) i_channel_0 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_enable (dac_enable_0),
.dac_data ({dac_data_0_3, dac_data_0_2, dac_data_0_1, dac_data_0_0}),
.dma_data (dac_ddata_0),
.dac_data_sync (dac_sync_s),
.dac_dds_format (dac_datafmt_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_0_s),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_0_s),
.up_rack (up_rack_0_s));
// dac channel
axi_ad9152_channel #(.CHID(1), .DP_DISABLE(DP_DISABLE)) i_channel_1 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_enable (dac_enable_1),
.dac_data ({dac_data_1_3, dac_data_1_2, dac_data_1_1, dac_data_1_0}),
.dma_data (dac_ddata_1),
.dac_data_sync (dac_sync_s),
.dac_dds_format (dac_datafmt_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_1_s),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_1_s),
.up_rack (up_rack_1_s));
// dac common processor interface
up_dac_common #(.PCORE_ID(PCORE_ID)) i_up_dac_common (
.mmcm_rst (),
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_sync (dac_sync_s),
.dac_frame (),
.dac_par_type (),
.dac_par_enb (),
.dac_r1_mode (),
.dac_datafmt (dac_datafmt_s),
.dac_datarate (),
.dac_status (1'b1),
.dac_status_ovf (dac_dovf),
.dac_status_unf (dac_dunf),
.dac_clk_ratio (32'd40),
.drp_clk (up_clk),
.drp_rst (),
.drp_sel (),
.drp_wr (),
.drp_addr (),
.drp_wdata (),
.drp_rdata (16'd0),
.drp_ready (1'd0),
.drp_locked (1'd1),
.up_usr_chanmax (),
.dac_usr_chanmax (8'd3),
.up_dac_gpio_in (32'd0),
.up_dac_gpio_out (),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s),
.up_rack (up_rack_s));
endmodule
// ***************************************************************************
// ***************************************************************************

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library/axi_ad9152/axi_ad9152_if.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// This is the dac physical interface (drives samples from the low speed clock to the
// dac clock domain.
`timescale 1ns/100ps
module axi_ad9152_if (
// jesd interface
// tx_clk is (line-rate/40)
tx_clk,
tx_data,
// dac interface
dac_clk,
dac_rst,
dac_data_0_0,
dac_data_0_1,
dac_data_0_2,
dac_data_0_3,
dac_data_1_0,
dac_data_1_1,
dac_data_1_2,
dac_data_1_3);
// jesd interface
// tx_clk is (line-rate/40)
input tx_clk;
output [127:0] tx_data;
// dac interface
output dac_clk;
input dac_rst;
input [15:0] dac_data_0_0;
input [15:0] dac_data_0_1;
input [15:0] dac_data_0_2;
input [15:0] dac_data_0_3;
input [15:0] dac_data_1_0;
input [15:0] dac_data_1_1;
input [15:0] dac_data_1_2;
input [15:0] dac_data_1_3;
// internal registers
reg [127:0] tx_data = 'd0;
// reorder data for the jesd links
assign dac_clk = tx_clk;
always @(posedge dac_clk) begin
if (dac_rst == 1'b1) begin
tx_data <= 128'd0;
end else begin
tx_data[127:120] <= dac_data_1_3[ 7: 0];
tx_data[119:112] <= dac_data_1_2[ 7: 0];
tx_data[111:104] <= dac_data_1_1[ 7: 0];
tx_data[103: 96] <= dac_data_1_0[ 7: 0];
tx_data[ 95: 88] <= dac_data_1_3[15: 8];
tx_data[ 87: 80] <= dac_data_1_2[15: 8];
tx_data[ 79: 72] <= dac_data_1_1[15: 8];
tx_data[ 71: 64] <= dac_data_1_0[15: 8];
tx_data[ 63: 56] <= dac_data_0_3[ 7: 0];
tx_data[ 55: 48] <= dac_data_0_2[ 7: 0];
tx_data[ 47: 40] <= dac_data_0_1[ 7: 0];
tx_data[ 39: 32] <= dac_data_0_0[ 7: 0];
tx_data[ 31: 24] <= dac_data_0_3[15: 8];
tx_data[ 23: 16] <= dac_data_0_2[15: 8];
tx_data[ 15: 8] <= dac_data_0_1[15: 8];
tx_data[ 7: 0] <= dac_data_0_0[15: 8];
end
end
endmodule
// ***************************************************************************
// ***************************************************************************

30
library/axi_ad9152/axi_ad9152_ip.tcl Normal file
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@ -0,0 +1,30 @@
# ip
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_ad9152
adi_ip_files axi_ad9152 [list \
"$ad_hdl_dir/library/common/ad_mul.v" \
"$ad_hdl_dir/library/common/ad_dds_sine.v" \
"$ad_hdl_dir/library/common/ad_dds_1.v" \
"$ad_hdl_dir/library/common/ad_dds.v" \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_drp_cntrl.v" \
"$ad_hdl_dir/library/common/up_dac_common.v" \
"$ad_hdl_dir/library/common/up_dac_channel.v" \
"axi_ad9152_channel.v" \
"axi_ad9152_core.v" \
"axi_ad9152_if.v" \
"axi_ad9152.v" ]
adi_ip_properties axi_ad9152
adi_ip_constraints axi_ad9152 [list \
"axi_ad9152_constr.xdc" ]
ipx::save_core [ipx::current_core]

63
library/axi_ad9234/axi_ad9234.v
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@ -132,7 +132,8 @@ module axi_ad9234 (
reg up_status_pn_oos = 'd0;
reg up_status_or = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_ack = 'd0;
reg up_rack = 'd0;
reg up_wack = 'd0;
// internal clocks & resets
@ -142,8 +143,8 @@ module axi_ad9234 (
// internal signals
wire [55:0] adc_data_a_s;
wire [55:0] adc_data_b_s;
wire [63:0] adc_data_a_s;
wire [63:0] adc_data_b_s;
wire adc_or_a_s;
wire adc_or_b_s;
wire adc_status_s;
@ -151,11 +152,13 @@ module axi_ad9234 (
wire [ 1:0] up_adc_pn_oos_s;
wire [ 1:0] up_adc_or_s;
wire [31:0] up_rdata_s[0:2];
wire up_ack_s[0:2];
wire up_sel_s;
wire up_wr_s;
wire [13:0] up_addr_s;
wire up_rack_s[0:2];
wire up_wack_s[0:2];
wire up_wreq_s;
wire [13:0] up_waddr_s;
wire [31:0] up_wdata_s;
wire up_rreq_s;
wire [13:0] up_raddr_s;
// signal name changes
@ -175,13 +178,15 @@ module axi_ad9234 (
up_status_pn_oos <= 'd0;
up_status_or <= 'd0;
up_rdata <= 'd0;
up_ack <= 'd0;
up_rack <= 'd0;
up_wack <= 'd0;
end else begin
up_status_pn_err <= | up_adc_pn_err_s;
up_status_pn_oos <= | up_adc_pn_oos_s;
up_status_or <= | up_adc_or_s;
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2];
up_ack <= up_ack_s[0] | up_ack_s[1] | up_ack_s[2];
up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2];
up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2];
end
end
@ -212,12 +217,14 @@ module axi_ad9234 (
.up_adc_or (up_adc_or_s[0]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[0]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[0]),
.up_ack (up_ack_s[0]));
.up_rack (up_rack_s[0]));
// channel
@ -233,12 +240,14 @@ module axi_ad9234 (
.up_adc_or (up_adc_or_s[1]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[1]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[1]),
.up_ack (up_ack_s[1]));
.up_rack (up_rack_s[1]));
// common processor control
@ -280,12 +289,14 @@ module axi_ad9234 (
.up_adc_gpio_out (),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[2]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[2]),
.up_ack (up_ack_s[2]));
.up_rack (up_rack_s[2]));
// up bus interface
@ -309,12 +320,14 @@ module axi_ad9234 (
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata),
.up_ack (up_ack));
.up_rack (up_rack));
endmodule

56
library/axi_ad9234/axi_ad9234_channel.v
View File

@ -61,12 +61,14 @@ module axi_ad9234_channel (
up_rstn,
up_clk,
up_sel,
up_wr,
up_addr,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_ack);
up_rack);
// parameters
@ -77,7 +79,7 @@ module axi_ad9234_channel (
input adc_clk;
input adc_rst;
input [55:0] adc_data;
input [63:0] adc_data;
input adc_or;
// channel interface
@ -92,20 +94,19 @@ module axi_ad9234_channel (
input up_rstn;
input up_clk;
input up_sel;
input up_wr;
input [13:0] up_addr;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_ack;
output up_rack;
// internal signals
wire adc_pn_oos_s;
wire adc_pn_err_s;
wire adc_dfmt_enable_s;
wire adc_dfmt_type_s;
wire adc_dfmt_se_s;
wire [ 3:0] adc_pnseq_sel_s;
// instantiations
@ -117,20 +118,7 @@ module axi_ad9234_channel (
.adc_pn_err (adc_pn_err_s),
.adc_pnseq_sel (adc_pnseq_sel_s));
genvar n;
generate
for (n = 0; n < 4; n = n + 1) begin: g_ad_datafmt_1
ad_datafmt #(.DATA_WIDTH(14)) i_ad_datafmt (
.clk (adc_clk),
.valid (1'b1),
.data (adc_data[n*14+13:n*14]),
.valid_out (),
.data_out (adc_dfmt_data[n*16+15:n*16]),
.dfmt_enable (adc_dfmt_enable_s),
.dfmt_type (adc_dfmt_type_s),
.dfmt_se (adc_dfmt_se_s));
end
endgenerate
assign adc_dfmt_data = adc_data;
up_adc_channel #(.PCORE_ADC_CHID(CHID)) i_up_adc_channel (
.adc_clk (adc_clk),
@ -138,9 +126,9 @@ module axi_ad9234_channel (
.adc_enable (adc_enable),
.adc_iqcor_enb (),
.adc_dcfilt_enb (),
.adc_dfmt_se (adc_dfmt_se_s),
.adc_dfmt_type (adc_dfmt_type_s),
.adc_dfmt_enable (adc_dfmt_enable_s),
.adc_dfmt_se (),
.adc_dfmt_type (),
.adc_dfmt_enable (),
.adc_dcfilt_offset (),
.adc_dcfilt_coeff (),
.adc_iqcor_coeff_1 (),
@ -169,12 +157,14 @@ module axi_ad9234_channel (
.adc_usr_decimation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),
.up_wr (up_wr),
.up_addr (up_addr),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_ack (up_ack));
.up_rack (up_rack));
endmodule

4
library/axi_ad9234/axi_ad9234_constr.xdc
View File

@ -1,6 +1,4 @@
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports adc_clk]]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports s_axi_aclk]]

28
library/axi_ad9234/axi_ad9234_if.v
View File

@ -68,8 +68,8 @@ module axi_ad9234_if (
output adc_clk;
input adc_rst;
output [55:0] adc_data_a;
output [55:0] adc_data_b;
output [63:0] adc_data_a;
output [63:0] adc_data_b;
output adc_or_a;
output adc_or_b;
output adc_status;
@ -97,23 +97,23 @@ module axi_ad9234_if (
// adc channels
assign adc_data_a = { adc_data_a_s3_s[13:0], adc_data_a_s2_s[13:0],
adc_data_a_s1_s[13:0], adc_data_a_s0_s[13:0]};
assign adc_data_a = { adc_data_a_s3_s, adc_data_a_s2_s,
adc_data_a_s1_s, adc_data_a_s0_s};
assign adc_data_b = { adc_data_b_s3_s[13:0], adc_data_b_s2_s[13:0],
adc_data_b_s1_s[13:0], adc_data_b_s0_s[13:0]};
assign adc_data_b = { adc_data_b_s3_s, adc_data_b_s2_s,
adc_data_b_s1_s, adc_data_b_s0_s};
// data multiplex
assign adc_data_a_s3_s = {rx_data[ 57: 56], rx_data[ 31: 24], rx_data[ 63: 58]};
assign adc_data_a_s2_s = {rx_data[ 49: 48], rx_data[ 23: 16], rx_data[ 55: 50]};
assign adc_data_a_s1_s = {rx_data[ 41: 40], rx_data[ 15: 8], rx_data[ 47: 42]};
assign adc_data_a_s0_s = {rx_data[ 33: 32], rx_data[ 7: 0], rx_data[ 39: 34]};
assign adc_data_a_s3_s = {rx_data[ 31: 24], rx_data[ 63: 56]};
assign adc_data_a_s2_s = {rx_data[ 23: 16], rx_data[ 55: 48]};
assign adc_data_a_s1_s = {rx_data[ 15: 8], rx_data[ 47: 40]};
assign adc_data_a_s0_s = {rx_data[ 7: 0], rx_data[ 39: 32]};
assign adc_data_b_s3_s = {rx_data[121:120], rx_data[ 95: 88], rx_data[127:122]};
assign adc_data_b_s2_s = {rx_data[113:112], rx_data[ 87: 80], rx_data[119:114]};
assign adc_data_b_s1_s = {rx_data[105:104], rx_data[ 79: 72], rx_data[111:106]};
assign adc_data_b_s0_s = {rx_data[ 97: 96], rx_data[ 71: 64], rx_data[103: 98]};
assign adc_data_b_s3_s = {rx_data[ 95: 88], rx_data[127:120]};
assign adc_data_b_s2_s = {rx_data[ 87: 80], rx_data[119:112]};
assign adc_data_b_s1_s = {rx_data[ 79: 72], rx_data[111:104]};
assign adc_data_b_s0_s = {rx_data[ 71: 64], rx_data[103: 96]};
// status

3
library/axi_ad9234/axi_ad9234_ip.tcl
View File

@ -19,7 +19,8 @@ adi_ip_files axi_ad9234 [list \
"axi_ad9234_pnmon.v" \
"axi_ad9234_channel.v" \
"axi_ad9234_if.v" \
"axi_ad9234.v" ]
"axi_ad9234.v" \
"axi_ad9234_constr.xdc" ]
adi_ip_properties axi_ad9234
adi_ip_constraints axi_ad9234 [list \

270
library/axi_ad9234/axi_ad9234_pnmon.v
View File

@ -59,7 +59,7 @@ module axi_ad9234_pnmon (
// adc interface
input adc_clk;
input [55:0] adc_data;
input [63:0] adc_data;
// pn out of sync and error
@ -72,141 +72,157 @@ module axi_ad9234_pnmon (
// internal registers
reg [55:0] adc_pn_data_in = 'd0;
reg [55:0] adc_pn_data_pn = 'd0;
reg [63:0] adc_pn_data_in = 'd0;
reg [63:0] adc_pn_data_pn = 'd0;
// internal signals
wire [55:0] adc_pn_data_pn_s;
wire [63:0] adc_pn_data_pn_s;
// PN23 function
function [55:0] pn23;
input [55:0] din;
reg [55:0] dout;
function [63:0] pn23;
input [63:0] din;
reg [63:0] dout;
begin
dout[55] = din[22] ^ din[17];
dout[54] = din[21] ^ din[16];
dout[53] = din[20] ^ din[15];
dout[52] = din[19] ^ din[14];
dout[51] = din[18] ^ din[13];
dout[50] = din[17] ^ din[12];
dout[49] = din[16] ^ din[11];
dout[48] = din[15] ^ din[10];
dout[47] = din[14] ^ din[ 9];
dout[46] = din[13] ^ din[ 8];
dout[45] = din[12] ^ din[ 7];
dout[44] = din[11] ^ din[ 6];
dout[43] = din[10] ^ din[ 5];
dout[42] = din[ 9] ^ din[ 4];
dout[41] = din[ 8] ^ din[ 3];
dout[40] = din[ 7] ^ din[ 2];
dout[39] = din[ 6] ^ din[ 1];
dout[38] = din[ 5] ^ din[ 0];
dout[37] = din[ 4] ^ din[22] ^ din[17];
dout[36] = din[ 3] ^ din[21] ^ din[16];
dout[35] = din[ 2] ^ din[20] ^ din[15];
dout[34] = din[ 1] ^ din[19] ^ din[14];
dout[33] = din[ 0] ^ din[18] ^ din[13];
dout[32] = din[22] ^ din[12];
dout[31] = din[21] ^ din[11];
dout[30] = din[20] ^ din[10];
dout[29] = din[19] ^ din[ 9];
dout[28] = din[18] ^ din[ 8];
dout[27] = din[17] ^ din[ 7];
dout[26] = din[16] ^ din[ 6];
dout[25] = din[15] ^ din[ 5];
dout[24] = din[14] ^ din[ 4];
dout[23] = din[13] ^ din[ 3];
dout[22] = din[12] ^ din[ 2];
dout[21] = din[11] ^ din[ 1];
dout[20] = din[10] ^ din[ 0];
dout[19] = din[ 9] ^ din[22] ^ din[17];
dout[18] = din[ 8] ^ din[21] ^ din[16];
dout[17] = din[ 7] ^ din[20] ^ din[15];
dout[16] = din[ 6] ^ din[19] ^ din[14];
dout[15] = din[ 5] ^ din[18] ^ din[13];
dout[14] = din[ 4] ^ din[17] ^ din[12];
dout[13] = din[ 3] ^ din[16] ^ din[11];
dout[12] = din[ 2] ^ din[15] ^ din[10];
dout[11] = din[ 1] ^ din[14] ^ din[ 9];
dout[10] = din[ 0] ^ din[13] ^ din[ 8];
dout[ 9] = din[22] ^ din[12] ^ din[17] ^ din[ 7];
dout[ 8] = din[21] ^ din[11] ^ din[16] ^ din[ 6];
dout[ 7] = din[20] ^ din[10] ^ din[15] ^ din[ 5];
dout[ 6] = din[19] ^ din[ 9] ^ din[14] ^ din[ 4];
dout[ 5] = din[18] ^ din[ 8] ^ din[13] ^ din[ 3];
dout[ 4] = din[17] ^ din[ 7] ^ din[12] ^ din[ 2];
dout[ 3] = din[16] ^ din[ 6] ^ din[11] ^ din[ 1];
dout[ 2] = din[15] ^ din[ 5] ^ din[10] ^ din[ 0];
dout[ 1] = din[14] ^ din[ 4] ^ din[ 9] ^ din[22] ^ din[17];
dout[ 0] = din[13] ^ din[ 3] ^ din[ 8] ^ din[21] ^ din[16];
dout[63] = din[22] ^ din[17];
dout[62] = din[21] ^ din[16];
dout[61] = din[20] ^ din[15];
dout[60] = din[19] ^ din[14];
dout[59] = din[18] ^ din[13];
dout[58] = din[17] ^ din[12];
dout[57] = din[16] ^ din[11];
dout[56] = din[15] ^ din[10];
dout[55] = din[14] ^ din[ 9];
dout[54] = din[13] ^ din[ 8];
dout[53] = din[12] ^ din[ 7];
dout[52] = din[11] ^ din[ 6];
dout[51] = din[10] ^ din[ 5];
dout[50] = din[ 9] ^ din[ 4];
dout[49] = din[ 8] ^ din[ 3];
dout[48] = din[ 7] ^ din[ 2];
dout[47] = din[ 6] ^ din[ 1];
dout[46] = din[ 5] ^ din[ 0];
dout[45] = din[ 4] ^ din[22] ^ din[17];
dout[44] = din[ 3] ^ din[21] ^ din[16];
dout[43] = din[ 2] ^ din[20] ^ din[15];
dout[42] = din[ 1] ^ din[19] ^ din[14];
dout[41] = din[ 0] ^ din[18] ^ din[13];
dout[40] = din[22] ^ din[12];
dout[39] = din[21] ^ din[11];
dout[38] = din[20] ^ din[10];
dout[37] = din[19] ^ din[ 9];
dout[36] = din[18] ^ din[ 8];
dout[35] = din[17] ^ din[ 7];
dout[34] = din[16] ^ din[ 6];
dout[33] = din[15] ^ din[ 5];
dout[32] = din[14] ^ din[ 4];
dout[31] = din[13] ^ din[ 3];
dout[30] = din[12] ^ din[ 2];
dout[29] = din[11] ^ din[ 1];
dout[28] = din[10] ^ din[ 0];
dout[27] = din[ 9] ^ din[22] ^ din[17];
dout[26] = din[ 8] ^ din[21] ^ din[16];
dout[25] = din[ 7] ^ din[20] ^ din[15];
dout[24] = din[ 6] ^ din[19] ^ din[14];
dout[23] = din[ 5] ^ din[18] ^ din[13];
dout[22] = din[ 4] ^ din[17] ^ din[12];
dout[21] = din[ 3] ^ din[16] ^ din[11];
dout[20] = din[ 2] ^ din[15] ^ din[10];
dout[19] = din[ 1] ^ din[14] ^ din[ 9];
dout[18] = din[ 0] ^ din[13] ^ din[ 8];
dout[17] = din[22] ^ din[12] ^ din[17] ^ din[ 7];
dout[16] = din[21] ^ din[11] ^ din[16] ^ din[ 6];
dout[15] = din[20] ^ din[10] ^ din[15] ^ din[ 5];
dout[14] = din[19] ^ din[ 9] ^ din[14] ^ din[ 4];
dout[13] = din[18] ^ din[ 8] ^ din[13] ^ din[ 3];
dout[12] = din[17] ^ din[ 7] ^ din[12] ^ din[ 2];
dout[11] = din[16] ^ din[ 6] ^ din[11] ^ din[ 1];
dout[10] = din[15] ^ din[ 5] ^ din[10] ^ din[ 0];
dout[ 9] = din[14] ^ din[ 4] ^ din[ 9] ^ din[22] ^ din[17];
dout[ 8] = din[13] ^ din[ 3] ^ din[ 8] ^ din[21] ^ din[16];
dout[ 7] = din[12] ^ din[ 2] ^ din[ 7] ^ din[20] ^ din[15];
dout[ 6] = din[11] ^ din[ 1] ^ din[ 6] ^ din[19] ^ din[14];
dout[ 5] = din[10] ^ din[ 0] ^ din[ 5] ^ din[18] ^ din[13];
dout[ 4] = din[ 9] ^ din[22] ^ din[ 4] ^ din[12];
dout[ 3] = din[ 8] ^ din[21] ^ din[ 3] ^ din[11];
dout[ 2] = din[ 7] ^ din[20] ^ din[ 2] ^ din[10];
dout[ 1] = din[ 6] ^ din[19] ^ din[ 1] ^ din[ 9];
dout[ 0] = din[ 5] ^ din[18] ^ din[ 0] ^ din[ 8];
pn23 = dout;
end
endfunction
// PN9 function
function [55:0] pn9;
input [55:0] din;
reg [55:0] dout;
function [63:0] pn9;
input [63:0] din;
reg [63:0] dout;
begin
dout[55] = din[ 8] ^ din[ 4];
dout[54] = din[ 7] ^ din[ 3];
dout[53] = din[ 6] ^ din[ 2];
dout[52] = din[ 5] ^ din[ 1];
dout[51] = din[ 4] ^ din[ 0];
dout[50] = din[ 3] ^ din[ 8] ^ din[ 4];
dout[49] = din[ 2] ^ din[ 7] ^ din[ 3];
dout[48] = din[ 1] ^ din[ 6] ^ din[ 2];
dout[47] = din[ 0] ^ din[ 5] ^ din[ 1];
dout[46] = din[ 8] ^ din[ 0];
dout[45] = din[ 7] ^ din[ 8] ^ din[ 4];
dout[44] = din[ 6] ^ din[ 7] ^ din[ 3];
dout[43] = din[ 5] ^ din[ 6] ^ din[ 2];
dout[42] = din[ 4] ^ din[ 5] ^ din[ 1];
dout[41] = din[ 3] ^ din[ 4] ^ din[ 0];
dout[40] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4];
dout[39] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3];
dout[38] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2];
dout[37] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1];
dout[36] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0];
dout[35] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4];
dout[34] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3];
dout[33] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2];
dout[32] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1];
dout[31] = din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 0];
dout[30] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 4];
dout[29] = din[ 0] ^ din[ 2] ^ din[ 5] ^ din[ 7] ^ din[ 3];
dout[28] = din[ 8] ^ din[ 1] ^ din[ 6] ^ din[ 2];
dout[27] = din[ 7] ^ din[ 0] ^ din[ 5] ^ din[ 1];
dout[26] = din[ 6] ^ din[ 8] ^ din[ 0];
dout[25] = din[ 5] ^ din[ 7] ^ din[ 8] ^ din[ 4];
dout[24] = din[ 4] ^ din[ 6] ^ din[ 7] ^ din[ 3];
dout[23] = din[ 3] ^ din[ 5] ^ din[ 6] ^ din[ 2];
dout[22] = din[ 2] ^ din[ 4] ^ din[ 5] ^ din[ 1];
dout[21] = din[ 1] ^ din[ 3] ^ din[ 4] ^ din[ 0];
dout[20] = din[ 0] ^ din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4];
dout[19] = din[ 8] ^ din[ 1] ^ din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 3];
dout[18] = din[ 7] ^ din[ 0] ^ din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 2];
dout[17] = din[ 6] ^ din[ 8] ^ din[ 0] ^ din[ 2] ^ din[ 4] ^ din[ 5] ^ din[ 1];
dout[16] = din[ 5] ^ din[ 7] ^ din[ 8] ^ din[ 1] ^ din[ 3] ^ din[ 0];
dout[15] = din[ 6] ^ din[ 7] ^ din[ 0] ^ din[ 2] ^ din[ 8];
dout[14] = din[ 5] ^ din[ 6] ^ din[ 8] ^ din[ 1] ^ din[ 4] ^ din[ 7];
dout[13] = din[ 4] ^ din[ 5] ^ din[ 7] ^ din[ 0] ^ din[ 3] ^ din[ 6];
dout[12] = din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 2] ^ din[ 5];
dout[11] = din[ 2] ^ din[ 4] ^ din[ 5] ^ din[ 7] ^ din[ 1];
dout[10] = din[ 1] ^ din[ 4] ^ din[ 3] ^ din[ 6] ^ din[ 0];
dout[ 9] = din[ 0] ^ din[ 3] ^ din[ 2] ^ din[ 5] ^ din[ 8] ^ din[ 4];
dout[ 8] = din[ 8] ^ din[ 2] ^ din[ 1] ^ din[ 7] ^ din[ 3];
dout[ 7] = din[ 7] ^ din[ 1] ^ din[ 0] ^ din[ 6] ^ din[ 2];
dout[ 6] = din[ 6] ^ din[ 0] ^ din[ 8] ^ din[ 4] ^ din[ 5] ^ din[ 1];
dout[ 5] = din[ 5] ^ din[ 8] ^ din[ 7] ^ din[ 3] ^ din[ 0];
dout[ 4] = din[ 7] ^ din[ 6] ^ din[ 2] ^ din[ 8];
dout[ 3] = din[ 6] ^ din[ 5] ^ din[ 1] ^ din[ 7];
dout[ 2] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6];
dout[ 1] = din[ 3] ^ din[ 8] ^ din[ 5];
dout[ 0] = din[ 2] ^ din[ 4] ^ din[ 7];
dout[63] = din[ 8] ^ din[ 4];
dout[62] = din[ 7] ^ din[ 3];
dout[61] = din[ 6] ^ din[ 2];
dout[60] = din[ 5] ^ din[ 1];
dout[59] = din[ 4] ^ din[ 0];
dout[58] = din[ 3] ^ din[ 8] ^ din[ 4];
dout[57] = din[ 2] ^ din[ 7] ^ din[ 3];
dout[56] = din[ 1] ^ din[ 6] ^ din[ 2];
dout[55] = din[ 0] ^ din[ 5] ^ din[ 1];
dout[54] = din[ 8] ^ din[ 0];
dout[53] = din[ 7] ^ din[ 8] ^ din[ 4];
dout[52] = din[ 6] ^ din[ 7] ^ din[ 3];
dout[51] = din[ 5] ^ din[ 6] ^ din[ 2];
dout[50] = din[ 4] ^ din[ 5] ^ din[ 1];
dout[49] = din[ 3] ^ din[ 4] ^ din[ 0];
dout[48] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4];
dout[47] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3];
dout[46] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2];
dout[45] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1];
dout[44] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0];
dout[43] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4];
dout[42] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3];
dout[41] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2];
dout[40] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1];
dout[39] = din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 0];
dout[38] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 4];
dout[37] = din[ 0] ^ din[ 2] ^ din[ 5] ^ din[ 7] ^ din[ 3];
dout[36] = din[ 8] ^ din[ 1] ^ din[ 6] ^ din[ 2];
dout[35] = din[ 7] ^ din[ 0] ^ din[ 5] ^ din[ 1];
dout[34] = din[ 6] ^ din[ 8] ^ din[ 0];
dout[33] = din[ 5] ^ din[ 7] ^ din[ 8] ^ din[ 4];
dout[32] = din[ 4] ^ din[ 6] ^ din[ 7] ^ din[ 3];
dout[31] = din[ 3] ^ din[ 5] ^ din[ 6] ^ din[ 2];
dout[30] = din[ 2] ^ din[ 4] ^ din[ 5] ^ din[ 1];
dout[29] = din[ 1] ^ din[ 3] ^ din[ 4] ^ din[ 0];
dout[28] = din[ 0] ^ din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4];
dout[27] = din[ 8] ^ din[ 1] ^ din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 3];
dout[26] = din[ 7] ^ din[ 0] ^ din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 2];
dout[25] = din[ 6] ^ din[ 8] ^ din[ 0] ^ din[ 2] ^ din[ 4] ^ din[ 5] ^ din[ 1];
dout[24] = din[ 5] ^ din[ 7] ^ din[ 8] ^ din[ 1] ^ din[ 3] ^ din[ 0];
dout[23] = din[ 6] ^ din[ 7] ^ din[ 0] ^ din[ 2] ^ din[ 8];
dout[22] = din[ 5] ^ din[ 6] ^ din[ 8] ^ din[ 1] ^ din[ 4] ^ din[ 7];
dout[21] = din[ 4] ^ din[ 5] ^ din[ 7] ^ din[ 0] ^ din[ 3] ^ din[ 6];
dout[20] = din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 2] ^ din[ 5];
dout[19] = din[ 2] ^ din[ 4] ^ din[ 5] ^ din[ 7] ^ din[ 1];
dout[18] = din[ 1] ^ din[ 4] ^ din[ 3] ^ din[ 6] ^ din[ 0];
dout[17] = din[ 0] ^ din[ 3] ^ din[ 2] ^ din[ 5] ^ din[ 8] ^ din[ 4];
dout[16] = din[ 8] ^ din[ 2] ^ din[ 1] ^ din[ 7] ^ din[ 3];
dout[15] = din[ 7] ^ din[ 1] ^ din[ 0] ^ din[ 6] ^ din[ 2];
dout[14] = din[ 6] ^ din[ 0] ^ din[ 8] ^ din[ 4] ^ din[ 5] ^ din[ 1];
dout[13] = din[ 5] ^ din[ 8] ^ din[ 7] ^ din[ 3] ^ din[ 0];
dout[12] = din[ 7] ^ din[ 6] ^ din[ 2] ^ din[ 8];
dout[11] = din[ 6] ^ din[ 5] ^ din[ 1] ^ din[ 7];
dout[10] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6];
dout[ 9] = din[ 3] ^ din[ 8] ^ din[ 5];
dout[ 8] = din[ 2] ^ din[ 4] ^ din[ 7];
dout[ 7] = din[ 1] ^ din[ 3] ^ din[ 6];
dout[ 6] = din[ 0] ^ din[ 2] ^ din[ 5];
dout[ 5] = din[ 8] ^ din[ 1];
dout[ 4] = din[ 7] ^ din[ 0];
dout[ 3] = din[ 6] ^ din[ 8] ^ din[ 4];
dout[ 2] = din[ 5] ^ din[ 7] ^ din[ 3];
dout[ 1] = din[ 4] ^ din[ 6] ^ din[ 2];
dout[ 0] = din[ 3] ^ din[ 5] ^ din[ 1];
pn9 = dout;
end
endfunction
@ -216,10 +232,10 @@ module axi_ad9234_pnmon (
assign adc_pn_data_pn_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in : adc_pn_data_pn;
always @(posedge adc_clk) begin
adc_pn_data_in <= { ~adc_data[13], adc_data[12: 0],
~adc_data[27], adc_data[26:14],
~adc_data[41], adc_data[40:28],
~adc_data[55], adc_data[54:42]};
adc_pn_data_in <= { ~adc_data[15], adc_data[14: 0],
~adc_data[31], adc_data[30:16],
~adc_data[47], adc_data[46:32],
~adc_data[63], adc_data[62:48]};
if (adc_pnseq_sel == 4'd0) begin
adc_pn_data_pn <= pn9(adc_pn_data_pn_s);
end else begin
@ -229,7 +245,7 @@ module axi_ad9234_pnmon (
// pn oos & pn err
ad_pnmon #(.DATA_WIDTH(56)) i_pnmon (
ad_pnmon #(.DATA_WIDTH(64)) i_pnmon (
.adc_clk (adc_clk),
.adc_valid_in (1'b1),
.adc_data_in (adc_pn_data_in),

59
library/axi_ad9250/axi_ad9250.v
View File

@ -132,7 +132,8 @@ module axi_ad9250 (
reg up_status_pn_oos = 'd0;
reg up_status_or = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_ack = 'd0;
reg up_rack = 'd0;
reg up_wack = 'd0;
// internal clocks & resets
@ -151,11 +152,13 @@ module axi_ad9250 (
wire [ 1:0] up_status_pn_oos_s;
wire [ 1:0] up_status_or_s;
wire [31:0] up_rdata_s[0:2];
wire up_ack_s[0:2];
wire up_sel_s;
wire up_wr_s;
wire [13:0] up_addr_s;
wire up_rack_s[0:2];
wire up_wack_s[0:2];
wire up_wreq_s;
wire [13:0] up_waddr_s;
wire [31:0] up_wdata_s;
wire up_rreq_s;
wire [13:0] up_raddr_s;
// signal name changes
@ -170,13 +173,15 @@ module axi_ad9250 (
up_status_pn_oos <= 'd0;
up_status_or <= 'd0;
up_rdata <= 'd0;
up_ack <= 'd0;
up_rack <= 'd0;
up_wack <= 'd0;
end else begin
up_status_pn_err <= | up_status_pn_err_s;
up_status_pn_oos <= | up_status_pn_oos_s;
up_status_or <= | up_status_or_s;
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2];
up_ack <= up_ack_s[0] | up_ack_s[1] | up_ack_s[2];
up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2];
up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2];
end
end
@ -212,12 +217,14 @@ module axi_ad9250 (
.up_adc_or (up_status_or_s[0]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[0]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[0]),
.up_ack (up_ack_s[0]));
.up_rack (up_rack_s[0]));
// channel
@ -233,12 +240,14 @@ module axi_ad9250 (
.up_adc_or (up_status_or_s[1]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[1]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[1]),
.up_ack (up_ack_s[1]));
.up_rack (up_rack_s[1]));
// common processor control
@ -280,12 +289,14 @@ module axi_ad9250 (
.up_adc_gpio_out (),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[2]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[2]),
.up_ack (up_ack_s[2]));
.up_rack (up_rack_s[2]));
// up bus interface
@ -309,12 +320,14 @@ module axi_ad9250 (
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata),
.up_ack (up_ack));
.up_rack (up_rack));
endmodule

30
library/axi_ad9250/axi_ad9250_channel.v
View File

@ -61,12 +61,14 @@ module axi_ad9250_channel (
up_rstn,
up_clk,
up_sel,
up_wr,
up_addr,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_ack);
up_rack);
// parameters
@ -92,12 +94,14 @@ module axi_ad9250_channel (
input up_rstn;
input up_clk;
input up_sel;
input up_wr;
input [13:0] up_addr;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_ack;
output up_rack;
// internal signals
@ -169,12 +173,14 @@ module axi_ad9250_channel (
.adc_usr_decimation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),
.up_wr (up_wr),
.up_addr (up_addr),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_ack (up_ack));
.up_rack (up_rack));
endmodule

342
library/axi_ad9265/axi_ad9265.v Normal file
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@ -0,0 +1,342 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9265 (
// adc interface (clk, data, over-range)
adc_clk_in_p,
adc_clk_in_n,
adc_data_in_p,
adc_data_in_n,
adc_or_in_p,
adc_or_in_n,
// delay interface
delay_clk,
// dma interface
adc_clk,
adc_valid,
adc_enable,
adc_data,
adc_dovf,
adc_dunf,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_rvalid,
s_axi_rresp,
s_axi_rdata,
s_axi_rready);
// parameters
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_ADC_DP_DISABLE = 0;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
parameter C_S_AXI_MIN_SIZE = 32'hffff;
// adc interface (clk, data, over-range)
input adc_clk_in_p;
input adc_clk_in_n;
input [ 7:0] adc_data_in_p;
input [ 7:0] adc_data_in_n;
input adc_or_in_p;
input adc_or_in_n;
// delay interface
input delay_clk;
// dma interface
output adc_clk;
output adc_valid;
output adc_enable;
output [15:0] adc_data;
input adc_dovf;
input adc_dunf;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata;
input s_axi_rready;
// internal registers
reg up_status_pn_err = 'd0;
reg up_status_pn_oos = 'd0;
reg up_status_or = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_wack = 'd0;
reg up_rack = 'd0;
// internal clocks & resets
wire adc_rst;
wire up_rstn;
wire up_clk;
// internal signals
wire [15:0] adc_data_s;
wire adc_or_s;
wire up_status_pn_err_s;
wire up_status_pn_oos_s;
wire up_status_or_s;
wire adc_status_s;
wire delay_rst_s;
wire delay_sel_s;
wire delay_rwn_s;
wire [ 7:0] delay_addr_s;
wire [ 4:0] delay_wdata_s;
wire [ 4:0] delay_rdata_s;
wire delay_ack_t_s;
wire delay_locked_s;
wire [13:0] up_raddr_s;
wire [31:0] up_rdata_s[0:1];
wire up_rack_s[0:1];
wire up_wack_s[0:1];
wire up_wreq_s;
wire [13:0] up_waddr_s;
wire [31:0] up_wdata_s;
wire up_rreq_s;
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_status_pn_err <= 'd0;
up_status_pn_oos <= 'd0;
up_status_or <= 'd0;
up_rdata <= 'd0;
up_rack <= 'd0;
up_wack <= 'd0;
end else begin
up_status_pn_err <= up_status_pn_err_s;
up_status_pn_oos <= up_status_pn_oos_s;
up_status_or <= up_status_or_s;
up_rdata <= up_rdata_s[0] | up_rdata_s[1];
up_rack <= up_rack_s[0] | up_rack_s[1];
up_wack <= up_wack_s[0] | up_wack_s[1];
end
end
// channel
axi_ad9265_channel #(
.CHID(0),
.DP_DISABLE (PCORE_ADC_DP_DISABLE))
i_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data (adc_data_s),
.adc_or (adc_or_s),
.adc_dcfilter_data_out (adc_data),
.adc_enable (adc_enable),
.adc_valid (adc_valid),
.up_adc_pn_err (up_status_pn_err_s),
.up_adc_pn_oos (up_status_pn_oos_s),
.up_adc_or (up_status_or_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[0]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[0]),
.up_rack (up_rack_s[0]));
// main (device interface)
axi_ad9265_if #(
.PCORE_BUFTYPE (PCORE_DEVICE_TYPE),
.PCORE_IODELAY_GROUP (PCORE_IODELAY_GROUP))
i_if (
.adc_clk_in_p (adc_clk_in_p),
.adc_clk_in_n (adc_clk_in_n),
.adc_data_in_p (adc_data_in_p),
.adc_data_in_n (adc_data_in_n),
.adc_or_in_p (adc_or_in_p),
.adc_or_in_n (adc_or_in_n),
.adc_clk (adc_clk),
.adc_data (adc_data_s),
.adc_or (adc_or_s),
.adc_status (adc_status_s),
.delay_clk (delay_clk),
.delay_rst (delay_rst_s),
.delay_sel (delay_sel_s),
.delay_rwn (delay_rwn_s),
.delay_addr (delay_addr_s),
.delay_wdata (delay_wdata_s),
.delay_rdata (delay_rdata_s),
.delay_ack_t (delay_ack_t_s),
.delay_locked (delay_locked_s));
// common processor control
up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common (
.mmcm_rst (),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_r1_mode (),
.adc_ddr_edgesel (),
.adc_pin_mode (),
.adc_status (adc_status_s),
.adc_status_ovf (adc_dovf),
.adc_status_unf (adc_dunf),
.adc_clk_ratio (32'd1),
.up_status_pn_err (up_status_pn_err),
.up_status_pn_oos (up_status_pn_oos),
.up_status_or (up_status_or),
.delay_clk (delay_clk),
.delay_rst (delay_rst_s),
.delay_sel (delay_sel_s),
.delay_rwn (delay_rwn_s),
.delay_addr (delay_addr_s),
.delay_wdata (delay_wdata_s),
.delay_rdata (delay_rdata_s),
.delay_ack_t (delay_ack_t_s),
.delay_locked (delay_locked_s),
.drp_clk (1'd0),
.drp_rst (),
.drp_sel (),
.drp_wr (),
.drp_addr (),
.drp_wdata (),
.drp_rdata (16'd0),
.drp_ready (1'd0),
.drp_locked (1'd1),
.up_usr_chanmax (),
.adc_usr_chanmax (8'd0),
.up_adc_gpio_in (),
.up_adc_gpio_out (),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[1]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[1]),
.up_rack (up_rack_s[1]));
// up bus interface
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************

211
library/axi_ad9265/axi_ad9265_channel.v Normal file
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@ -0,0 +1,211 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ADC channel-
`timescale 1ns/100ps
module axi_ad9265_channel (
// adc interface
adc_clk,
adc_rst,
adc_data,
adc_or,
// channel interface
adc_dcfilter_data_out,
adc_valid,
adc_enable,
up_adc_pn_err,
up_adc_pn_oos,
up_adc_or,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
parameter CHID = 0;
parameter DP_DISABLE = 0;
// adc interface
input adc_clk;
input adc_rst;
input [15:0] adc_data;
input adc_or;
// channel interface
output [15:0] adc_dcfilter_data_out;
output adc_valid;
output adc_enable;
output up_adc_pn_err;
output up_adc_pn_oos;
output up_adc_or;
// processor interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal signals
wire [15:0] adc_dfmt_data_s;
wire adc_dcfilt_enb_s;
wire adc_dfmt_se_s;
wire adc_dfmt_type_s;
wire adc_dfmt_enable_s;
wire [15:0] adc_dcfilt_offset_s;
wire [15:0] adc_dcfilt_coeff_s;
wire [ 3:0] adc_pnseq_sel_s;
wire adc_pn_err_s;
wire adc_pn_oos_s;
// iq correction inputs
axi_ad9265_pnmon i_pnmon (
.adc_clk (adc_clk),
.adc_data (adc_data),
.adc_pn_oos (adc_pn_oos_s),
.adc_pn_err (adc_pn_err_s),
.adc_pnseq_sel (adc_pnseq_sel_s));
generate
if (DP_DISABLE == 1) begin
assign adc_dfmt_data_s = adc_data;
end else begin
ad_datafmt #(.DATA_WIDTH(16)) i_ad_datafmt (
.clk (adc_clk),
.valid (1'b1),
.data (adc_data),
.valid_out (),
.data_out (adc_dfmt_data_s),
.dfmt_enable (adc_dfmt_enable_s),
.dfmt_type (adc_dfmt_type_s),
.dfmt_se (adc_dfmt_se_s));
end
endgenerate
generate
if (DP_DISABLE == 1) begin
assign adc_dcfilter_data_out = adc_dfmt_data_s;
end else begin
ad_dcfilter i_ad_dcfilter (
.clk (adc_clk),
.valid (1'b1),
.data (adc_dfmt_data_s),
.valid_out (adc_valid),
.data_out (adc_dcfilter_data_out),
.dcfilt_enb (adc_dcfilt_enb_s),
.dcfilt_coeff (adc_dcfilt_coeff_s),
.dcfilt_offset (adc_dcfilt_offset_s));
end
endgenerate
up_adc_channel #(.PCORE_ADC_CHID(CHID)) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),
.adc_iqcor_enb (),
.adc_dcfilt_enb (adc_dcfilt_enb_s),
.adc_dfmt_se (adc_dfmt_se_s),
.adc_dfmt_type (adc_dfmt_type_s),
.adc_dfmt_enable (adc_dfmt_enable_s),
.adc_dcfilt_offset (adc_dcfilt_offset_s),
.adc_dcfilt_coeff (adc_dcfilt_coeff_s),
.adc_iqcor_coeff_1 (),
.adc_iqcor_coeff_2 (),
.adc_pnseq_sel (adc_pnseq_sel_s),
.adc_data_sel (),
.adc_pn_err (adc_pn_err_s),
.adc_pn_oos (adc_pn_oos_s),
.adc_or (adc_or),
.up_adc_pn_err (up_adc_pn_err),
.up_adc_pn_oos (up_adc_pn_oos),
.up_adc_or (up_adc_or),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),
.up_usr_datatype_total_bits (),
.up_usr_datatype_bits (),
.up_usr_decimation_m (),
.up_usr_decimation_n (),
.adc_usr_datatype_be (1'b0),
.adc_usr_datatype_signed (1'b1),
.adc_usr_datatype_shift (8'd0),
.adc_usr_datatype_total_bits (8'd16),
.adc_usr_datatype_bits (8'd16),
.adc_usr_decimation_m (16'd1),
.adc_usr_decimation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************

236
library/axi_ad9265/axi_ad9265_if.v Normal file
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@ -0,0 +1,236 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// This is the LVDS/DDR interface, note that overrange is independent of data path,
// software will not be able to relate overrange to a specific sample!
`timescale 1ns/100ps
module axi_ad9265_if (
// adc interface (clk, data, over-range)
// nominal clock 125 MHz, up to 300 MHz
adc_clk_in_p,
adc_clk_in_n,
adc_data_in_p,
adc_data_in_n,
adc_or_in_p,
adc_or_in_n,
// interface outputs
adc_clk,
adc_data,
adc_or,
adc_status,
// delay control signals
delay_clk,
delay_rst,
delay_sel,
delay_rwn,
delay_addr,
delay_wdata,
delay_rdata,
delay_ack_t,
delay_locked);
// This parameter controls the buffer type based on the target device.
parameter PCORE_BUFTYPE = 0;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
// adc interface (clk, data, over-range)
// nominal clock 125 MHz, up to 300 MHz
input adc_clk_in_p;
input adc_clk_in_n;
input [ 7:0] adc_data_in_p;
input [ 7:0] adc_data_in_n;
input adc_or_in_p;
input adc_or_in_n;
// interface outputs
output adc_clk;
output [15:0] adc_data;
output adc_or;
output adc_status;
// delay control signals
input delay_clk;
input delay_rst;
input delay_sel;
input delay_rwn;
input [ 7:0] delay_addr;
input [ 4:0] delay_wdata;
output [ 4:0] delay_rdata;
output delay_ack_t;
output delay_locked;
// internal registers
reg adc_status = 'd0;
reg [ 7:0] adc_data_p = 'd0;
reg [ 7:0] adc_data_n = 'd0;
reg adc_or_p = 'd0;
reg adc_or_n = 'd0;
reg [15:0] adc_data = 'd0;
reg adc_or = 'd0;
reg [ 8:0] delay_ld = 'd0;
reg delay_ack_t = 'd0;
reg [ 4:0] delay_rdata = 'd0;
// internal signals
wire [ 4:0] delay_rdata_s[8:0];
wire [ 7:0] adc_data_p_s;
wire [ 7:0] adc_data_n_s;
wire adc_or_p_s;
wire adc_or_n_s;
genvar l_inst;
always @(posedge adc_clk)
begin
adc_status <= 1'b1;
adc_or <= adc_or_p_s | adc_or_n_s;
adc_data <= { adc_data_p_s[7], adc_data_n_s[7], adc_data_p_s[6], adc_data_n_s[6], adc_data_p_s[5], adc_data_n_s[5], adc_data_p_s[4], adc_data_n_s[4], adc_data_p_s[3], adc_data_n_s[3], adc_data_p_s[2], adc_data_n_s[2], adc_data_p_s[1], adc_data_n_s[1], adc_data_p_s[0], adc_data_n_s[0]};
end
// delay write interface, each delay element can be individually
// addressed, and a delay value can be directly loaded (no inc/dec stuff)
always @(posedge delay_clk) begin
if ((delay_sel == 1'b1) && (delay_rwn == 1'b0)) begin
case (delay_addr)
8'h08: delay_ld <= 15'h0100;
8'h07: delay_ld <= 15'h0080;
8'h06: delay_ld <= 15'h0040;
8'h05: delay_ld <= 15'h0020;
8'h04: delay_ld <= 15'h0010;
8'h03: delay_ld <= 15'h0008;
8'h02: delay_ld <= 15'h0004;
8'h01: delay_ld <= 15'h0002;
8'h00: delay_ld <= 15'h0001;
default: delay_ld <= 15'h0000;
endcase
end else begin
delay_ld <= 15'h0000;
end
end
// delay read interface, a delay ack toggle is used to transfer data to the
// processor side- delay locked is independently transferred
always @(posedge delay_clk) begin
case (delay_addr)
8'h08: delay_rdata <= delay_rdata_s[8];
8'h07: delay_rdata <= delay_rdata_s[7];
8'h06: delay_rdata <= delay_rdata_s[6];
8'h05: delay_rdata <= delay_rdata_s[5];
8'h04: delay_rdata <= delay_rdata_s[4];
8'h03: delay_rdata <= delay_rdata_s[3];
8'h02: delay_rdata <= delay_rdata_s[2];
8'h01: delay_rdata <= delay_rdata_s[1];
8'h00: delay_rdata <= delay_rdata_s[0];
default: delay_rdata <= 5'd0;
endcase
if (delay_sel == 1'b1) begin
delay_ack_t <= ~delay_ack_t;
end
end
// data interface
generate
for (l_inst = 0; l_inst <= 7; l_inst = l_inst + 1) begin : g_adc_if
ad_lvds_in #(
.BUFTYPE (PCORE_BUFTYPE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (PCORE_IODELAY_GROUP))
i_adc_data (
.rx_clk (adc_clk),
.rx_data_in_p (adc_data_in_p[l_inst]),
.rx_data_in_n (adc_data_in_n[l_inst]),
.rx_data_p (adc_data_p_s[l_inst]),
.rx_data_n (adc_data_n_s[l_inst]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_ld (delay_ld[l_inst]),
.delay_wdata (delay_wdata),
.delay_rdata (delay_rdata_s[l_inst]),
.delay_locked ());
end
endgenerate
// over-range interface
ad_lvds_in #(
.BUFTYPE (PCORE_BUFTYPE),
.IODELAY_CTRL (1),
.IODELAY_GROUP (PCORE_IODELAY_GROUP))
i_adc_or (
.rx_clk (adc_clk),
.rx_data_in_p (adc_or_in_p),
.rx_data_in_n (adc_or_in_n),
.rx_data_p (adc_or_p_s),
.rx_data_n (adc_or_n_s),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_ld (delay_ld[8]),
.delay_wdata (delay_wdata),
.delay_rdata (delay_rdata_s[8]),
.delay_locked (delay_locked));
// clock
ad_lvds_clk #(
.BUFTYPE (PCORE_BUFTYPE))
i_adc_clk (
.clk_in_p (adc_clk_in_p),
.clk_in_n (adc_clk_in_n),
.clk (adc_clk));
endmodule
// ***************************************************************************
// ***************************************************************************

29
library/axi_ad9265/axi_ad9265_ip.tcl Normal file
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@ -0,0 +1,29 @@
# ip
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_ad9265
adi_ip_files axi_ad9265 [list \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/ad_lvds_clk.v" \
"$ad_hdl_dir/library/common/ad_lvds_in.v" \
"$ad_hdl_dir/library/common/ad_datafmt.v" \
"$ad_hdl_dir/library/common/ad_dcfilter.v" \
"$ad_hdl_dir/library/common/ad_pnmon.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_delay_cntrl.v" \
"$ad_hdl_dir/library/common/up_drp_cntrl.v" \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"axi_ad9265_pnmon.v" \
"axi_ad9265_if.v" \
"axi_ad9265_channel.v" \
"axi_ad9265.v"]
adi_ip_properties axi_ad9265
ipx::save_core [ipx::current_core]

191
library/axi_ad9265/axi_ad9265_pnmon.v Normal file
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@ -0,0 +1,191 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// PN monitors
`timescale 1ns/100ps
module axi_ad9265_pnmon (
// adc interface
adc_clk,
adc_data,
// pn out of sync and error
adc_pn_oos,
adc_pn_err,
adc_pnseq_sel);
// adc interface
input adc_clk;
input [15:0] adc_data;
// pn out of sync and error
output adc_pn_oos;
output adc_pn_err;
input [ 3:0] adc_pnseq_sel;
// internal registers
reg adc_valid_in = 'd0;
reg [31:0] adc_pn_data_in = 'd0;
reg [31:0] adc_pn_data_pn = 'd0;
// internal signals
wire [31:0] adc_pn_data_pn_s;
// PN23 function
function [31:0] pn23;
input [31:0] din;
reg [31:0] dout;
begin
dout[31] = din[22] ^ din[17];
dout[30] = din[21] ^ din[16];
dout[29] = din[20] ^ din[15];
dout[28] = din[19] ^ din[14];
dout[27] = din[18] ^ din[13];
dout[26] = din[17] ^ din[12];
dout[25] = din[16] ^ din[11];
dout[24] = din[15] ^ din[10];
dout[23] = din[14] ^ din[ 9];
dout[22] = din[13] ^ din[ 8];
dout[21] = din[12] ^ din[ 7];
dout[20] = din[11] ^ din[ 6];
dout[19] = din[10] ^ din[ 5];
dout[18] = din[ 9] ^ din[ 4];
dout[17] = din[ 8] ^ din[ 3];
dout[16] = din[ 7] ^ din[ 2];
dout[15] = din[ 6] ^ din[ 1];
dout[14] = din[ 5] ^ din[ 0];
dout[13] = din[ 4] ^ din[22] ^ din[17];
dout[12] = din[ 3] ^ din[21] ^ din[16];
dout[11] = din[ 2] ^ din[20] ^ din[15];
dout[10] = din[ 1] ^ din[19] ^ din[14];
dout[ 9] = din[ 0] ^ din[18] ^ din[13];
dout[ 8] = din[22] ^ din[12];
dout[ 7] = din[21] ^ din[11];
dout[ 6] = din[20] ^ din[10];
dout[ 5] = din[19] ^ din[ 9];
dout[ 4] = din[18] ^ din[ 8];
dout[ 3] = din[17] ^ din[ 7];
dout[ 2] = din[16] ^ din[ 6];
dout[ 1] = din[15] ^ din[ 5];
dout[ 0] = din[14] ^ din[ 4];
pn23 = dout;
end
endfunction
// PN9 function
function [31:0] pn9;
input [31:0] din;
reg [31:0] dout;
begin
dout[31] = din[ 8] ^ din[ 4];
dout[30] = din[ 7] ^ din[ 3];
dout[29] = din[ 6] ^ din[ 2];
dout[28] = din[ 5] ^ din[ 1];
dout[27] = din[ 4] ^ din[ 0];
dout[26] = din[ 3] ^ din[ 8] ^ din[ 4];
dout[25] = din[ 2] ^ din[ 7] ^ din[ 3];
dout[24] = din[ 1] ^ din[ 6] ^ din[ 2];
dout[23] = din[ 0] ^ din[ 5] ^ din[ 1];
dout[22] = din[ 8] ^ din[ 0];
dout[21] = din[ 7] ^ din[ 8] ^ din[ 4];
dout[20] = din[ 6] ^ din[ 7] ^ din[ 3];
dout[19] = din[ 5] ^ din[ 6] ^ din[ 2];
dout[18] = din[ 4] ^ din[ 5] ^ din[ 1];
dout[17] = din[ 3] ^ din[ 4] ^ din[ 0];
dout[16] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4];
dout[15] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3];
dout[14] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2];
dout[13] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1];
dout[12] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0];
dout[11] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4];
dout[10] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3];
dout[ 9] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2];
dout[ 8] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1];
dout[ 7] = din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 0];
dout[ 6] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 4];
dout[ 5] = din[ 0] ^ din[ 2] ^ din[ 5] ^ din[ 7] ^ din[ 3];
dout[ 4] = din[ 8] ^ din[ 1] ^ din[ 6] ^ din[ 2];
dout[ 3] = din[ 7] ^ din[ 0] ^ din[ 5] ^ din[ 1];
dout[ 2] = din[ 6] ^ din[ 8] ^ din[ 0];
dout[ 1] = din[5] ^ din[7] ^ din[8] ^ din[4];
dout[ 0] = din[4] ^ din[6] ^ din[7] ^ din[3];
pn9 = dout;
end
endfunction
// pn sequence select
assign adc_pn_data_pn_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in : adc_pn_data_pn;
always @(posedge adc_clk) begin
adc_valid_in <= ~adc_valid_in;
adc_pn_data_in <= {adc_pn_data_in[15:0], adc_data[15:0]};
if(adc_valid_in == 1'b1) begin
if (adc_pnseq_sel == 4'd0) begin
adc_pn_data_pn <= pn9(adc_pn_data_pn_s);
end else begin
adc_pn_data_pn <= pn23(adc_pn_data_pn_s);
end
end
end
// pn oos & pn err
ad_pnmon #(.DATA_WIDTH(32)) i_pnmon (
.adc_clk (adc_clk),
.adc_valid_in (adc_valid_in),
.adc_data_in (adc_pn_data_in),
.adc_data_pn (adc_pn_data_pn),
.adc_pn_oos (adc_pn_oos),
.adc_pn_err (adc_pn_err));
endmodule
// ***************************************************************************
// ***************************************************************************

52
library/axi_ad9361/axi_ad9361.v
View File

@ -252,8 +252,9 @@ module axi_ad9361 (
// internal registers
reg up_wack = 'd0;
reg up_rack = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_ack = 'd0;
// internal clocks and resets
@ -278,14 +279,17 @@ module axi_ad9361 (
wire [ 4:0] delay_rdata_s;
wire delay_ack_t_s;
wire delay_locked_s;
wire up_sel_s;
wire up_wr_s;
wire [13:0] up_addr_s;
wire up_wreq_s;
wire [13:0] up_waddr_s;
wire [31:0] up_wdata_s;
wire up_wack_rx_s;
wire up_wack_tx_s;
wire up_rreq_s;
wire [13:0] up_raddr_s;
wire [31:0] up_rdata_rx_s;
wire up_ack_rx_s;
wire up_rack_rx_s;
wire [31:0] up_rdata_tx_s;
wire up_ack_tx_s;
wire up_rack_tx_s;
// signal name changes
@ -296,11 +300,13 @@ module axi_ad9361 (
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_wack <= 'd0;
up_rack <= 'd0;
up_rdata <= 'd0;
up_ack <= 'd0;
end else begin
up_wack <= up_wack_rx_s | up_wack_tx_s;
up_rack <= up_rack_rx_s | up_rack_tx_s;
up_rdata <= up_rdata_rx_s | up_rdata_tx_s;
up_ack <= up_ack_rx_s | up_ack_tx_s;
end
end
@ -384,12 +390,14 @@ module axi_ad9361 (
.up_adc_gpio_out (up_adc_gpio_out),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_rx_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_rx_s),
.up_ack (up_ack_rx_s));
.up_rack (up_rack_rx_s));
// transmit
@ -422,12 +430,14 @@ module axi_ad9361 (
.up_dac_gpio_out (up_dac_gpio_out),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_tx_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_tx_s),
.up_ack (up_ack_tx_s));
.up_rack (up_rack_tx_s));
// axi interface
@ -451,12 +461,14 @@ module axi_ad9361 (
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata),
.up_ack (up_ack));
.up_rack (up_rack));
endmodule

85
library/axi_ad9361/axi_ad9361_rx.v
View File

@ -90,12 +90,14 @@ module axi_ad9361_rx (
up_rstn,
up_clk,
up_sel,
up_wr,
up_addr,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_ack);
up_rack);
// parameters
@ -150,12 +152,14 @@ module axi_ad9361_rx (
input up_rstn;
input up_clk;
input up_sel;
input up_wr;
input [13:0] up_addr;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_ack;
output up_rack;
// internal registers
@ -163,7 +167,8 @@ module axi_ad9361_rx (
reg up_status_pn_oos = 'd0;
reg up_status_or = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_ack = 'd0;
reg up_rack = 'd0;
reg up_wack = 'd0;
// internal signals
@ -175,7 +180,8 @@ module axi_ad9361_rx (
wire [ 3:0] up_adc_pn_oos_s;
wire [ 3:0] up_adc_or_s;
wire [31:0] up_rdata_s[0:4];
wire up_ack_s[0:4];
wire up_rack_s[0:4];
wire up_wack_s[0:4];
// processor read interface
@ -185,13 +191,15 @@ module axi_ad9361_rx (
up_status_pn_oos <= 'd0;
up_status_or <= 'd0;
up_rdata <= 'd0;
up_ack <= 'd0;
up_rack <= 'd0;
up_wack <= 'd0;
end else begin
up_status_pn_err <= | up_adc_pn_err_s;
up_status_pn_oos <= | up_adc_pn_oos_s;
up_status_or <= | up_adc_or_s;
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | up_rdata_s[3] | up_rdata_s[4];
up_ack <= up_ack_s[0] | up_ack_s[1] | up_ack_s[2] | up_ack_s[3] | up_ack_s[4];
up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2] | up_rack_s[3] | up_rack_s[4];
up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2] | up_wack_s[3] | up_wack_s[4];
end
end
@ -219,12 +227,14 @@ module axi_ad9361_rx (
.up_adc_or (up_adc_or_s[0]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),
.up_wr (up_wr),
.up_addr (up_addr),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[0]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[0]),
.up_ack (up_ack_s[0]));
.up_rack (up_rack_s[0]));
// channel 1 (q)
@ -250,12 +260,14 @@ module axi_ad9361_rx (
.up_adc_or (up_adc_or_s[1]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),
.up_wr (up_wr),
.up_addr (up_addr),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[1]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[1]),
.up_ack (up_ack_s[1]));
.up_rack (up_rack_s[1]));
// channel 2 (i)
@ -281,12 +293,14 @@ module axi_ad9361_rx (
.up_adc_or (up_adc_or_s[2]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),
.up_wr (up_wr),
.up_addr (up_addr),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[2]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[2]),
.up_ack (up_ack_s[2]));
.up_rack (up_rack_s[2]));
// channel 3 (q)
@ -312,12 +326,14 @@ module axi_ad9361_rx (
.up_adc_or (up_adc_or_s[3]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),
.up_wr (up_wr),
.up_addr (up_addr),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[3]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[3]),
.up_ack (up_ack_s[3]));
.up_rack (up_rack_s[3]));
// common processor control
@ -329,9 +345,12 @@ module axi_ad9361_rx (
.adc_ddr_edgesel (),
.adc_pin_mode (),
.adc_status (adc_status),
.adc_sync_status(),
.adc_status_ovf (adc_dovf),
.adc_status_unf (adc_dunf),
.adc_clk_ratio (32'd1),
.adc_start_code(),
.adc_sync(),
.up_status_pn_err (up_status_pn_err),
.up_status_pn_oos (up_status_pn_oos),
.up_status_or (up_status_or),
@ -359,12 +378,14 @@ module axi_ad9361_rx (
.up_adc_gpio_out (up_adc_gpio_out),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),
.up_wr (up_wr),
.up_addr (up_addr),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[4]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[4]),
.up_ack (up_ack_s[4]));
.up_rack (up_rack_s[4]));
endmodule

30
library/axi_ad9361/axi_ad9361_rx_channel.v
View File

@ -67,12 +67,14 @@ module axi_ad9361_rx_channel (
up_rstn,
up_clk,
up_sel,
up_wr,
up_addr,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_ack);
up_rack);
// parameters
@ -105,12 +107,14 @@ module axi_ad9361_rx_channel (
input up_rstn;
input up_clk;
input up_sel;
input up_wr;
input [13:0] up_addr;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_ack;
output up_rack;
// internal signals
@ -238,12 +242,14 @@ module axi_ad9361_rx_channel (
.adc_usr_decimation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),
.up_wr (up_wr),
.up_addr (up_addr),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_ack (up_ack));
.up_rack (up_rack));
endmodule

82
library/axi_ad9361/axi_ad9361_tx.v
View File

@ -80,12 +80,14 @@ module axi_ad9361_tx (
up_rstn,
up_clk,
up_sel,
up_wr,
up_addr,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_ack);
up_rack);
// parameters
@ -131,12 +133,14 @@ module axi_ad9361_tx (
input up_rstn;
input up_clk;
input up_sel;
input up_wr;
input [13:0] up_addr;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_ack;
output up_rack;
// internal registers
@ -148,7 +152,8 @@ module axi_ad9361_tx (
reg dac_valid_i1 = 'd0;
reg dac_valid_q1 = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_ack = 'd0;
reg up_rack = 'd0;
reg up_wack = 'd0;
// internal clock and resets
@ -161,7 +166,8 @@ module axi_ad9361_tx (
wire [ 7:0] dac_datarate_s;
wire [47:0] dac_data_int_s;
wire [31:0] up_rdata_s[0:4];
wire up_ack_s[0:4];
wire up_rack_s[0:4];
wire up_wack_s[0:4];
// master/slave
@ -196,10 +202,12 @@ module axi_ad9361_tx (
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rdata <= 'd0;
up_ack <= 'd0;
up_rack <= 'd0;
up_wack <= 'd0;
end else begin
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | up_rdata_s[3] | up_rdata_s[4];
up_ack <= up_ack_s[0] | up_ack_s[1] | up_ack_s[2] | up_ack_s[3] | up_ack_s[4];
up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2] | up_rack_s[3] | up_rack_s[4];
up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2] | up_wack_s[3] | up_wack_s[4];
end
end
@ -223,12 +231,14 @@ module axi_ad9361_tx (
.dac_dds_format (dac_dds_format_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),
.up_wr (up_wr),
.up_addr (up_addr),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[0]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[0]),
.up_ack (up_ack_s[0]));
.up_rack (up_rack_s[0]));
// dac channel
@ -250,12 +260,14 @@ module axi_ad9361_tx (
.dac_dds_format (dac_dds_format_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),
.up_wr (up_wr),
.up_addr (up_addr),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[1]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[1]),
.up_ack (up_ack_s[1]));
.up_rack (up_rack_s[1]));
// dac channel
@ -277,12 +289,14 @@ module axi_ad9361_tx (
.dac_dds_format (dac_dds_format_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),
.up_wr (up_wr),
.up_addr (up_addr),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[2]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[2]),
.up_ack (up_ack_s[2]));
.up_rack (up_rack_s[2]));
// dac channel
@ -304,12 +318,14 @@ module axi_ad9361_tx (
.dac_dds_format (dac_dds_format_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),
.up_wr (up_wr),
.up_addr (up_addr),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[3]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[3]),
.up_ack (up_ack_s[3]));
.up_rack (up_rack_s[3]));
// dac common processor interface
@ -343,12 +359,14 @@ module axi_ad9361_tx (
.up_dac_gpio_out (up_dac_gpio_out),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),
.up_wr (up_wr),
.up_addr (up_addr),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[4]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[4]),
.up_ack (up_ack_s[4]));
.up_rack (up_rack_s[4]));
endmodule

30
library/axi_ad9361/axi_ad9361_tx_channel.v
View File

@ -62,12 +62,14 @@ module axi_ad9361_tx_channel (
up_rstn,
up_clk,
up_sel,
up_wr,
up_addr,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_ack);
up_rack);
// parameters
@ -101,12 +103,14 @@ module axi_ad9361_tx_channel (
input up_rstn;
input up_clk;
input up_sel;
input up_wr;
input [13:0] up_addr;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_ack;
output up_rack;
// internal registers
@ -409,12 +413,14 @@ module axi_ad9361_tx_channel (
.dac_usr_interpolation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),
.up_wr (up_wr),
.up_addr (up_addr),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_ack (up_ack));
.up_rack (up_rack));
endmodule

30
library/axi_ad9434/axi_ad9434.v
View File

@ -139,12 +139,14 @@ module axi_ad9434 (
wire drp_clk;
// internal signals
wire up_sel_s;
wire up_wr_s;
wire [13:0] up_addr_s;
wire up_wreq_s;
wire up_rreq_s;
wire [13:0] up_waddr_s;
wire [13:0] up_raddr_s;
wire [31:0] up_wdata_s;
wire [31:0] up_rdata_s;
wire up_ack_s;
wire up_wack_s;
wire up_rack_s;
wire [ 1:0] up_status_pn_err_s;
wire [ 1:0] up_status_pn_oos_s;
@ -247,12 +249,14 @@ module axi_ad9434 (
.drp_locked (drp_locked_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_ack (up_ack_s));
.up_rack (up_rack_s));
// up bus interface
up_axi i_up_axi (
@ -275,11 +279,13 @@ module axi_ad9434 (
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_rdata (up_rdata_s),
.up_ack (up_ack_s));
.up_wack (up_wack_s),
.up_raddr (up_raddr_s),
.up_rreq (up_rreq_s),
.up_rack (up_rack_s));
endmodule

233
library/axi_ad9434/axi_ad9434_core.v
View File

@ -82,12 +82,14 @@ module axi_ad9434_core (
up_rstn,
up_clk,
up_sel,
up_wr,
up_addr,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_ack,
up_rack,
// status and control signals
@ -133,19 +135,23 @@ module axi_ad9434_core (
// processor interface
input up_clk;
input up_rstn;
input up_sel;
input up_wr;
input [13:0] up_addr;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_ack;
output up_rack;
output mmcm_rst;
output adc_rst;
input adc_status;
// internal registers
reg up_wack;
reg [31:0] up_rdata;
reg up_ack;
reg up_rack;
// internal signals
wire up_status_pn_err_s;
@ -160,16 +166,17 @@ module axi_ad9434_core (
wire adc_pn_err_s;
wire adc_pn_oos_s;
wire up_wack_s[0:1];
wire [31:0] up_rdata_s[0:1];
wire up_ack_s[0:1];
wire up_rack_s[0:1];
// instantiations
axi_ad9434_pnmon i_pnmon (
.adc_clk(adc_clk),
.adc_data(adc_data),
.adc_pnseq_sel(adc_pnseq_sel_s),
.adc_pn_err(adc_pn_err_s),
.adc_pn_oos(adc_pn_oos_s));
.adc_clk (adc_clk),
.adc_data (adc_data),
.adc_pnseq_sel (adc_pnseq_sel_s),
.adc_pn_err (adc_pn_err_s),
.adc_pn_oos (adc_pn_oos_s));
genvar n;
generate
@ -177,14 +184,14 @@ module axi_ad9434_core (
ad_datafmt # (
.DATA_WIDTH(12))
i_datafmt (
.clk(adc_clk),
.valid(1'b1),
.data(adc_data[n*12+11:n*12]),
.valid_out(dma_dvalid),
.data_out(dma_data[n*16+15:n*16]),
.dfmt_enable(adc_dfmt_enable_s),
.dfmt_type(adc_dfmt_type_s),
.dfmt_se(adc_dfmt_se_s));
.clk (adc_clk),
.valid (1'b1),
.data (adc_data[n*12+11:n*12]),
.valid_out (dma_dvalid),
.data_out (dma_data[n*16+15:n*16]),
.dfmt_enable (adc_dfmt_enable_s),
.dfmt_type (adc_dfmt_type_s),
.dfmt_se (adc_dfmt_se_s));
end
endgenerate
@ -193,104 +200,110 @@ module axi_ad9434_core (
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rdata <= 'd0;
up_ack <= 'd0;
up_rack <= 'd0;
up_wack <= 'd0;
end else begin
up_rdata <= up_rdata_s[0] | up_rdata_s[1];
up_ack <= up_ack_s[0] | up_ack_s[1];
up_rack <= up_rack_s[0] | up_rack_s[1];
up_wack <= up_wack_s[0] | up_wack_s[1];
end
end
up_adc_common #(
.PCORE_ID(PCORE_ID))
i_adc_common(
.mmcm_rst(mmcm_rst),
.adc_clk(adc_clk),
.adc_rst(adc_rst),
.adc_r1_mode(),
.adc_ddr_edgesel(),
.adc_pin_mode(),
.adc_status(adc_status),
.adc_status_ovf(dma_dovf),
.adc_status_unf(1'b0),
.adc_clk_ratio(32'd4),
.up_status_pn_err(up_status_pn_err_s),
.up_status_pn_oos(up_status_pn_oos_s),
.up_status_or(up_status_or_s),
.delay_clk(delay_clk),
.delay_rst(delay_rst),
.delay_sel(delay_sel),
.delay_rwn(delay_rwn),
.delay_addr(delay_addr),
.delay_wdata(delay_wdata),
.delay_rdata(delay_rdata),
.delay_ack_t(delay_ack_t),
.delay_locked(delay_locked),
.drp_clk(drp_clk),
.drp_rst(drp_rst),
.drp_sel(drp_sel),
.drp_wr(drp_wr),
.drp_addr(drp_addr),
.drp_wdata(drp_wdata),
.drp_rdata(drp_rdata),
.drp_ready(drp_ready),
.drp_locked(drp_locked),
.up_usr_chanmax(),
.adc_usr_chanmax(),
.up_adc_gpio_in(),
.up_adc_gpio_out(),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_sel(up_sel),
.up_wr(up_wr),
.up_addr(up_addr),
.up_wdata(up_wdata),
.up_rdata(up_rdata_s[0]),
.up_ack(up_ack_s[0]));
.mmcm_rst (mmcm_rst),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_r1_mode (),
.adc_ddr_edgesel (),
.adc_pin_mode (),
.adc_status (adc_status),
.adc_status_ovf (dma_dovf),
.adc_status_unf (1'b0),
.adc_clk_ratio (32'd4),
.up_status_pn_err (up_status_pn_err_s),
.up_status_pn_oos (up_status_pn_oos_s),
.up_status_or (up_status_or_s),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_sel (delay_sel),
.delay_rwn (delay_rwn),
.delay_addr (delay_addr),
.delay_wdata (delay_wdata),
.delay_rdata (delay_rdata),
.delay_ack_t (delay_ack_t),
.delay_locked (delay_locked),
.drp_clk (drp_clk),
.drp_rst (drp_rst),
.drp_sel (drp_sel),
.drp_wr (drp_wr),
.drp_addr (drp_addr),
.drp_wdata (drp_wdata),
.drp_rdata (drp_rdata),
.drp_ready (drp_ready),
.drp_locked (drp_locked),
.up_usr_chanmax (),
.adc_usr_chanmax (8'd0),
.up_adc_gpio_in (32'd0),
.up_adc_gpio_out (),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[0]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[0]),
.up_rack (up_rack_s[0]));
up_adc_channel #(
.PCORE_ADC_CHID(0))
i_adc_channel(
.adc_clk(adc_clk),
.adc_rst(adc_rst),
.adc_enable(),
.adc_iqcor_enb(),
.adc_dcfilt_enb(),
.adc_dfmt_se(adc_dfmt_se_s),
.adc_dfmt_type(adc_dfmt_type_s),
.adc_dfmt_enable(adc_dfmt_enable_s),
.adc_dcfilt_offset(),
.adc_dcfilt_coeff(),
.adc_iqcor_coeff_1(),
.adc_iqcor_coeff_2(),
.adc_pnseq_sel(adc_pnseq_sel_s),
.adc_data_sel(),
.adc_pn_err(adc_pn_err_s),
.adc_pn_oos(adc_pn_oos_s),
.adc_or(adc_or),
.up_adc_pn_err(up_status_pn_err_s),
.up_adc_pn_oos(up_status_pn_oos_s),
.up_adc_or(up_status_or_s),
.up_usr_datatype_be(),
.up_usr_datatype_signed(),
.up_usr_datatype_shift(),
.up_usr_datatype_total_bits(),
.up_usr_datatype_bits(),
.up_usr_decimation_m(),
.up_usr_decimation_n(),
.adc_usr_datatype_be(1'b0),
.adc_usr_datatype_signed(1'b1),
.adc_usr_datatype_shift(8'd0),
.adc_usr_datatype_total_bits(8'd16),
.adc_usr_datatype_bits(8'd16),
.adc_usr_decimation_m(16'd1),
.adc_usr_decimation_n(16'd1),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_sel(up_sel),
.up_wr(up_wr),
.up_addr(up_addr),
.up_wdata(up_wdata),
.up_rdata(up_rdata_s[1]),
.up_ack(up_ack_s[1]));
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (),
.adc_iqcor_enb (),
.adc_dcfilt_enb (),
.adc_dfmt_se (adc_dfmt_se_s),
.adc_dfmt_type (adc_dfmt_type_s),
.adc_dfmt_enable (adc_dfmt_enable_s),
.adc_dcfilt_offset (),
.adc_dcfilt_coeff (),
.adc_iqcor_coeff_1 (),
.adc_iqcor_coeff_2 (),
.adc_pnseq_sel (adc_pnseq_sel_s),
.adc_data_sel (),
.adc_pn_err (adc_pn_err_s),
.adc_pn_oos (adc_pn_oos_s),
.adc_or (adc_or),
.up_adc_pn_err (up_status_pn_err_s),
.up_adc_pn_oos (up_status_pn_oos_s),
.up_adc_or (up_status_or_s),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),
.up_usr_datatype_total_bits (),
.up_usr_datatype_bits (),
.up_usr_decimation_m (),
.up_usr_decimation_n (),
.adc_usr_datatype_be (1'b0),
.adc_usr_datatype_signed (1'b1),
.adc_usr_datatype_shift (8'd0),
.adc_usr_datatype_total_bits (8'd16),
.adc_usr_datatype_bits (8'd16),
.adc_usr_decimation_m (16'd1),
.adc_usr_decimation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[1]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[1]),
.up_rack (up_rack_s[1]));
endmodule

49
library/axi_ad9467/axi_ad9467.v
View File

@ -138,8 +138,9 @@ module axi_ad9467(
// internal registers
reg up_wack = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_ack = 'd0;
reg up_rack = 'd0;
// internal clocks & resets
@ -163,11 +164,13 @@ module axi_ad9467(
wire up_status_pn_err_s;
wire up_status_pn_oos_s;
wire up_status_or_s;
wire up_rreq_s;
wire [13:0] up_raddr_s;
wire [31:0] up_rdata_s[0:1];
wire up_ack_s[0:1];
wire up_sel_s;
wire up_wr_s;
wire [13:0] up_addr_s;
wire up_rack_s[0:1];
wire up_wack_s[0:1];
wire up_wreq_s;
wire [13:0] up_waddr_s;
wire [31:0] up_wdata_s;
//defaults
@ -181,10 +184,12 @@ module axi_ad9467(
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rdata <= 32'd0;
up_ack <= 1'd0;
up_rack <= 1'd0;
up_wack <= 1'd0;
end else begin
up_rdata <= up_rdata_s[0] | up_rdata_s[1];
up_ack <= up_ack_s[0] | up_ack_s[1];
up_rack <= up_rack_s[0] | up_rack_s[1];
up_wack <= up_wack_s[0] | up_wack_s[1];
end
end
@ -228,12 +233,14 @@ module axi_ad9467(
.up_adc_or (up_status_or_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[0]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[0]),
.up_ack (up_ack_s[0]));
.up_rack (up_rack_s[0]));
// common processor control
@ -275,12 +282,14 @@ module axi_ad9467(
.up_adc_gpio_out (),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[1]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[1]),
.up_ack (up_ack_s[1]));
.up_rack (up_rack_s[1]));
// up bus interface
@ -304,12 +313,14 @@ module axi_ad9467(
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata),
.up_ack (up_ack));
.up_rack (up_rack));
endmodule

34
library/axi_ad9467/axi_ad9467_channel.v
View File

@ -58,12 +58,14 @@ module axi_ad9467_channel(
up_rstn,
up_clk,
up_sel,
up_wr,
up_addr,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_ack);
up_rack);
// parameters
@ -88,12 +90,14 @@ module axi_ad9467_channel(
input up_rstn;
input up_clk;
input up_sel;
input up_wr;
input [13:0] up_addr;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_ack;
output up_rack;
// internal signals
@ -112,7 +116,7 @@ module axi_ad9467_channel(
.adc_pn_oos (adc_pn_oos_s),
.adc_pn_err (adc_pn_err_s),
.adc_pnseq_sel (adc_pnseq_sel_s));
ad_datafmt #(.DATA_WIDTH(16)) i_datafmt (
.clk(adc_clk),
.valid(1'b1),
@ -122,7 +126,7 @@ module axi_ad9467_channel(
.dfmt_enable(adc_dfmt_enable_s),
.dfmt_type(adc_dfmt_type_s),
.dfmt_se(adc_dfmt_se_s));
up_adc_channel #(.PCORE_ADC_CHID(0)) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
@ -160,12 +164,14 @@ module axi_ad9467_channel(
.adc_usr_decimation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),
.up_wr (up_wr),
.up_addr (up_addr),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_ack (up_ack));
.up_rack (up_rack));
endmodule

51
library/axi_ad9625/axi_ad9625.v
View File

@ -129,7 +129,8 @@ module axi_ad9625 (
// internal registers
reg [ 31:0] up_rdata = 'd0;
reg up_ack = 'd0;
reg up_rack = 'd0;
reg up_wack = 'd0;
// internal clocks & resets
@ -145,12 +146,14 @@ module axi_ad9625 (
wire up_adc_pn_err_s;
wire up_adc_pn_oos_s;
wire up_adc_or_s;
wire up_sel_s;
wire up_wr_s;
wire [ 13:0] up_addr_s;
wire [ 31:0] up_wdata_s;
wire [ 31:0] up_rdata_s[0:1];
wire up_ack_s[0:1];
wire up_rack_s[0:1];
wire up_wack_s[0:1];
wire up_wreq_s;
wire [ 13:0] up_waddr_s;
wire [ 31:0] up_wdata_s;
wire up_rreq_s;
wire [ 13:0] up_raddr_s;
// signal name changes
@ -162,10 +165,12 @@ module axi_ad9625 (
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rdata <= 'd0;
up_ack <= 'd0;
up_rack <= 'd0;
up_wack <= 'd0;
end else begin
up_rdata <= up_rdata_s[0] | up_rdata_s[1];
up_ack <= up_ack_s[0] | up_ack_s[1] ;
up_rack <= up_rack_s[0] | up_rack_s[1] ;
up_wack <= up_wack_s[0] | up_wack_s[1] ;
end
end
@ -199,12 +204,14 @@ module axi_ad9625 (
.up_adc_or (up_adc_or_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[0]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[0]),
.up_ack (up_ack_s[0]));
.up_rack (up_rack_s[0]));
// common processor control
@ -246,12 +253,14 @@ module axi_ad9625 (
.up_adc_gpio_out (),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[1]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[1]),
.up_ack (up_ack_s[1]));
.up_rack (up_rack_s[1]));
// up bus interface
@ -275,12 +284,14 @@ module axi_ad9625 (
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata),
.up_ack (up_ack));
.up_rack (up_rack));
endmodule

30
library/axi_ad9625/axi_ad9625_channel.v
View File

@ -61,12 +61,14 @@ module axi_ad9625_channel (
up_rstn,
up_clk,
up_sel,
up_wr,
up_addr,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_ack);
up_rack);
// adc interface
@ -87,12 +89,14 @@ module axi_ad9625_channel (
input up_rstn;
input up_clk;
input up_sel;
input up_wr;
input [13:0] up_addr;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_ack;
output up_rack;
// internal signals
@ -164,12 +168,14 @@ module axi_ad9625_channel (
.adc_usr_decimation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),
.up_wr (up_wr),
.up_addr (up_addr),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_ack (up_ack));
.up_rack (up_rack));
endmodule

4
library/axi_ad9625/axi_ad9625_constr.xdc Normal file
View File

@ -0,0 +1,4 @@
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports rx_clk]]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports s_axi_aclk]]

5
library/axi_ad9625/axi_ad9625_ip.tcl
View File

@ -20,9 +20,12 @@ adi_ip_files axi_ad9625 [list \
"axi_ad9625_pnmon.v" \
"axi_ad9625_channel.v" \
"axi_ad9625_if.v" \
"axi_ad9625.v" ]
"axi_ad9625.v" \
"axi_ad9625_constr.xdc" ]
adi_ip_properties axi_ad9625
adi_ip_constraints axi_ad9625 [list \
"axi_ad9625_constr.xdc" ]
ipx::save_core [ipx::current_core]

61
library/axi_ad9643/axi_ad9643.v
View File

@ -153,7 +153,8 @@ module axi_ad9643 (
reg up_status_pn_oos = 'd0;
reg up_status_or = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_ack = 'd0;
reg up_rack = 'd0;
reg up_wack = 'd0;
// internal clocks & resets
@ -185,12 +186,14 @@ module axi_ad9643 (
wire [ 4:0] delay_rdata_s;
wire delay_ack_t_s;
wire delay_locked_s;
wire up_sel_s;
wire up_wr_s;
wire [13:0] up_addr_s;
wire [31:0] up_wdata_s;
wire [31:0] up_rdata_s[0:2];
wire up_ack_s[0:2];
wire up_rack_s[0:2];
wire up_wack_s[0:2];
wire up_wreq_s;
wire [13:0] up_waddr_s;
wire [31:0] up_wdata_s;
wire up_rreq_s;
wire [13:0] up_raddr_s;
// signal name changes
@ -210,13 +213,15 @@ module axi_ad9643 (
up_status_pn_oos <= 'd0;
up_status_or <= 'd0;
up_rdata <= 'd0;
up_ack <= 'd0;
up_rack <= 'd0;
up_wack <= 'd0;
end else begin
up_status_pn_err <= up_status_pn_err_s[0] | up_status_pn_err_s[1];
up_status_pn_oos <= up_status_pn_oos_s[0] | up_status_pn_oos_s[1];
up_status_or <= up_status_or_s[0] | up_status_or_s[1];
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2];
up_ack <= up_ack_s[0] | up_ack_s[1] | up_ack_s[2];
up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2];
up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2];
end
end
@ -240,12 +245,14 @@ module axi_ad9643 (
.up_adc_or (up_status_or_s[0]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[0]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[0]),
.up_ack (up_ack_s[0]));
.up_rack (up_rack_s[0]));
// channel
@ -267,12 +274,14 @@ module axi_ad9643 (
.up_adc_or (up_status_or_s[1]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[1]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[1]),
.up_ack (up_ack_s[1]));
.up_rack (up_rack_s[1]));
// main (device interface)
@ -344,12 +353,14 @@ module axi_ad9643 (
.up_adc_gpio_out (up_adc_gpio_out),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[2]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[2]),
.up_ack (up_ack_s[2]));
.up_rack (up_rack_s[2]));
// up bus interface
@ -373,12 +384,14 @@ module axi_ad9643 (
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata),
.up_ack (up_ack));
.up_rack (up_rack));
endmodule

30
library/axi_ad9643/axi_ad9643_channel.v
View File

@ -63,12 +63,14 @@ module axi_ad9643_channel (
up_rstn,
up_clk,
up_sel,
up_wr,
up_addr,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_ack);
up_rack);
// parameters
@ -97,12 +99,14 @@ module axi_ad9643_channel (
input up_rstn;
input up_clk;
input up_sel;
input up_wr;
input [13:0] up_addr;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_ack;
output up_rack;
// internal signals
@ -220,12 +224,14 @@ module axi_ad9643_channel (
.adc_usr_decimation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),
.up_wr (up_wr),
.up_addr (up_addr),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_ack (up_ack));
.up_rack (up_rack));
endmodule

3
library/axi_ad9643/axi_ad9643_constr.xdc Executable file
View File

@ -0,0 +1,3 @@
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports adc_clk]]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports s_axi_aclk]]

3
library/axi_ad9643/axi_ad9643_ip.tcl
View File

@ -24,9 +24,12 @@ adi_ip_files axi_ad9643 [list \
"axi_ad9643_pnmon.v" \
"axi_ad9643_channel.v" \
"axi_ad9643_if.v" \
"axi_ad9643_constr.xdc" \
"axi_ad9643.v" ]
adi_ip_properties axi_ad9643
adi_ip_constraints axi_ad9643 [list \
"axi_ad9643_constr.xdc" ]
ipx::save_core [ipx::current_core]

61
library/axi_ad9652/axi_ad9652.v
View File

@ -153,7 +153,8 @@ module axi_ad9652 (
reg up_status_pn_oos = 'd0;
reg up_status_or = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_ack = 'd0;
reg up_rack = 'd0;
reg up_wack = 'd0;
// internal clocks & resets
@ -184,12 +185,14 @@ module axi_ad9652 (
wire [ 4:0] delay_rdata_s;
wire delay_ack_t_s;
wire delay_locked_s;
wire up_sel_s;
wire up_wr_s;
wire [13:0] up_addr_s;
wire [31:0] up_wdata_s;
wire [31:0] up_rdata_s[0:2];
wire up_ack_s[0:2];
wire up_rack_s[0:2];
wire up_wack_s[0:2];
wire up_wreq_s;
wire [13:0] up_waddr_s;
wire [31:0] up_wdata_s;
wire up_rreq_s;
wire [13:0] up_raddr_s;
// signal name changes
@ -209,13 +212,15 @@ module axi_ad9652 (
up_status_pn_oos <= 'd0;
up_status_or <= 'd0;
up_rdata <= 'd0;
up_ack <= 'd0;
up_rack <= 'd0;
up_wack <= 'd0;
end else begin
up_status_pn_err <= up_status_pn_err_s[0] | up_status_pn_err_s[1];
up_status_pn_oos <= up_status_pn_oos_s[0] | up_status_pn_oos_s[1];
up_status_or <= up_status_or_s[0] | up_status_or_s[1];
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2];
up_ack <= up_ack_s[0] | up_ack_s[1] | up_ack_s[2];
up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2];
up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2];
end
end
@ -239,12 +244,14 @@ module axi_ad9652 (
.up_adc_or (up_status_or_s[0]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[0]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[0]),
.up_ack (up_ack_s[0]));
.up_rack (up_rack_s[0]));
// channel
@ -266,12 +273,14 @@ module axi_ad9652 (
.up_adc_or (up_status_or_s[1]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[1]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[1]),
.up_ack (up_ack_s[1]));
.up_rack (up_rack_s[1]));
// main (device interface)
@ -342,12 +351,14 @@ module axi_ad9652 (
.up_adc_gpio_out (up_adc_gpio_out),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[2]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[2]),
.up_ack (up_ack_s[2]));
.up_rack (up_rack_s[2]));
// up bus interface
@ -371,12 +382,14 @@ module axi_ad9652 (
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata),
.up_ack (up_ack));
.up_rack (up_rack));
endmodule

30
library/axi_ad9652/axi_ad9652_channel.v
View File

@ -63,12 +63,14 @@ module axi_ad9652_channel (
up_rstn,
up_clk,
up_sel,
up_wr,
up_addr,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_ack);
up_rack);
// parameters
@ -97,12 +99,14 @@ module axi_ad9652_channel (
input up_rstn;
input up_clk;
input up_sel;
input up_wr;
input [13:0] up_addr;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_ack;
output up_rack;
// internal signals
@ -200,12 +204,14 @@ module axi_ad9652_channel (
.adc_usr_decimation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),
.up_wr (up_wr),
.up_addr (up_addr),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_ack (up_ack));
.up_rack (up_rack));
endmodule

109
library/axi_ad9671/axi_ad9671.v
View File

@ -1,9 +1,9 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
//
// All rights reserved.
//
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
@ -21,16 +21,16 @@
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
@ -41,11 +41,12 @@
module axi_ad9671 (
// jesd interface
// jesd interface
// rx_clk is (line-rate/40)
rx_clk,
rx_data,
rx_data_sof,
// dma interface
@ -55,6 +56,10 @@ module axi_ad9671 (
adc_data,
adc_dovf,
adc_dunf,
adc_sync_in,
adc_sync_out,
adc_raddr_in,
adc_raddr_out,
// axi interface
@ -62,6 +67,7 @@ module axi_ad9671 (
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awprot,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
@ -72,6 +78,7 @@ module axi_ad9671 (
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arprot,
s_axi_arready,
s_axi_rvalid,
s_axi_rresp,
@ -84,11 +91,12 @@ module axi_ad9671 (
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
parameter C_S_AXI_MIN_SIZE = 32'hffff;
// jesd interface
// jesd interface
// rx_clk is the jesd clock (ref_clk/2)
input rx_clk;
input [(64*PCORE_4L_2L_N)+63:0] rx_data;
input rx_data_sof;
// dma interface
@ -98,6 +106,10 @@ module axi_ad9671 (
output [127:0] adc_data;
input adc_dovf;
input adc_dunf;
input adc_sync_in;
output adc_sync_out;
input [ 3:0] adc_raddr_in;
output [ 3:0] adc_raddr_out;
// axi interface
@ -105,6 +117,7 @@ module axi_ad9671 (
input s_axi_aresetn;
input s_axi_awvalid;
input [ 31:0] s_axi_awaddr;
input [ 2:0] s_axi_awprot;
output s_axi_awready;
input s_axi_wvalid;
input [ 31:0] s_axi_wdata;
@ -115,6 +128,7 @@ module axi_ad9671 (
input s_axi_bready;
input s_axi_arvalid;
input [ 31:0] s_axi_araddr;
input [ 2:0] s_axi_arprot;
output s_axi_arready;
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
@ -127,7 +141,8 @@ module axi_ad9671 (
reg up_status_pn_oos = 'd0;
reg up_status_or = 'd0;
reg [ 31:0] up_rdata = 'd0;
reg up_ack = 'd0;
reg up_rack = 'd0;
reg up_wack = 'd0;
// internal clocks & resets
@ -138,18 +153,23 @@ module axi_ad9671 (
// internal signals
wire adc_status_s;
wire adc_sync_status_s;
wire adc_valid_s;
wire [ 15:0] adc_data_s[7:0];
wire [ 7:0] adc_or_s;
wire [ 7:0] up_adc_pn_err_s;
wire [ 7:0] up_adc_pn_oos_s;
wire [ 7:0] up_adc_or_s;
wire up_sel_s;
wire up_wr_s;
wire [ 13:0] up_addr_s;
wire up_wreq_s;
wire [ 13:0] up_waddr_s;
wire [ 31:0] up_wdata_s;
wire up_rreq_s;
wire [ 13:0] up_raddr_s;
wire [ 31:0] up_rdata_s[8:0];
wire up_ack_s[8:0];
wire up_rack_s[8:0];
wire up_wack_s[8:0];
wire [ 31:0] adc_start_code;
wire adc_sync;
// signal name changes
@ -164,23 +184,30 @@ module axi_ad9671 (
up_status_pn_oos <= 'd0;
up_status_or <= 'd0;
up_rdata <= 'd0;
up_ack <= 'd0;
up_rack <= 'd0;
up_wack <= 'd0;
end else begin
up_status_pn_err <= | up_adc_pn_err_s;
up_status_pn_oos <= | up_adc_pn_oos_s;
up_status_or <= | up_adc_or_s;
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | up_rdata_s[3] |
up_rdata_s[4] | up_rdata_s[5] | up_rdata_s[6] | up_rdata_s[7] | up_rdata_s[8];
up_ack <= up_ack_s[0] | up_ack_s[1] | up_ack_s[2] | up_ack_s[3] |
up_ack_s[4] | up_ack_s[5] | up_ack_s[6] | up_ack_s[7] | up_ack_s[8];
up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2] | up_rack_s[3] |
up_rack_s[4] | up_rack_s[5] | up_rack_s[6] | up_rack_s[7] | up_rack_s[8];
up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2] | up_wack_s[3] |
up_wack_s[4] | up_wack_s[5] | up_wack_s[6] | up_wack_s[7] | up_wack_s[8];
end
end
// main (device interface)
axi_ad9671_if #(.PCORE_4L_2L_N(PCORE_4L_2L_N)) i_if (
axi_ad9671_if #(
.PCORE_4L_2L_N(PCORE_4L_2L_N),
.PCORE_ID(PCORE_ID)
) i_if (
.rx_clk (rx_clk),
.rx_data (rx_data),
.rx_data_sof (rx_data_sof),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_valid (adc_valid_s),
@ -200,7 +227,14 @@ module axi_ad9671 (
.adc_or_g (adc_or_s[6]),
.adc_data_h (adc_data_s[7]),
.adc_or_h (adc_or_s[7]),
.adc_status (adc_status_s));
.adc_start_code (adc_start_code),
.adc_sync (adc_sync),
.adc_sync_in (adc_sync_in),
.adc_sync_out (adc_sync_out),
.adc_sync_status (adc_sync_status_s),
.adc_status (adc_status_s),
.adc_raddr_in(adc_raddr_in),
.adc_raddr_out(adc_raddr_out));
// channels
@ -221,24 +255,31 @@ module axi_ad9671 (
.up_adc_or (up_adc_or_s[n]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[n]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[n]),
.up_ack (up_ack_s[n]));
.up_rack (up_rack_s[n]));
end
endgenerate
// common processor control
up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common (
up_adc_common #(
.PCORE_ID(PCORE_ID)
) i_up_adc_common (
.mmcm_rst (),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_r1_mode (),
.adc_ddr_edgesel (),
.adc_pin_mode (),
.adc_start_code (adc_start_code),
.adc_sync (adc_sync),
.adc_sync_status (adc_sync_status_s),
.adc_status (adc_status_s),
.adc_status_ovf (adc_dovf),
.adc_status_unf (adc_dunf),
@ -270,16 +311,20 @@ module axi_ad9671 (
.up_adc_gpio_out (),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[8]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[8]),
.up_ack (up_ack_s[8]));
.up_rack (up_rack_s[8]));
// up bus interface
up_axi i_up_axi (
up_axi #(
.PCORE_ADDR_WIDTH (14)
) i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
@ -299,12 +344,14 @@ module axi_ad9671 (
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata),
.up_ack (up_ack));
.up_rack (up_rack));
endmodule

206
library/axi_ad9671/axi_ad9671_alt.v
View File

@ -1,206 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9671_alt (
// jesd interface
// rx_clk is (line-rate/40)
rx_clk,
rx_data,
// dma interface
adc_clk,
adc_valid,
adc_enable,
adc_data,
adc_dovf,
adc_dunf,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awid,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bid,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arid,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arready,
s_axi_rvalid,
s_axi_rresp,
s_axi_rdata,
s_axi_rid,
s_axi_rlast,
s_axi_rready);
parameter PCORE_ID = 0;
parameter PCORE_AXI_ID_WIDTH = 3;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_4L_2L_N = 1;
// jesd interface
// rx_clk is (line-rate/40)
input rx_clk;
input [(64*PCORE_4L_2L_N)+63:0] rx_data;
// dma interface
output adc_clk;
output [ 7:0] adc_valid;
output [ 7:0] adc_enable;
output [127:0] adc_data;
input adc_dovf;
input adc_dunf;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [13:0] s_axi_awaddr;
input [(PCORE_AXI_ID_WIDTH-1):0] s_axi_awid;
input [ 7:0] s_axi_awlen;
input [ 2:0] s_axi_awsize;
input [ 1:0] s_axi_awburst;
input [ 0:0] s_axi_awlock;
input [ 3:0] s_axi_awcache;
input [ 2:0] s_axi_awprot;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
input s_axi_wlast;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
output [(PCORE_AXI_ID_WIDTH-1):0] s_axi_bid;
input s_axi_bready;
input s_axi_arvalid;
input [13:0] s_axi_araddr;
input [(PCORE_AXI_ID_WIDTH-1):0] s_axi_arid;
input [ 7:0] s_axi_arlen;
input [ 2:0] s_axi_arsize;
input [ 1:0] s_axi_arburst;
input [ 0:0] s_axi_arlock;
input [ 3:0] s_axi_arcache;
input [ 2:0] s_axi_arprot;
output s_axi_arready;
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata;
output [(PCORE_AXI_ID_WIDTH-1):0] s_axi_rid;
output s_axi_rlast;
input s_axi_rready;
// defaults
assign s_axi_bid = s_axi_awid;
assign s_axi_rid = s_axi_arid;
assign s_axi_rlast = 1'd0;
// ad9671 lite version
axi_ad9671 #(
.PCORE_ID (PCORE_ID),
.PCORE_4L_2L_N (PCORE_4L_2L_N),
.PCORE_DEVICE_TYPE (PCORE_DEVICE_TYPE),
.PCORE_IODELAY_GROUP ("adc_if_delay_group"),
.C_S_AXI_MIN_SIZE (32'hffff))
i_ad9671 (
.rx_clk (rx_clk),
.rx_data (rx_data),
.adc_clk (adc_clk),
.adc_valid (adc_valid),
.adc_enable (adc_enable),
.adc_data (adc_data),
.adc_dovf (adc_dovf),
.adc_dunf (adc_dunf),
.s_axi_aclk (s_axi_aclk),
.s_axi_aresetn (s_axi_aresetn),
.s_axi_awvalid (s_axi_awvalid),
.s_axi_awaddr ({18'd0, s_axi_awaddr}),
.s_axi_awready (s_axi_awready),
.s_axi_wvalid (s_axi_wvalid),
.s_axi_wdata (s_axi_wdata),
.s_axi_wstrb (s_axi_wstrb),
.s_axi_wready (s_axi_wready),
.s_axi_bvalid (s_axi_bvalid),
.s_axi_bresp (s_axi_bresp),
.s_axi_bready (s_axi_bready),
.s_axi_arvalid (s_axi_arvalid),
.s_axi_araddr ({18'd0, s_axi_araddr}),
.s_axi_arready (s_axi_arready),
.s_axi_rvalid (s_axi_rvalid),
.s_axi_rresp (s_axi_rresp),
.s_axi_rdata (s_axi_rdata),
.s_axi_rready (s_axi_rready));
endmodule
// ***************************************************************************
// ***************************************************************************

30
library/axi_ad9671/axi_ad9671_channel.v
View File

@ -63,12 +63,14 @@ module axi_ad9671_channel (
up_rstn,
up_clk,
up_sel,
up_wr,
up_addr,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_ack);
up_rack);
// parameters
@ -95,12 +97,14 @@ module axi_ad9671_channel (
input up_rstn;
input up_clk;
input up_sel;
input up_wr;
input [13:0] up_addr;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_ack;
output up_rack;
// internal signals
@ -168,12 +172,14 @@ module axi_ad9671_channel (
.adc_usr_decimation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),
.up_wr (up_wr),
.up_addr (up_addr),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_ack (up_ack));
.up_rack (up_rack));
endmodule

50
library/axi_ad9671/axi_ad9671_hw.tcl
View File

@ -1,6 +1,6 @@
package require -exact qsys 13.0
package require -exact qsys 14.0
source ../scripts/adi_env.tcl
set_module_property NAME axi_ad9671
@ -11,7 +11,7 @@ set_module_property DISPLAY_NAME axi_ad9671
# files
add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
set_fileset_property quartus_synth TOP_LEVEL axi_ad9671_alt
set_fileset_property quartus_synth TOP_LEVEL axi_ad9671
add_fileset_file ad_rst.v VERILOG PATH $ad_hdl_dir/library/common/altera/ad_rst.v
add_fileset_file ad_pnmon.v VERILOG PATH $ad_hdl_dir/library/common/ad_pnmon.v
add_fileset_file ad_datafmt.v VERILOG PATH $ad_hdl_dir/library/common/ad_datafmt.v
@ -23,11 +23,11 @@ add_fileset_file up_drp_cntrl.v VERILOG PATH $ad_hdl_dir/library/common/up
add_fileset_file up_delay_cntrl.v VERILOG PATH $ad_hdl_dir/library/common/up_delay_cntrl.v
add_fileset_file up_adc_common.v VERILOG PATH $ad_hdl_dir/library/common/up_adc_common.v
add_fileset_file up_adc_channel.v VERILOG PATH $ad_hdl_dir/library/common/up_adc_channel.v
add_fileset_file ad_mem.v VERILOG PATH $ad_hdl_dir/library/common/ad_mem.v
add_fileset_file axi_ad9671_pnmon.v VERILOG PATH axi_ad9671_pnmon.v
add_fileset_file axi_ad9671_if.v VERILOG PATH axi_ad9671_if.v
add_fileset_file axi_ad9671_channel.v VERILOG PATH axi_ad9671_channel.v
add_fileset_file axi_ad9671.v VERILOG PATH axi_ad9671.v
add_fileset_file axi_ad9671_alt.v VERILOG PATH axi_ad9671_alt.v TOP_LEVEL_FILE
add_fileset_file axi_ad9671.v VERILOG PATH axi_ad9671.v TOP_LEVEL_FILE
# parameters
@ -52,13 +52,6 @@ set_parameter_property PCORE_4L_2L_N TYPE INTEGER
set_parameter_property PCORE_4L_2L_N UNITS None
set_parameter_property PCORE_4L_2L_N HDL_PARAMETER true
add_parameter PCORE_AXI_ID_WIDTH INTEGER 0
set_parameter_property PCORE_AXI_ID_WIDTH DEFAULT_VALUE 3
set_parameter_property PCORE_AXI_ID_WIDTH DISPLAY_NAME PCORE_AXI_ID_WIDTH
set_parameter_property PCORE_AXI_ID_WIDTH TYPE INTEGER
set_parameter_property PCORE_AXI_ID_WIDTH UNITS None
set_parameter_property PCORE_AXI_ID_WIDTH HDL_PARAMETER true
# axi4 slave
add_interface s_axi_clock clock end
@ -68,11 +61,12 @@ add_interface s_axi_reset reset end
set_interface_property s_axi_reset associatedClock s_axi_clock
add_interface_port s_axi_reset s_axi_aresetn reset_n Input 1
add_interface s_axi axi4 end
add_interface s_axi axi4lite end
set_interface_property s_axi associatedClock s_axi_clock
set_interface_property s_axi associatedReset s_axi_reset
add_interface_port s_axi s_axi_awvalid awvalid Input 1
add_interface_port s_axi s_axi_awaddr awaddr Input 14
add_interface_port s_axi s_axi_awprot awprot Input 3
add_interface_port s_axi s_axi_awready awready Output 1
add_interface_port s_axi s_axi_wvalid wvalid Input 1
add_interface_port s_axi s_axi_wdata wdata Input 32
@ -83,30 +77,12 @@ add_interface_port s_axi s_axi_bresp bresp Output 2
add_interface_port s_axi s_axi_bready bready Input 1
add_interface_port s_axi s_axi_arvalid arvalid Input 1
add_interface_port s_axi s_axi_araddr araddr Input 14
add_interface_port s_axi s_axi_arprot arprot Input 3
add_interface_port s_axi s_axi_arready arready Output 1
add_interface_port s_axi s_axi_rvalid rvalid Output 1
add_interface_port s_axi s_axi_rresp rresp Output 2
add_interface_port s_axi s_axi_rdata rdata Output 32
add_interface_port s_axi s_axi_rready rready Input 1
add_interface_port s_axi s_axi_awid awid Input PCORE_AXI_ID_WIDTH
add_interface_port s_axi s_axi_awlen awlen Input 8
add_interface_port s_axi s_axi_awsize awsize Input 3
add_interface_port s_axi s_axi_awburst awburst Input 2
add_interface_port s_axi s_axi_awlock awlock Input 1
add_interface_port s_axi s_axi_awcache awcache Input 4
add_interface_port s_axi s_axi_awprot awprot Input 3
add_interface_port s_axi s_axi_wlast wlast Input 1
add_interface_port s_axi s_axi_bid bid Output PCORE_AXI_ID_WIDTH
add_interface_port s_axi s_axi_arid arid Input PCORE_AXI_ID_WIDTH
add_interface_port s_axi s_axi_arlen arlen Input 8
add_interface_port s_axi s_axi_arsize arsize Input 3
add_interface_port s_axi s_axi_arburst arburst Input 2
add_interface_port s_axi s_axi_arlock arlock Input 1
add_interface_port s_axi s_axi_arcache arcache Input 4
add_interface_port s_axi s_axi_arprot arprot Input 3
add_interface_port s_axi s_axi_rid rid Output PCORE_AXI_ID_WIDTH
add_interface_port s_axi s_axi_rlast rlast Output 1
# transceiver interface
@ -116,6 +92,14 @@ add_interface_port xcvr_clk rx_clk clk Input 1
add_interface xcvr_data conduit end
set_interface_property xcvr_data associatedClock xcvr_clk
add_interface_port xcvr_data rx_data data Input 64*PCORE_4L_2L_N+64
add_interface_port xcvr_data rx_data_sof data_sof Input 1
add_interface xcvr_sync conduit end
set_interface_property xcvr_sync associatedClock xcvr_clk
add_interface_port xcvr_sync adc_sync_in sync_in Input 1
add_interface_port xcvr_sync adc_sync_out sync_out Output 1
add_interface_port xcvr_sync adc_raddr_in raddr_in Input 4
add_interface_port xcvr_sync adc_raddr_out raddr_out Output 4
# dma interface
@ -124,8 +108,8 @@ add_interface_port adc_clock adc_clk clk Output 1
add_interface adc_dma_if conduit end
set_interface_property adc_dma_if associatedClock adc_clock
add_interface_port adc_dma_if adc_valid valid Output 7
add_interface_port adc_dma_if adc_enable enable Output 7
add_interface_port adc_dma_if adc_valid valid Output 8
add_interface_port adc_dma_if adc_enable enable Output 8
add_interface_port adc_dma_if adc_data data Output 128
add_interface_port adc_dma_if adc_dovf dovf Input 1
add_interface_port adc_dma_if adc_dunf dunf Input 1

117
library/axi_ad9671/axi_ad9671_if.v
View File

@ -46,6 +46,7 @@ module axi_ad9671_if (
// rx_clk is (line-rate/40)
rx_clk,
rx_data_sof,
rx_data,
// adc data output
@ -69,16 +70,25 @@ module axi_ad9671_if (
adc_or_g,
adc_data_h,
adc_or_h,
adc_status);
adc_start_code,
adc_sync_in,
adc_sync_out,
adc_sync,
adc_sync_status,
adc_status,
adc_raddr_in,
adc_raddr_out);
// parameters
parameter PCORE_4L_2L_N = 1;
parameter PCORE_ID = 0;
// jesd interface
// rx_clk is (line-rate/40)
input rx_clk;
input rx_data_sof;
input [(64*PCORE_4L_2L_N)+63:0] rx_data;
// adc data output
@ -102,18 +112,53 @@ module axi_ad9671_if (
output adc_or_g;
output [ 15:0] adc_data_h;
output adc_or_h;
input [ 31:0] adc_start_code;
input adc_sync_in;
output adc_sync_out;
input adc_sync;
output adc_sync_status;
output adc_status;
input [ 3:0] adc_raddr_in;
output [ 3:0] adc_raddr_out;
// internal wires
wire [127:0] adc_wdata;
wire [127:0] adc_rdata;
wire [ 15:0] adc_data_a_s;
wire [ 15:0] adc_data_b_s;
wire [ 15:0] adc_data_c_s;
wire [ 15:0] adc_data_d_s;
wire [ 15:0] adc_data_e_s;
wire [ 15:0] adc_data_f_s;
wire [ 15:0] adc_data_g_s;
wire [ 15:0] adc_data_h_s;
wire [ 3:0] adc_raddr_s;
wire adc_sync_s;
// internal registers
reg int_valid = 'd0;
reg [127:0] int_data = 'd0;
reg adc_status = 'd0;
reg adc_sync_status = 'd0;
reg [ 3:0] adc_waddr = 'd0;
reg [ 3:0] adc_raddr_out = 'd0;
reg [ 15:0] adc_data_a;
reg [ 15:0] adc_data_b;
reg [ 15:0] adc_data_c;
reg [ 15:0] adc_data_d;
reg [ 15:0] adc_data_e;
reg [ 15:0] adc_data_f;
reg [ 15:0] adc_data_g;
reg [ 15:0] adc_data_h;
// adc clock & valid
assign adc_clk = rx_clk;
assign adc_valid = int_valid;
assign adc_sync_out = adc_sync;
assign adc_or_a = 'd0;
assign adc_or_b = 'd0;
@ -123,23 +168,62 @@ module axi_ad9671_if (
assign adc_or_f = 'd0;
assign adc_or_g = 'd0;
assign adc_or_h = 'd0;
assign adc_data_a = {int_data[ 7: 0], int_data[ 15: 8]};
assign adc_data_b = {int_data[ 23: 16], int_data[ 31: 24]};
assign adc_data_c = {int_data[ 39: 32], int_data[ 47: 40]};
assign adc_data_d = {int_data[ 55: 48], int_data[ 63: 56]};
assign adc_data_e = {int_data[ 71: 64], int_data[ 79: 72]};
assign adc_data_f = {int_data[ 87: 80], int_data[ 95: 88]};
assign adc_data_g = {int_data[103: 96], int_data[111:104]};
assign adc_data_h = {int_data[119:112], int_data[127:120]};
assign adc_data_a_s = {int_data[ 7: 0], int_data[ 15: 8]};
assign adc_data_b_s = {int_data[ 23: 16], int_data[ 31: 24]};
assign adc_data_c_s = {int_data[ 39: 32], int_data[ 47: 40]};
assign adc_data_d_s = {int_data[ 55: 48], int_data[ 63: 56]};
assign adc_data_e_s = {int_data[ 71: 64], int_data[ 79: 72]};
assign adc_data_f_s = {int_data[ 87: 80], int_data[ 95: 88]};
assign adc_data_g_s = {int_data[103: 96], int_data[111:104]};
assign adc_data_h_s = {int_data[119:112], int_data[127:120]};
assign adc_wdata = {adc_data_h_s, adc_data_g_s, adc_data_f_s, adc_data_e_s,
adc_data_d_s, adc_data_c_s, adc_data_b_s, adc_data_a_s};
assign adc_raddr_s = (PCORE_ID == 0) ? adc_raddr_out : adc_raddr_in;
assign adc_sync_s = (PCORE_ID == 0) ? adc_sync_out : adc_sync_in;
always @(posedge rx_clk) begin
adc_data_a <= adc_rdata[ 15: 0];
adc_data_b <= adc_rdata[ 31: 16];
adc_data_c <= adc_rdata[ 47: 32];
adc_data_d <= adc_rdata[ 63: 48];
adc_data_e <= adc_rdata[ 79: 64];
adc_data_f <= adc_rdata[ 95: 80];
adc_data_g <= adc_rdata[111: 96];
adc_data_h <= adc_rdata[127:112];
end
always @(posedge rx_clk) begin
if (adc_rst == 1'b1) begin
adc_waddr <= 4'h0;
adc_raddr_out <= 4'h8;
adc_sync_status <= 1'b0;
end else begin
if (adc_data_a_s == adc_start_code[15:0] && adc_sync_status == 1'b1) begin
adc_sync_status <= 1'b0;
end else if(adc_sync_s == 1'b1) begin
adc_sync_status <= 1'b1;
end
if (adc_data_a_s == adc_start_code[15:0] && adc_sync_status == 1'b1) begin
adc_waddr <= 4'h0;
adc_raddr_out <= 4'h8;
end else if (int_valid == 1'b1) begin
adc_waddr <= adc_waddr + 1;
adc_raddr_out <= adc_raddr_out + 1;
end
end
end
always @(posedge rx_clk) begin
if (PCORE_4L_2L_N == 1'b1) begin
int_valid <= 1'b1;
int_data <= rx_data;
end else begin
int_valid <= ~int_valid;
int_data <= {rx_data[63:0], int_data[127:64]};
int_valid <= !rx_data_sof;
int_data[63:0] <= {rx_data[31:0], int_data[63:32]};
int_data[127:64] <= {rx_data[63:32], int_data[127:96]};
end
end
@ -151,6 +235,15 @@ module axi_ad9671_if (
end
end
ad_mem #(.ADDR_WIDTH(4), .DATA_WIDTH(128)) i_mem (
.clka(rx_clk),
.wea(int_valid),
.addra(adc_waddr),
.dina(adc_wdata),
.clkb(rx_clk),
.addrb(adc_raddr_s),
.doutb(adc_rdata));
endmodule
// ***************************************************************************

1
library/axi_ad9671/axi_ad9671_ip.tcl
View File

@ -16,6 +16,7 @@ adi_ip_files axi_ad9671 [list \
"$ad_hdl_dir/library/common/up_delay_cntrl.v" \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"$ad_hdl_dir/library/common/ad_mem.v" \
"axi_ad9671_pnmon.v" \
"axi_ad9671_channel.v" \
"axi_ad9671_if.v" \

59
library/axi_ad9680/axi_ad9680.v
View File

@ -132,7 +132,8 @@ module axi_ad9680 (
reg up_status_pn_oos = 'd0;
reg up_status_or = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_ack = 'd0;
reg up_rack = 'd0;
reg up_wack = 'd0;
// internal clocks & resets
@ -151,11 +152,13 @@ module axi_ad9680 (
wire [ 1:0] up_adc_pn_oos_s;
wire [ 1:0] up_adc_or_s;
wire [31:0] up_rdata_s[0:2];
wire up_ack_s[0:2];
wire up_sel_s;
wire up_wr_s;
wire [13:0] up_addr_s;
wire up_rack_s[0:2];
wire up_wack_s[0:2];
wire up_wreq_s;
wire [13:0] up_waddr_s;
wire [31:0] up_wdata_s;
wire up_rreq_s;
wire [13:0] up_raddr_s;
// signal name changes
@ -175,13 +178,15 @@ module axi_ad9680 (
up_status_pn_oos <= 'd0;
up_status_or <= 'd0;
up_rdata <= 'd0;
up_ack <= 'd0;
up_rack <= 'd0;
up_wack <= 'd0;
end else begin
up_status_pn_err <= | up_adc_pn_err_s;
up_status_pn_oos <= | up_adc_pn_oos_s;
up_status_or <= | up_adc_or_s;
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2];
up_ack <= up_ack_s[0] | up_ack_s[1] | up_ack_s[2];
up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2];
up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2];
end
end
@ -212,12 +217,14 @@ module axi_ad9680 (
.up_adc_or (up_adc_or_s[0]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[0]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[0]),
.up_ack (up_ack_s[0]));
.up_rack (up_rack_s[0]));
// channel
@ -233,12 +240,14 @@ module axi_ad9680 (
.up_adc_or (up_adc_or_s[1]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[1]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[1]),
.up_ack (up_ack_s[1]));
.up_rack (up_rack_s[1]));
// common processor control
@ -280,12 +289,14 @@ module axi_ad9680 (
.up_adc_gpio_out (),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[2]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[2]),
.up_ack (up_ack_s[2]));
.up_rack (up_rack_s[2]));
// up bus interface
@ -309,12 +320,14 @@ module axi_ad9680 (
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata),
.up_ack (up_ack));
.up_rack (up_rack));
endmodule

30
library/axi_ad9680/axi_ad9680_channel.v
View File

@ -61,12 +61,14 @@ module axi_ad9680_channel (
up_rstn,
up_clk,
up_sel,
up_wr,
up_addr,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_ack);
up_rack);
// parameters
@ -92,12 +94,14 @@ module axi_ad9680_channel (
input up_rstn;
input up_clk;
input up_sel;
input up_wr;
input [13:0] up_addr;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_ack;
output up_rack;
// internal signals
@ -169,12 +173,14 @@ module axi_ad9680_channel (
.adc_usr_decimation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),
.up_wr (up_wr),
.up_addr (up_addr),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_ack (up_ack));
.up_rack (up_rack));
endmodule

2
library/axi_ad9680/axi_ad9680_constr.xdc
View File

@ -1,5 +1,5 @@
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports adc_clk]]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports rx_clk]]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports s_axi_aclk]]

3
library/axi_ad9680/axi_ad9680_ip.tcl
View File

@ -19,7 +19,8 @@ adi_ip_files axi_ad9680 [list \
"axi_ad9680_pnmon.v" \
"axi_ad9680_channel.v" \
"axi_ad9680_if.v" \
"axi_ad9680.v" ]
"axi_ad9680.v" \
"axi_ad9680_constr.xdc" ]
adi_ip_properties axi_ad9680
adi_ip_constraints axi_ad9680 [list \

30
library/axi_clkgen/axi_clkgen.v
View File

@ -125,12 +125,14 @@ module axi_clkgen (
wire [15:0] drp_rdata_s;
wire drp_ready_s;
wire drp_locked_s;
wire up_sel_s;
wire up_wr_s;
wire [13:0] up_addr_s;
wire up_wreq_s;
wire [13:0] up_waddr_s;
wire [31:0] up_wdata_s;
wire up_wack_s;
wire up_rreq_s;
wire [13:0] up_raddr_s;
wire [31:0] up_rdata_s;
wire up_ack_s;
wire up_rack_s;
// signal name changes
@ -159,12 +161,14 @@ module axi_clkgen (
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_ack (up_ack_s));
.up_rack (up_rack_s));
// processor interface
@ -181,12 +185,14 @@ module axi_clkgen (
.drp_locked (drp_locked_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_ack (up_ack_s));
.up_rack (up_rack_s));
// mmcm instantiations

54
library/axi_dmac/axi_dmac.v
View File

@ -146,6 +146,7 @@ module axi_dmac (
input s_axis_valid,
input [C_DMA_DATA_WIDTH_SRC-1:0] s_axis_data,
input [0:0] s_axis_user,
output s_axis_xfer_req,
// Master streaming AXI interface
input m_axis_aclk,
@ -222,11 +223,13 @@ localparam BYTES_PER_BEAT_WIDTH_SRC = C_DMA_DATA_WIDTH_SRC > 1024 ? 8 :
// Register interface signals
reg [31:0] up_rdata = 'd0;
reg up_ack = 1'b0;
wire up_wr;
wire up_sel;
reg up_wack = 1'b0;
reg up_rack = 1'b0;
wire up_wreq;
wire up_rreq;
wire [31:0] up_wdata;
wire [11:0] up_addr;
wire [11:0] up_waddr;
wire [11:0] up_raddr;
wire up_write;
// Scratch register
@ -275,6 +278,22 @@ wire [2:0] src_address_id;
wire [2:0] src_response_id;
wire [7:0] dbg_status;
assign m_dest_axi_araddr = 'd0;
assign m_dest_axi_arlen = 'd0;
assign m_dest_axi_arsize = 'd0;
assign m_dest_axi_arburst = 'd0;
assign m_dest_axi_arcache = 'd0;
assign m_dest_axi_arprot = 'd0;
assign m_src_axi_awaddr = 'd0;
assign m_src_axi_awlen = 'd0;
assign m_src_axi_awsize = 'd0;
assign m_src_axi_awburst = 'd0;
assign m_src_axi_awcache = 'd0;
assign m_src_axi_awprot = 'd0;
assign m_src_axi_wdata = 'd0;
assign m_src_axi_wstrb = 'd0;
assign m_src_axi_wlast = 'd0;
up_axi #(
.PCORE_ADDR_WIDTH (12)
) i_up_axi (
@ -297,18 +316,20 @@ up_axi #(
.up_axi_rresp(s_axi_rresp),
.up_axi_rdata(s_axi_rdata),
.up_axi_rready(s_axi_rready),
.up_wr(up_wr),
.up_sel(up_sel),
.up_addr(up_addr),
.up_wreq(up_wreq),
.up_waddr(up_waddr),
.up_wdata(up_wdata),
.up_wack(up_wack),
.up_rreq(up_rreq),
.up_raddr(up_raddr),
.up_rdata(up_rdata),
.up_ack(up_ack)
.up_rack(up_rack)
);
// IRQ handling
assign up_irq_pending = ~up_irq_mask & up_irq_source;
assign up_irq_trigger = {up_eot, up_sot};
assign up_irq_source_clear = (up_write == 1'b1 && up_addr == 12'h021) ? up_wdata[1:0] : 0;
assign up_irq_source_clear = (up_write == 1'b1 && up_waddr == 12'h021) ? up_wdata[1:0] : 0;
always @(posedge s_axi_aclk)
begin
@ -328,7 +349,7 @@ begin
end
// Register Interface
assign up_write = up_wr & up_sel;
assign up_write = up_wreq;
always @(posedge s_axi_aclk)
begin
@ -344,11 +365,11 @@ begin
up_irq_mask <= 3'b11;
up_dma_req_valid <= 1'b0;
up_scratch <= 'h00;
up_ack <= 1'b0;
up_wack <= 1'b0;
end else begin
up_ack <= up_sel;
up_wack <= up_wreq;
if (up_enable == 1'b1) begin
if (up_write && up_addr == 12'h102) begin
if (up_write && up_waddr == 12'h102) begin
up_dma_req_valid <= up_dma_req_valid | up_wdata[0];
end else if (up_sot) begin
up_dma_req_valid <= 1'b0;
@ -358,7 +379,7 @@ begin
end
if (up_write) begin
case (up_addr)
case (up_waddr)
12'h002: up_scratch <= up_wdata;
12'h020: up_irq_mask <= up_wdata;
12'h100: {up_pause, up_enable} <= up_wdata[1:0];
@ -377,9 +398,11 @@ end
always @(posedge s_axi_aclk)
begin
if (s_axi_aresetn == 1'b0) begin
up_rack <= 'd0;
up_rdata <= 'h00;
end else begin
case (up_addr)
up_rack <= up_rreq;
case (up_raddr)
12'h000: up_rdata <= PCORE_VERSION;
12'h001: up_rdata <= PCORE_ID;
12'h002: up_rdata <= up_scratch;
@ -565,6 +588,7 @@ dmac_request_arb #(
.s_axis_valid(s_axis_valid),
.s_axis_data(s_axis_data),
.s_axis_user(s_axis_user),
.s_axis_xfer_req(s_axis_xfer_req),
.m_axis_aclk(m_axis_aclk),

24
library/axi_dmac/axi_dmac_constr.tcl Normal file
View File

@ -0,0 +1,24 @@
if { [get_clocks -quiet -of_objects [get_ports s_axi_aclk]] != ""} {
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports s_axi_aclk]]
}
if { [get_clocks -quiet -of_objects [get_ports m_dest_axi_aclk]] != ""} {
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports m_dest_axi_aclk]]
}
if { [get_clocks -quiet -of_objects [get_ports m_src_axi_aclk]] != ""} {
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports m_src_axi_aclk]]
}
if { [get_clocks -quiet -of_objects [get_ports s_axis_aclk]] != ""} {
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports s_axis_aclk]]
}
if { [get_clocks -quiet -of_objects [get_ports m_axis_aclk]] != ""} {
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports m_axis_aclk]]
}
if { [get_clocks -quiet -of_objects [get_ports fifo_rd_clk]] != ""} {
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports fifo_rd_clk]]
}

9
library/axi_dmac/axi_dmac_constr.xdc
View File

@ -1,9 +0,0 @@
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports fifo_wr_clk]]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports m_dest_axi_aclk]]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports fifo_rd_clk]]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports m_src_axi_aclk]]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports s_axi_aclk]]

5
library/axi_dmac/axi_dmac_ip.tcl
View File

@ -28,11 +28,12 @@ adi_ip_files axi_dmac [list \
"splitter.v" \
"response_generator.v" \
"axi_dmac.v" \
"axi_repack.v" ]
"axi_repack.v" \
"axi_dmac_constr.tcl" ]
adi_ip_properties axi_dmac
adi_ip_constraints axi_dmac [list \
"axi_dmac_constr.xdc" ]
"axi_dmac_constr.tcl" ]
set_property physical_name {s_axi_aclk} [ipx::get_port_map CLK \
[ipx::get_bus_interface s_axi_signal_clock [ipx::current_core]]]

4
library/axi_dmac/request_arb.v
View File

@ -102,6 +102,7 @@ module dmac_request_arb (
input s_axis_valid,
input [C_DMA_DATA_WIDTH_SRC-1:0] s_axis_data,
input [0:0] s_axis_user,
output s_axis_xfer_req,
// Master streaming AXI interface
input m_axis_aclk,
@ -691,7 +692,8 @@ dmac_src_axi_stream #(
.s_axis_valid(s_axis_valid),
.s_axis_ready(s_axis_ready),
.s_axis_data(s_axis_data),
.s_axis_user(s_axis_user)
.s_axis_user(s_axis_user),
.s_axis_xfer_req(s_axis_xfer_req)
);
end else begin

3
library/axi_dmac/src_axi_stream.v
View File

@ -53,6 +53,7 @@ module dmac_src_axi_stream (
input s_axis_valid,
input [C_S_AXIS_DATA_WIDTH-1:0] s_axis_data,
input [0:0] s_axis_user,
output s_axis_xfer_req,
input fifo_ready,
output fifo_valid,
@ -101,6 +102,8 @@ dmac_data_mover # (
.enabled(enabled),
.sync_id(sync_id),
.xfer_req(s_axis_xfer_req),
.request_id(request_id),
.response_id(response_id),
.eot(eot),

245
library/axi_fifo2f/axi_fifo2f.v Normal file
View File

@ -0,0 +1,245 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_fifo2f (
// fifo interface
adc_rst,
adc_clk,
adc_wr,
adc_wdata,
adc_wovf,
// dma interface
dma_clk,
dma_wr,
dma_wdata,
dma_wready,
dma_xfer_req,
dma_xfer_status);
// parameters
parameter ADC_DATA_WIDTH = 256;
parameter DMA_DATA_WIDTH = 64;
parameter DMA_READY_ENABLE = 1;
parameter DMA_ADDR_WIDTH = 10;
localparam DMA_MEM_RATIO = ADC_DATA_WIDTH/DMA_DATA_WIDTH;
localparam ADC_ADDR_WIDTH = (DMA_MEM_RATIO == 2) ? (DMA_ADDR_WIDTH - 1) :
((DMA_MEM_RATIO == 4) ? (DMA_ADDR_WIDTH - 2) : (DMA_ADDR_WIDTH - 3));
localparam ADC_ADDR_LIMIT = (2**ADC_ADDR_WIDTH)-1;
// adc interface
input adc_rst;
input adc_clk;
input adc_wr;
input [ADC_DATA_WIDTH-1:0] adc_wdata;
output adc_wovf;
// dma interface
input dma_clk;
output dma_wr;
output [DMA_DATA_WIDTH-1:0] dma_wdata;
input dma_wready;
input dma_xfer_req;
output [ 3:0] dma_xfer_status;
// internal registers
reg [ 2:0] adc_xfer_req_m = 'd0;
reg adc_xfer_init = 'd0;
reg adc_xfer_enable = 'd0;
reg adc_wr_int = 'd0;
reg [ADC_DATA_WIDTH-1:0] adc_wdata_int = 'd0;
reg [ADC_ADDR_WIDTH-1:0] adc_waddr_int = 'd0;
reg adc_waddr_rel_t = 'd0;
reg [ADC_ADDR_WIDTH-1:0] adc_waddr_rel = 'd0;
reg dma_rst = 'd0;
reg [ 2:0] dma_waddr_rel_t_m = 'd0;
reg [ADC_ADDR_WIDTH-1:0] dma_waddr_rel = 'd0;
reg dma_rd = 'd0;
reg dma_rd_d = 'd0;
reg [DMA_DATA_WIDTH-1:0] dma_rdata_d = 'd0;
reg [DMA_ADDR_WIDTH-1:0] dma_raddr = 'd0;
// internal signals
wire dma_waddr_rel_t_s;
wire [DMA_ADDR_WIDTH-1:0] dma_waddr_rel_s;
wire dma_wready_s;
wire dma_rd_s;
wire [DMA_DATA_WIDTH-1:0] dma_rdata_s;
// write interface
assign adc_wovf = 1'd0;
always @(posedge adc_clk or posedge adc_rst) begin
if (adc_rst == 1'b1) begin
adc_xfer_req_m <= 'd0;
adc_xfer_init <= 'd0;
adc_xfer_enable <= 'd0;
end else begin
adc_xfer_req_m <= {adc_xfer_req_m[1:0], dma_xfer_req};
adc_xfer_init <= adc_xfer_req_m[1] & ~adc_xfer_req_m[2];
if (adc_xfer_init == 1'b1) begin
adc_xfer_enable <= 1'b1;
end else if ((adc_waddr_int >= ADC_ADDR_LIMIT) ||
(adc_xfer_req_m[2] == 1'b0)) begin
adc_xfer_enable <= 1'b0;
end
end
end
always @(posedge adc_clk or posedge adc_rst) begin
if (adc_rst == 1'b1) begin
adc_wr_int <= 'd0;
adc_wdata_int <= 'd0;
adc_waddr_int <= 'd0;
end else begin
if (adc_xfer_init == 1'b1) begin
adc_wr_int <= 'd0;
adc_wdata_int <= 'd0;
adc_waddr_int <= 'd0;
end else begin
adc_wr_int <= adc_wr & adc_xfer_enable;
adc_wdata_int <= adc_wdata;
if (adc_wr_int == 1'b1) begin
adc_waddr_int <= adc_waddr_int + 1'b1;
end
end
end
end
always @(posedge adc_clk or posedge adc_rst) begin
if (adc_rst == 1'b1) begin
adc_waddr_rel_t <= 'd0;
adc_waddr_rel <= 'd0;
end else begin
if ((adc_wr_int == 1'b1) && (adc_waddr_int[2:0] == 3'd7)) begin
adc_waddr_rel_t <= ~adc_waddr_rel_t;
adc_waddr_rel <= adc_waddr_int;
end
end
end
// read interface
assign dma_xfer_status = 4'd0;
assign dma_waddr_rel_t_s = dma_waddr_rel_t_m[2] ^ dma_waddr_rel_t_m[1];
assign dma_waddr_rel_s = (DMA_MEM_RATIO == 2) ? {dma_waddr_rel, 1'd0} :
((DMA_MEM_RATIO == 4) ? {dma_waddr_rel, 2'd0} : {dma_waddr_rel, 3'd0});
always @(posedge dma_clk) begin
if (dma_xfer_req == 1'b0) begin
dma_rst <= 1'b1;
dma_waddr_rel_t_m <= 'd0;
dma_waddr_rel <= 'd0;
end else begin
dma_rst <= 1'b0;
dma_waddr_rel_t_m <= {dma_waddr_rel_t_m[1:0], adc_waddr_rel_t};
if (dma_waddr_rel_t_s == 1'b1) begin
dma_waddr_rel <= adc_waddr_rel;
end
end
end
always @(posedge dma_clk) begin
if (dma_xfer_req == 1'b0) begin
end else begin
end
end
assign dma_wready_s = (DMA_READY_ENABLE == 0) ? 1'b1 : dma_wready;
assign dma_rd_s = (dma_raddr >= dma_waddr_rel_s) ? 1'b0 : dma_wready_s;
always @(posedge dma_clk) begin
if (dma_xfer_req == 1'b0) begin
dma_rd <= 'd0;
dma_rd_d <= 'd0;
dma_rdata_d <= 'd0;
dma_raddr <= 'd0;
end else begin
dma_rd <= dma_rd_s;
dma_rd_d <= dma_rd;
dma_rdata_d <= dma_rdata_s;
if (dma_rd_s == 1'b1) begin
dma_raddr <= dma_raddr + 1'b1;
end
end
end
// instantiations
ad_mem_asym #(
.ADDR_WIDTH_A (ADC_ADDR_WIDTH),
.DATA_WIDTH_A (ADC_DATA_WIDTH),
.ADDR_WIDTH_B (DMA_ADDR_WIDTH),
.DATA_WIDTH_B (DMA_DATA_WIDTH))
i_mem_asym (
.clka (adc_clk),
.wea (adc_wr_int),
.addra (adc_waddr_int),
.dina (adc_wdata_int),
.clkb (dma_clk),
.addrb (dma_raddr),
.doutb (dma_rdata_s));
ad_axis_inf_rx #(.DATA_WIDTH(DMA_DATA_WIDTH)) i_axis_inf (
.clk (dma_clk),
.rst (dma_rst),
.valid (dma_rd_d),
.last (1'd0),
.data (dma_rdata_d),
.inf_valid (dma_wr),
.inf_last (),
.inf_data (dma_wdata),
.inf_ready (dma_wready));
endmodule
// ***************************************************************************
// ***************************************************************************

6
library/axi_fifo2f/axi_fifo2f_constr.xdc Normal file
View File

@ -0,0 +1,6 @@
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports adc_clk]]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports dma_clk]]

19
library/axi_fifo2f/axi_fifo2f_ip.tcl Normal file
View File

@ -0,0 +1,19 @@
# ip
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_fifo2f
adi_ip_files axi_fifo2f [list \
"$ad_hdl_dir/library/common/ad_axis_inf_rx.v" \
"$ad_hdl_dir/library/common/ad_mem_asym.v" \
"axi_fifo2f.v" \
"axi_fifo2f_constr.xdc" ]
adi_ip_properties_lite axi_fifo2f
adi_ip_constraints axi_fifo2f [list \
"axi_fifo2f_constr.xdc" ]
ipx::save_core [ipx::current_core]

189
library/axi_fifo2s/axi_fifo2s.v
View File

@ -43,17 +43,20 @@ module axi_fifo2s (
// fifo interface
m_rst,
m_clk,
m_wr,
m_wdata,
m_wovf,
adc_rst,
adc_clk,
adc_wr,
adc_wdata,
adc_wovf,
axi_mrstn,
axi_mwr,
axi_mwdata,
axi_mwovf,
axi_mwpfull,
// dma interface
dma_clk,
dma_wr,
dma_wdata,
dma_wready,
dma_xfer_req,
dma_xfer_status,
// axi interface
@ -100,34 +103,36 @@ module axi_fifo2s (
axi_rresp,
axi_rlast,
axi_rdata,
axi_rready,
// transfer request
axi_xfer_req,
axi_xfer_status);
axi_rready);
// parameters
parameter DATA_WIDTH = 32;
parameter ADC_DATA_WIDTH = 128;
parameter DMA_DATA_WIDTH = 64;
parameter AXI_DATA_WIDTH = 512;
parameter DMA_READY_ENABLE = 1;
parameter AXI_SIZE = 2;
parameter AXI_LENGTH = 16;
parameter AXI_ADDRESS = 32'h00000000;
parameter AXI_ADDRLIMIT = 32'h00000000;
parameter AXI_ADDRLIMIT = 32'hffffffff;
parameter AXI_BYTE_WIDTH = AXI_DATA_WIDTH/8;
// fifo interface
// adc interface
input m_rst;
input m_clk;
input m_wr;
input [DATA_WIDTH-1:0] m_wdata;
output m_wovf;
input adc_rst;
input adc_clk;
input adc_wr;
input [ADC_DATA_WIDTH-1:0] adc_wdata;
output adc_wovf;
output axi_mrstn;
output axi_mwr;
output [DATA_WIDTH-1:0] axi_mwdata;
input axi_mwovf;
input axi_mwpfull;
// dma interface
input dma_clk;
output dma_wr;
output [DMA_DATA_WIDTH-1:0] dma_wdata;
input dma_wready;
input dma_xfer_req;
output [ 3:0] dma_xfer_status;
// axi interface
@ -146,8 +151,8 @@ module axi_fifo2s (
output [ 31:0] axi_awaddr;
input axi_awready;
output axi_wvalid;
output [DATA_WIDTH-1:0] axi_wdata;
output [(DATA_WIDTH/8)-1:0] axi_wstrb;
output [AXI_DATA_WIDTH-1:0] axi_wdata;
output [AXI_BYTE_WIDTH-1:0] axi_wstrb;
output axi_wlast;
output [ 3:0] axi_wuser;
input axi_wready;
@ -173,78 +178,52 @@ module axi_fifo2s (
input [ 3:0] axi_ruser;
input [ 1:0] axi_rresp;
input axi_rlast;
input [DATA_WIDTH-1:0] axi_rdata;
input [AXI_DATA_WIDTH-1:0] axi_rdata;
output axi_rready;
// transfer request & status
input axi_xfer_req;
output [ 4:0] axi_xfer_status;
// internal registers
reg [ 4:0] axi_xfer_status = 'd0;
reg [ 4:0] axi_status_cnt = 'd0;
reg m_wovf_m = 'd0;
reg m_wovf = 'd0;
// internal signals
wire adc_dwr_s;
wire [AXI_DATA_WIDTH-1:0] adc_ddata_s;
wire axi_rd_req_s;
wire [ 31:0] axi_rd_addr_s;
wire axi_dwovf_s;
wire axi_dwunf_s;
wire axi_werror_s;
wire axi_rerror_s;
// status signals
always @(posedge axi_clk) begin
if (axi_resetn == 1'b0) begin
axi_xfer_status <= 'd0;
axi_status_cnt <= 'd0;
end else begin
axi_xfer_status[4] <= axi_rerror_s;
axi_xfer_status[3] <= axi_werror_s;
axi_xfer_status[2] <= axi_dwunf_s;
axi_xfer_status[1] <= axi_dwovf_s;
axi_xfer_status[0] <= axi_mwovf;
if (axi_xfer_status == 0) begin
if (axi_status_cnt[4] == 1'b1) begin
axi_status_cnt <= axi_status_cnt + 1'b1;
end
end else begin
axi_status_cnt <= 5'd10;
end
end
end
always @(posedge m_clk) begin
if (m_rst == 1'b1) begin
m_wovf_m <= 'd0;
m_wovf <= 'd0;
end else begin
m_wovf_m <= axi_status_cnt[4];
m_wovf <= m_wovf_m;
end
end
wire [ 3:0] axi_xfer_status_s;
wire axi_drst_s;
wire axi_dvalid_s;
wire [AXI_DATA_WIDTH-1:0] axi_ddata_s;
wire axi_dready_s;
// instantiations
axi_fifo2s_adc #(
.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
.ADC_DATA_WIDTH (ADC_DATA_WIDTH))
i_adc_if (
.adc_rst (adc_rst),
.adc_clk (adc_clk),
.adc_wr (adc_wr),
.adc_wdata (adc_wdata),
.adc_wovf (adc_wovf),
.adc_dwr (adc_dwr_s),
.adc_ddata (adc_ddata_s),
.axi_drst (axi_drst_s),
.axi_clk (axi_clk),
.axi_xfer_status (axi_xfer_status_s));
axi_fifo2s_wr #(
.DATA_WIDTH (DATA_WIDTH),
.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
.AXI_SIZE (AXI_SIZE),
.AXI_LENGTH (AXI_LENGTH),
.AXI_ADDRESS (AXI_ADDRESS),
.AXI_ADDRLIMIT (AXI_ADDRLIMIT))
i_wr (
.axi_xfer_req (axi_xfer_req),
.dma_xfer_req (dma_xfer_req),
.axi_rd_req (axi_rd_req_s),
.axi_rd_addr (axi_rd_addr_s),
.m_rst (m_rst),
.m_clk (m_clk),
.m_wr (m_wr),
.m_wdata (m_wdata),
.adc_rst (adc_rst),
.adc_clk (adc_clk),
.adc_wr (adc_dwr_s),
.adc_wdata (adc_ddata_s),
.axi_clk (axi_clk),
.axi_resetn (axi_resetn),
.axi_awvalid (axi_awvalid),
@ -270,18 +249,18 @@ module axi_fifo2s (
.axi_bresp (axi_bresp),
.axi_buser (axi_buser),
.axi_bready (axi_bready),
.axi_dwovf (axi_dwovf_s),
.axi_dwunf (axi_dwunf_s),
.axi_werror (axi_werror_s));
.axi_dwovf (axi_xfer_status_s[0]),
.axi_dwunf (axi_xfer_status_s[1]),
.axi_werror (axi_xfer_status_s[2]));
axi_fifo2s_rd #(
.DATA_WIDTH (DATA_WIDTH),
.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
.AXI_SIZE (AXI_SIZE),
.AXI_LENGTH (AXI_LENGTH),
.AXI_ADDRESS (AXI_ADDRESS),
.AXI_ADDRLIMIT (AXI_ADDRLIMIT))
i_rd (
.axi_xfer_req (axi_xfer_req),
.dma_xfer_req (dma_xfer_req),
.axi_rd_req (axi_rd_req_s),
.axi_rd_addr (axi_rd_addr_s),
.axi_clk (axi_clk),
@ -305,11 +284,29 @@ module axi_fifo2s (
.axi_rlast (axi_rlast),
.axi_rdata (axi_rdata),
.axi_rready (axi_rready),
.axi_rerror (axi_rerror_s),
.axi_mrstn (axi_mrstn),
.axi_mwr (axi_mwr),
.axi_mwdata (axi_mwdata),
.axi_mwpfull (axi_mwpfull));
.axi_rerror (axi_xfer_status_s[3]),
.axi_drst (axi_drst_s),
.axi_dvalid (axi_dvalid_s),
.axi_ddata (axi_ddata_s),
.axi_dready (axi_dready_s));
axi_fifo2s_dma #(
.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
.DMA_DATA_WIDTH (DMA_DATA_WIDTH),
.DMA_READY_ENABLE (DMA_READY_ENABLE))
i_dma_if (
.axi_clk (axi_clk),
.axi_drst (axi_drst_s),
.axi_dvalid (axi_dvalid_s),
.axi_ddata (axi_ddata_s),
.axi_dready (axi_dready_s),
.axi_xfer_status (axi_xfer_status_s),
.dma_clk (dma_clk),
.dma_wr (dma_wr),
.dma_wdata (dma_wdata),
.dma_wready (dma_wready),
.dma_xfer_req (dma_xfer_req),
.dma_xfer_status (dma_xfer_status));
endmodule

148
library/axi_fifo2s/axi_fifo2s_adc.v Normal file
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@ -0,0 +1,148 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_fifo2s_adc (
// fifo interface
adc_rst,
adc_clk,
adc_wr,
adc_wdata,
adc_wovf,
adc_dwr,
adc_ddata,
// axi interface
axi_drst,
axi_clk,
axi_xfer_status);
// parameters
parameter ADC_DATA_WIDTH = 128;
parameter AXI_DATA_WIDTH = 512;
localparam ADC_MEM_RATIO = AXI_DATA_WIDTH/ADC_DATA_WIDTH;
// adc interface
input adc_rst;
input adc_clk;
input adc_wr;
input [ADC_DATA_WIDTH-1:0] adc_wdata;
output adc_wovf;
output adc_dwr;
output [AXI_DATA_WIDTH-1:0] adc_ddata;
// axi interface
input axi_clk;
input axi_drst;
input [ 3:0] axi_xfer_status;
// internal registers
reg adc_wovf = 'd0;
reg [ 2:0] adc_wcnt_int = 'd0;
reg adc_dwr = 'd0;
reg [AXI_DATA_WIDTH-1:0] adc_ddata = 'd0;
// internal signals
wire [ 3:0] adc_xfer_status_s;
// write interface: supports only 64, 128, 256 and 512 against 512
always @(posedge adc_clk) begin
if (adc_rst == 1'b1) begin
adc_wovf <= 'd0;
adc_wcnt_int <= 'd0;
adc_dwr <= 'd0;
adc_ddata <= 'd0;
end else begin
adc_wovf <= | adc_xfer_status_s;
adc_wcnt_int <= adc_wcnt_int + 1'b1;
case (ADC_MEM_RATIO)
8: begin
adc_dwr <= adc_wr & adc_wcnt_int[0] & adc_wcnt_int[1] & adc_wcnt_int[2];
adc_ddata[((ADC_DATA_WIDTH*8)-1):(ADC_DATA_WIDTH*7)] <= adc_wdata;
adc_ddata[((ADC_DATA_WIDTH*7)-1):(ADC_DATA_WIDTH*0)] <=
adc_ddata[((ADC_DATA_WIDTH*8)-1):(ADC_DATA_WIDTH*1)];
end
4: begin
adc_dwr <= adc_wr & adc_wcnt_int[0] & adc_wcnt_int[1];
adc_ddata[((ADC_DATA_WIDTH*4)-1):(ADC_DATA_WIDTH*3)] <= adc_wdata;
adc_ddata[((ADC_DATA_WIDTH*3)-1):(ADC_DATA_WIDTH*0)] <=
adc_ddata[((ADC_DATA_WIDTH*4)-1):(ADC_DATA_WIDTH*1)];
end
2: begin
adc_dwr <= adc_wr & adc_wcnt_int[0];
adc_ddata[((ADC_DATA_WIDTH*2)-1):(ADC_DATA_WIDTH*1)] <= adc_wdata;
adc_ddata[((ADC_DATA_WIDTH*1)-1):(ADC_DATA_WIDTH*0)] <=
adc_ddata[((ADC_DATA_WIDTH*2)-1):(ADC_DATA_WIDTH*1)];
end
1: begin
adc_dwr <= adc_wr;
adc_ddata <= adc_wdata;
end
default: begin
adc_dwr <= 'd0;
adc_ddata <= 'd0;
end
endcase
end
end
// instantiations
up_xfer_status #(.DATA_WIDTH(4)) i_xfer_status (
.up_rstn (~adc_rst),
.up_clk (adc_clk),
.up_data_status (adc_xfer_status_s),
.d_rst (axi_drst),
.d_clk (axi_clk),
.d_data_status (axi_xfer_status));
endmodule
// ***************************************************************************
// ***************************************************************************

13
library/axi_fifo2s/axi_fifo2s_constr.xdc Normal file
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@ -0,0 +1,13 @@
set_false_path -from [get_cells *dma_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
-to [get_cells *axi_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
set_false_path -from [get_cells *axi_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
-to [get_cells *dma_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
set_false_path -from [get_cells *adc_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
-to [get_cells *axi_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
set_false_path -from [get_cells *axi_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
-to [get_cells *adc_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]

249
library/axi_fifo2s/axi_fifo2s_dma.v Normal file
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@ -0,0 +1,249 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_fifo2s_dma (
axi_clk,
axi_drst,
axi_dvalid,
axi_ddata,
axi_dready,
axi_xfer_status,
dma_clk,
dma_wr,
dma_wdata,
dma_wready,
dma_xfer_req,
dma_xfer_status);
// parameters
parameter AXI_DATA_WIDTH = 512;
parameter DMA_DATA_WIDTH = 64;
parameter DMA_READY_ENABLE = 1;
localparam DMA_MEM_RATIO = AXI_DATA_WIDTH/DMA_DATA_WIDTH;
localparam DMA_ADDR_WIDTH = 8;
localparam AXI_ADDR_WIDTH = (DMA_MEM_RATIO == 2) ? (DMA_ADDR_WIDTH - 1) :
((DMA_MEM_RATIO == 4) ? (DMA_ADDR_WIDTH - 2) : (DMA_ADDR_WIDTH - 3));
// adc write
input axi_clk;
input axi_drst;
input axi_dvalid;
input [AXI_DATA_WIDTH-1:0] axi_ddata;
output axi_dready;
input [ 3:0] axi_xfer_status;
// dma read
input dma_clk;
output dma_wr;
output [DMA_DATA_WIDTH-1:0] dma_wdata;
input dma_wready;
input dma_xfer_req;
output [ 3:0] dma_xfer_status;
// internal registers
reg [AXI_ADDR_WIDTH-1:0] axi_waddr = 'd0;
reg [ 2:0] axi_waddr_rel_count = 'd0;
reg axi_waddr_rel_t = 'd0;
reg [AXI_ADDR_WIDTH-1:0] axi_waddr_rel = 'd0;
reg [ 2:0] axi_raddr_rel_t_m = 'd0;
reg [DMA_ADDR_WIDTH-1:0] axi_raddr_rel = 'd0;
reg [DMA_ADDR_WIDTH-1:0] axi_addr_diff = 'd0;
reg axi_dready = 'd0;
reg dma_rst = 'd0;
reg [ 2:0] dma_waddr_rel_t_m = 'd0;
reg [AXI_ADDR_WIDTH-1:0] dma_waddr_rel = 'd0;
reg dma_rd = 'd0;
reg dma_rd_d = 'd0;
reg [DMA_DATA_WIDTH-1:0] dma_rdata_d = 'd0;
reg [DMA_ADDR_WIDTH-1:0] dma_raddr = 'd0;
reg [ 2:0] dma_raddr_rel_count = 'd0;
reg dma_raddr_rel_t = 'd0;
reg [DMA_ADDR_WIDTH-1:0] dma_raddr_rel = 'd0;
// internal signals
wire [DMA_ADDR_WIDTH:0] axi_addr_diff_s;
wire axi_raddr_rel_t_s;
wire [DMA_ADDR_WIDTH-1:0] axi_waddr_s;
wire dma_waddr_rel_t_s;
wire [DMA_ADDR_WIDTH-1:0] dma_waddr_rel_s;
wire dma_wready_s;
wire dma_rd_s;
wire [DMA_DATA_WIDTH-1:0] dma_rdata_s;
// write interface
always @(posedge axi_clk) begin
if (axi_drst == 1'b1) begin
axi_waddr <= 'd0;
axi_waddr_rel_count <= 'd0;
axi_waddr_rel_t <= 'd0;
axi_waddr_rel <= 'd0;
end else begin
if (axi_dvalid == 1'b1) begin
axi_waddr <= axi_waddr + 1'b1;
end
axi_waddr_rel_count <= axi_waddr_rel_count + 1'b1;
if (axi_waddr_rel_count == 3'd7) begin
axi_waddr_rel_t <= ~axi_waddr_rel_t;
axi_waddr_rel <= axi_waddr;
end
end
end
assign axi_addr_diff_s = {1'b1, axi_waddr_s} - axi_raddr_rel;
assign axi_raddr_rel_t_s = axi_raddr_rel_t_m[2] ^ axi_raddr_rel_t_m[1];
assign axi_waddr_s = (DMA_MEM_RATIO == 2) ? {axi_waddr, 1'd0} :
((DMA_MEM_RATIO == 4) ? {axi_waddr, 2'd0} : {axi_waddr, 3'd0});
always @(posedge axi_clk) begin
if (axi_drst == 1'b1) begin
axi_raddr_rel_t_m <= 'd0;
axi_raddr_rel <= 'd0;
axi_addr_diff <= 'd0;
axi_dready <= 'd0;
end else begin
axi_raddr_rel_t_m <= {axi_raddr_rel_t_m[1:0], dma_raddr_rel_t};
if (axi_raddr_rel_t_s == 1'b1) begin
axi_raddr_rel <= dma_raddr_rel;
end
axi_addr_diff <= axi_addr_diff_s[DMA_ADDR_WIDTH-1:0];
if (axi_addr_diff >= 180) begin
axi_dready <= 1'b0;
end else if (axi_addr_diff <= 8) begin
axi_dready <= 1'b1;
end
end
end
// read interface
assign dma_waddr_rel_t_s = dma_waddr_rel_t_m[2] ^ dma_waddr_rel_t_m[1];
assign dma_waddr_rel_s = (DMA_MEM_RATIO == 2) ? {dma_waddr_rel, 1'd0} :
((DMA_MEM_RATIO == 4) ? {dma_waddr_rel, 2'd0} : {dma_waddr_rel, 3'd0});
always @(posedge dma_clk) begin
if (dma_xfer_req == 1'b0) begin
dma_rst <= 1'b1;
dma_waddr_rel_t_m <= 'd0;
dma_waddr_rel <= 'd0;
end else begin
dma_rst <= 1'b0;
dma_waddr_rel_t_m <= {dma_waddr_rel_t_m[1:0], axi_waddr_rel_t};
if (dma_waddr_rel_t_s == 1'b1) begin
dma_waddr_rel <= axi_waddr_rel;
end
end
end
assign dma_wready_s = (DMA_READY_ENABLE == 0) ? 1'b1 : dma_wready;
assign dma_rd_s = (dma_raddr == dma_waddr_rel_s) ? 1'b0 : dma_wready_s;
always @(posedge dma_clk) begin
if (dma_xfer_req == 1'b0) begin
dma_rd <= 'd0;
dma_rd_d <= 'd0;
dma_rdata_d <= 'd0;
dma_raddr <= 'd0;
dma_raddr_rel_count <= 'd0;
dma_raddr_rel_t <= 'd0;
dma_raddr_rel <= 'd0;
end else begin
dma_rd <= dma_rd_s;
dma_rd_d <= dma_rd;
dma_rdata_d <= dma_rdata_s;
if (dma_rd_s == 1'b1) begin
dma_raddr <= dma_raddr + 1'b1;
end
dma_raddr_rel_count <= dma_raddr_rel_count + 1'b1;
if (dma_raddr_rel_count == 3'd7) begin
dma_raddr_rel_t <= ~dma_raddr_rel_t;
dma_raddr_rel <= dma_raddr;
end
end
end
// instantiations
ad_mem_asym #(
.ADDR_WIDTH_A (AXI_ADDR_WIDTH),
.DATA_WIDTH_A (AXI_DATA_WIDTH),
.ADDR_WIDTH_B (DMA_ADDR_WIDTH),
.DATA_WIDTH_B (DMA_DATA_WIDTH))
i_mem_asym (
.clka (axi_clk),
.wea (axi_dvalid),
.addra (axi_waddr),
.dina (axi_ddata),
.clkb (dma_clk),
.addrb (dma_raddr),
.doutb (dma_rdata_s));
ad_axis_inf_rx #(.DATA_WIDTH(DMA_DATA_WIDTH)) i_axis_inf (
.clk (dma_clk),
.rst (dma_rst),
.valid (dma_rd_d),
.last (1'd0),
.data (dma_rdata_d),
.inf_valid (dma_wr),
.inf_last (),
.inf_data (dma_wdata),
.inf_ready (dma_wready));
up_xfer_status #(.DATA_WIDTH(4)) i_xfer_status (
.up_rstn (~dma_rst),
.up_clk (dma_clk),
.up_data_status (dma_xfer_status),
.d_rst (axi_drst),
.d_clk (axi_clk),
.d_data_status (axi_xfer_status));
endmodule
// ***************************************************************************
// ***************************************************************************

12
library/axi_fifo2s/axi_fifo2s_ip.tcl
View File

@ -6,17 +6,21 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_fifo2s
adi_ip_files axi_fifo2s [list \
"$ad_hdl_dir/library/common/ad_mem.v" \
"$ad_hdl_dir/library/common/ad_mem_asym.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/ad_axis_inf_rx.v" \
"axi_fifo2s_adc.v" \
"axi_fifo2s_dma.v" \
"axi_fifo2s_wr.v" \
"axi_fifo2s_rd.v" \
"axi_fifo2s.v" ]
"axi_fifo2s.v" \
"axi_fifo2s_constr.xdc" ]
adi_ip_properties_lite axi_fifo2s
adi_ip_constraints axi_fifo2s [list \
"axi_fifo2s_constr.xdc" ]
ipx::infer_bus_interfaces {{xilinx.com:interface:aximm:1.0}} [ipx::current_core]
ipx::remove_bus_interface {m} [ipx::current_core]
ipx::remove_bus_interface {m_signal_clock} [ipx::current_core]
ipx::remove_memory_map {m} [ipx::current_core]
ipx::save_core [ipx::current_core]

55
library/axi_fifo2s/axi_fifo2s_rd.v
View File

@ -43,7 +43,10 @@ module axi_fifo2s_rd (
// request and synchronization
axi_xfer_req,
dma_xfer_req,
// read interface
axi_rd_req,
axi_rd_addr,
@ -77,25 +80,29 @@ module axi_fifo2s_rd (
// fifo interface
axi_mrstn,
axi_mwr,
axi_mwdata,
axi_mwpfull);
axi_drst,
axi_dvalid,
axi_ddata,
axi_dready);
// parameters
parameter DATA_WIDTH = 32;
parameter AXI_DATA_WIDTH = 512;
parameter AXI_SIZE = 2;
parameter AXI_LENGTH = 16;
parameter AXI_ADDRESS = 32'h00000000;
parameter AXI_ADDRLIMIT = 32'h00000000;
localparam AXI_AWINCR = (AXI_LENGTH * DATA_WIDTH)/8;
localparam AXI_BYTE_WIDTH = AXI_DATA_WIDTH/8;
localparam AXI_AWINCR = AXI_LENGTH * AXI_BYTE_WIDTH;
localparam BUF_THRESHOLD_LO = 6'd3;
localparam BUF_THRESHOLD_HI = 6'd60;
// request and synchronization
input axi_xfer_req;
input dma_xfer_req;
// read interface
input axi_rd_req;
input [ 31:0] axi_rd_addr;
@ -120,7 +127,7 @@ module axi_fifo2s_rd (
input [ 3:0] axi_ruser;
input [ 1:0] axi_rresp;
input axi_rlast;
input [DATA_WIDTH-1:0] axi_rdata;
input [AXI_DATA_WIDTH-1:0] axi_rdata;
output axi_rready;
// axi status
@ -129,10 +136,10 @@ module axi_fifo2s_rd (
// fifo interface
output axi_mrstn;
output axi_mwr;
output [DATA_WIDTH-1:0] axi_mwdata;
input axi_mwpfull;
output axi_drst;
output axi_dvalid;
output [AXI_DATA_WIDTH-1:0] axi_ddata;
input axi_dready;
// internal registers
@ -144,9 +151,9 @@ module axi_fifo2s_rd (
reg axi_xfer_enable = 'd0;
reg axi_arvalid = 'd0;
reg [ 31:0] axi_araddr = 'd0;
reg axi_mrstn = 'd0;
reg axi_mwr = 'd0;
reg [DATA_WIDTH-1:0] axi_mwdata = 'd0;
reg axi_drst = 'd0;
reg axi_dvalid = 'd0;
reg [AXI_DATA_WIDTH-1:0] axi_ddata = 'd0;
reg axi_rready = 'd0;
reg axi_rerror = 'd0;
@ -156,7 +163,7 @@ module axi_fifo2s_rd (
// read is way too slow- buffer mode
assign axi_ready_s = (~axi_arvalid | axi_arready) & ~axi_mwpfull;
assign axi_ready_s = (~axi_arvalid | axi_arready) & axi_dready;
always @(posedge axi_clk or negedge axi_resetn) begin
if (axi_resetn == 1'b0) begin
@ -181,7 +188,7 @@ module axi_fifo2s_rd (
axi_rd <= axi_xfer_enable;
axi_rd_active <= axi_xfer_enable;
end
axi_xfer_req_m <= {axi_xfer_req_m[1:0], axi_xfer_req};
axi_xfer_req_m <= {axi_xfer_req_m[1:0], dma_xfer_req};
axi_xfer_init <= axi_xfer_req_m[1] & ~axi_xfer_req_m[2];
axi_xfer_enable <= axi_xfer_req_m[2];
end
@ -225,14 +232,14 @@ module axi_fifo2s_rd (
always @(posedge axi_clk or negedge axi_resetn) begin
if (axi_resetn == 1'b0) begin
axi_mrstn <= 'd0;
axi_mwr <= 'd0;
axi_mwdata <= 'd0;
axi_drst <= 'd1;
axi_dvalid <= 'd0;
axi_ddata <= 'd0;
axi_rready <= 'd0;
end else begin
axi_mrstn <= axi_xfer_enable;
axi_mwr <= axi_rvalid & axi_rready;
axi_mwdata <= axi_rdata;
axi_drst <= ~axi_xfer_req_m[1];
axi_dvalid <= axi_rvalid & axi_rready;
axi_ddata <= axi_rdata;
axi_rready <= 1'b1;
end
end

148
library/axi_fifo2s/axi_fifo2s_wr.v
View File

@ -43,16 +43,19 @@ module axi_fifo2s_wr (
// request and synchronization
axi_xfer_req,
dma_xfer_req,
// read interface
axi_rd_req,
axi_rd_addr,
// fifo interface
m_rst,
m_clk,
m_wr,
m_wdata,
adc_rst,
adc_clk,
adc_wr,
adc_wdata,
// axi interface
@ -82,7 +85,6 @@ module axi_fifo2s_wr (
axi_buser,
axi_bready,
// axi status
axi_dwovf,
@ -91,27 +93,31 @@ module axi_fifo2s_wr (
// parameters
parameter DATA_WIDTH = 32;
parameter AXI_DATA_WIDTH = 512;
parameter AXI_SIZE = 2;
parameter AXI_LENGTH = 16;
parameter AXI_ADDRESS = 32'h00000000;
parameter AXI_ADDRLIMIT = 32'h00000000;
localparam AXI_AWINCR = (AXI_LENGTH * DATA_WIDTH)/8;
localparam AXI_BYTE_WIDTH = AXI_DATA_WIDTH/8;
localparam AXI_AWINCR = AXI_LENGTH * AXI_BYTE_WIDTH;
localparam BUF_THRESHOLD_LO = 8'd6;
localparam BUF_THRESHOLD_HI = 8'd250;
// request and synchronization
input axi_xfer_req;
input dma_xfer_req;
// read interface
output axi_rd_req;
output [ 31:0] axi_rd_addr;
// fifo interface
input m_rst;
input m_clk;
input m_wr;
input [DATA_WIDTH-1:0] m_wdata;
input adc_rst;
input adc_clk;
input adc_wr;
input [AXI_DATA_WIDTH-1:0] adc_wdata;
// axi interface
@ -130,8 +136,8 @@ module axi_fifo2s_wr (
output [ 31:0] axi_awaddr;
input axi_awready;
output axi_wvalid;
output [DATA_WIDTH-1:0] axi_wdata;
output [(DATA_WIDTH/8)-1:0] axi_wstrb;
output [AXI_DATA_WIDTH-1:0] axi_wdata;
output [AXI_BYTE_WIDTH-1:0] axi_wstrb;
output axi_wlast;
output [ 3:0] axi_wuser;
input axi_wready;
@ -149,16 +155,16 @@ module axi_fifo2s_wr (
// internal registers
reg [ 2:0] m_xfer_req_m = 'd0;
reg m_xfer_init = 'd0;
reg m_xfer_limit = 'd0;
reg m_xfer_enable = 'd0;
reg [ 31:0] m_xfer_addr = 'd0;
reg [ 7:0] m_waddr = 'd0;
reg [ 7:0] m_waddr_g = 'd0;
reg m_rel_enable = 'd0;
reg m_rel_toggle = 'd0;
reg [ 7:0] m_rel_waddr = 'd0;
reg [ 2:0] adc_xfer_req_m = 'd0;
reg adc_xfer_init = 'd0;
reg adc_xfer_limit = 'd0;
reg adc_xfer_enable = 'd0;
reg [ 31:0] adc_xfer_addr = 'd0;
reg [ 7:0] adc_waddr = 'd0;
reg [ 7:0] adc_waddr_g = 'd0;
reg adc_rel_enable = 'd0;
reg adc_rel_toggle = 'd0;
reg [ 7:0] adc_rel_waddr = 'd0;
reg [ 2:0] axi_rel_toggle_m = 'd0;
reg [ 7:0] axi_rel_waddr = 'd0;
reg [ 7:0] axi_waddr_m1 = 'd0;
@ -176,7 +182,7 @@ module axi_fifo2s_wr (
reg axi_rlast = 'd0;
reg axi_rd_d = 'd0;
reg axi_rlast_d = 'd0;
reg [DATA_WIDTH-1:0] axi_rdata_d = 'd0;
reg [AXI_DATA_WIDTH-1:0] axi_rdata_d = 'd0;
reg axi_rd_req = 'd0;
reg [ 31:0] axi_rd_addr = 'd0;
reg axi_awvalid = 'd0;
@ -192,7 +198,7 @@ module axi_fifo2s_wr (
wire axi_rd_s;
wire axi_req_s;
wire axi_rlast_s;
wire [DATA_WIDTH-1:0] axi_rdata_s;
wire [AXI_DATA_WIDTH-1:0] axi_rdata_s;
// binary to grey conversion
@ -232,45 +238,45 @@ module axi_fifo2s_wr (
// fifo interface
always @(posedge m_clk) begin
if (m_rst == 1'b1) begin
m_waddr <= 'd0;
m_waddr_g <= 'd0;
m_xfer_req_m <= 'd0;
m_xfer_init <= 'd0;
m_xfer_limit <= 'd0;
m_xfer_enable <= 'd0;
m_xfer_addr <= 'd0;
m_rel_enable <= 'd0;
m_rel_toggle <= 'd0;
m_rel_waddr <= 'd0;
always @(posedge adc_clk) begin
if (adc_rst == 1'b1) begin
adc_waddr <= 'd0;
adc_waddr_g <= 'd0;
adc_xfer_req_m <= 'd0;
adc_xfer_init <= 'd0;
adc_xfer_limit <= 'd0;
adc_xfer_enable <= 'd0;
adc_xfer_addr <= 'd0;
adc_rel_enable <= 'd0;
adc_rel_toggle <= 'd0;
adc_rel_waddr <= 'd0;
end else begin
if ((m_wr == 1'b1) && (m_xfer_enable == 1'b1)) begin
m_waddr <= m_waddr + 1'b1;
if ((adc_wr == 1'b1) && (adc_xfer_enable == 1'b1)) begin
adc_waddr <= adc_waddr + 1'b1;
end
m_waddr_g <= b2g(m_waddr);
m_xfer_req_m <= {m_xfer_req_m[1:0], axi_xfer_req};
m_xfer_init <= m_xfer_req_m[1] & ~m_xfer_req_m[2];
if (m_xfer_init == 1'b1) begin
m_xfer_limit <= 1'd1;
end else if ((m_xfer_addr >= AXI_ADDRLIMIT) || (m_xfer_enable == 1'b0)) begin
m_xfer_limit <= 1'd0;
adc_waddr_g <= b2g(adc_waddr);
adc_xfer_req_m <= {adc_xfer_req_m[1:0], dma_xfer_req};
adc_xfer_init <= adc_xfer_req_m[1] & ~adc_xfer_req_m[2];
if (adc_xfer_init == 1'b1) begin
adc_xfer_limit <= 1'd1;
end else if ((adc_xfer_addr >= AXI_ADDRLIMIT) || (adc_xfer_enable == 1'b0)) begin
adc_xfer_limit <= 1'd0;
end
if (m_xfer_init == 1'b1) begin
m_xfer_enable <= 1'b1;
m_xfer_addr <= AXI_ADDRESS;
end else if ((m_waddr[1:0] == 2'h3) && (m_wr == 1'b1)) begin
m_xfer_enable <= m_xfer_req_m[2] & m_xfer_limit;
m_xfer_addr <= m_xfer_addr + AXI_AWINCR;
if (adc_xfer_init == 1'b1) begin
adc_xfer_enable <= 1'b1;
adc_xfer_addr <= AXI_ADDRESS;
end else if ((adc_waddr[1:0] == 2'h3) && (adc_wr == 1'b1)) begin
adc_xfer_enable <= adc_xfer_req_m[2] & adc_xfer_limit;
adc_xfer_addr <= adc_xfer_addr + AXI_AWINCR;
end
if (m_waddr[1:0] == 2'h3) begin
m_rel_enable <= m_wr;
if (adc_waddr[1:0] == 2'h3) begin
adc_rel_enable <= adc_wr;
end else begin
m_rel_enable <= 1'd0;
adc_rel_enable <= 1'd0;
end
if (m_rel_enable == 1'b1) begin
m_rel_toggle <= ~m_rel_toggle;
m_rel_waddr <= m_waddr;
if (adc_rel_enable == 1'b1) begin
adc_rel_toggle <= ~adc_rel_toggle;
adc_rel_waddr <= adc_waddr;
end
end
end
@ -287,11 +293,11 @@ module axi_fifo2s_wr (
axi_waddr_m2 <= 'd0;
axi_waddr <= 'd0;
end else begin
axi_rel_toggle_m <= {axi_rel_toggle_m[1:0], m_rel_toggle};
axi_rel_toggle_m <= {axi_rel_toggle_m[1:0], adc_rel_toggle};
if (axi_rel_toggle_s == 1'b1) begin
axi_rel_waddr <= m_rel_waddr;
axi_rel_waddr <= adc_rel_waddr;
end
axi_waddr_m1 <= m_waddr_g;
axi_waddr_m1 <= adc_waddr_g;
axi_waddr_m2 <= axi_waddr_m1;
axi_waddr <= g2b(axi_waddr_m2);
end
@ -334,7 +340,7 @@ module axi_fifo2s_wr (
axi_xfer_req_m <= 'd0;
axi_xfer_init <= 'd0;
end else begin
axi_xfer_req_m <= {axi_xfer_req_m[1:0], axi_xfer_req};
axi_xfer_req_m <= {axi_xfer_req_m[1:0], dma_xfer_req};
axi_xfer_init <= axi_xfer_req_m[1] & ~axi_xfer_req_m[2];
end
end
@ -418,7 +424,7 @@ module axi_fifo2s_wr (
// write channel
assign axi_wstrb = {(DATA_WIDTH/8){1'b1}};
assign axi_wstrb = {AXI_BYTE_WIDTH{1'b1}};
assign axi_wuser = 4'b0000;
// response channel
@ -445,7 +451,7 @@ module axi_fifo2s_wr (
// interface handler
ad_axis_inf_rx #(.DATA_WIDTH(DATA_WIDTH)) i_axis_inf (
ad_axis_inf_rx #(.DATA_WIDTH(AXI_DATA_WIDTH)) i_axis_inf (
.clk (axi_clk),
.rst (axi_reset),
.valid (axi_rd_d),
@ -458,11 +464,11 @@ module axi_fifo2s_wr (
// buffer
ad_mem #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(8)) i_mem (
.clka (m_clk),
.wea (m_wr),
.addra (m_waddr),
.dina (m_wdata),
ad_mem #(.DATA_WIDTH(AXI_DATA_WIDTH), .ADDR_WIDTH(8)) i_mem (
.clka (adc_clk),
.wea (adc_wr),
.addra (adc_waddr),
.dina (adc_wdata),
.clkb (axi_clk),
.addrb (axi_raddr),
.doutb (axi_rdata_s));

30
library/axi_hdmi_tx/axi_hdmi_tx.v
View File

@ -181,12 +181,14 @@ module axi_hdmi_tx (
// internal signals
wire up_sel_s;
wire up_wr_s;
wire [13:0] up_addr_s;
wire up_wreq_s;
wire [13:0] up_waddr_s;
wire [31:0] up_wdata_s;
wire up_wack_s;
wire up_rreq_s;
wire [13:0] up_raddr_s;
wire [31:0] up_rdata_s;
wire up_ack_s;
wire up_rack_s;
wire hdmi_full_range_s;
wire hdmi_csc_bypass_s;
wire [ 1:0] hdmi_srcsel_s;
@ -252,12 +254,14 @@ module axi_hdmi_tx (
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_ack (up_ack_s));
.up_rack (up_rack_s));
// processor interface
@ -288,12 +292,14 @@ module axi_hdmi_tx (
.vdma_tpm_oos (vdma_tpm_oos_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_ack (up_ack_s));
.up_rack (up_rack_s));
// vdma interface

2
library/axi_hdmi_tx/axi_hdmi_tx_constr.xdc
View File

@ -1,6 +1,6 @@
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports hdmi_clk]]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports m_axis_mm2s_clk]]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports s_axi_aclk]]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports m_axis_mm2s_clk]]

495
library/axi_jesd_gt/axi_jesd_gt.v
View File

@ -62,6 +62,7 @@ module axi_jesd_gt (
rx_clk_g,
rx_clk,
rx_data,
rx_data_sof,
rx_gt_charisk,
rx_gt_disperr,
rx_gt_notintable,
@ -71,7 +72,7 @@ module axi_jesd_gt (
rx_ip_sync,
rx_ip_sof,
rx_ip_data,
tx_rst,
tx_clk_g,
tx_clk,
@ -148,7 +149,8 @@ module axi_jesd_gt (
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_NUM_OF_LANES = 4;
parameter PCORE_NUM_OF_TX_LANES = 4;
parameter PCORE_NUM_OF_RX_LANES = 4;
parameter PCORE_QPLL_REFCLK_DIV = 1;
parameter PCORE_QPLL_CFG = 27'h0680181;
parameter PCORE_QPLL_FBDIV_RATIO = 1'b1;
@ -160,206 +162,241 @@ module axi_jesd_gt (
parameter PCORE_TX_CLK25_DIV = 20;
parameter PCORE_PMA_RSV = 32'h001E7080;
parameter PCORE_RX_CDR_CFG = 72'h0b000023ff10400020;
parameter PCORE_TX_LANE_SEL_0 = 0;
parameter PCORE_TX_LANE_SEL_1 = 1;
parameter PCORE_TX_LANE_SEL_2 = 2;
parameter PCORE_TX_LANE_SEL_3 = 3;
parameter PCORE_TX_LANE_SEL_4 = 4;
parameter PCORE_TX_LANE_SEL_5 = 5;
parameter PCORE_TX_LANE_SEL_6 = 6;
parameter PCORE_TX_LANE_SEL_7 = 7;
parameter PCORE_TX_LANE_SEL_8 = 8;
parameter C_S_AXI_MIN_SIZE = 32'hffff;
localparam PCORE_NUM_OF_LANES = (PCORE_NUM_OF_TX_LANES > PCORE_NUM_OF_RX_LANES) ?
PCORE_NUM_OF_TX_LANES : PCORE_NUM_OF_RX_LANES;
// physical interface
input ref_clk_q;
input ref_clk_c;
input ref_clk_q;
input ref_clk_c;
input [((PCORE_NUM_OF_LANES* 1)-1):0] rx_data_p;
input [((PCORE_NUM_OF_LANES* 1)-1):0] rx_data_n;
output rx_sync;
output rx_sysref;
input rx_ext_sysref;
input [((PCORE_NUM_OF_RX_LANES* 1)-1):0] rx_data_p;
input [((PCORE_NUM_OF_RX_LANES* 1)-1):0] rx_data_n;
output rx_sync;
output rx_sysref;
input rx_ext_sysref;
output [((PCORE_NUM_OF_LANES* 1)-1):0] tx_data_p;
output [((PCORE_NUM_OF_LANES* 1)-1):0] tx_data_n;
input tx_sync;
output tx_sysref;
input tx_ext_sysref;
output [((PCORE_NUM_OF_TX_LANES* 1)-1):0] tx_data_p;
output [((PCORE_NUM_OF_TX_LANES* 1)-1):0] tx_data_n;
input tx_sync;
output tx_sysref;
input tx_ext_sysref;
// core interface
output rx_rst;
output rx_clk_g;
input rx_clk;
output [((PCORE_NUM_OF_LANES*32)-1):0] rx_data;
output [((PCORE_NUM_OF_LANES* 4)-1):0] rx_gt_charisk;
output [((PCORE_NUM_OF_LANES* 4)-1):0] rx_gt_disperr;
output [((PCORE_NUM_OF_LANES* 4)-1):0] rx_gt_notintable;
output [((PCORE_NUM_OF_LANES*32)-1):0] rx_gt_data;
output rx_rst_done;
input rx_ip_comma_align;
input rx_ip_sync;
input [ 3:0] rx_ip_sof;
input [((PCORE_NUM_OF_LANES*32)-1):0] rx_ip_data;
output rx_rst;
output rx_clk_g;
input rx_clk;
output [((PCORE_NUM_OF_RX_LANES*32)-1):0] rx_data;
output [((PCORE_NUM_OF_RX_LANES* 1)-1):0] rx_data_sof;
output [((PCORE_NUM_OF_RX_LANES* 4)-1):0] rx_gt_charisk;
output [((PCORE_NUM_OF_RX_LANES* 4)-1):0] rx_gt_disperr;
output [((PCORE_NUM_OF_RX_LANES* 4)-1):0] rx_gt_notintable;
output [((PCORE_NUM_OF_RX_LANES*32)-1):0] rx_gt_data;
output rx_rst_done;
input rx_ip_comma_align;
input rx_ip_sync;
input [ 3:0] rx_ip_sof;
input [((PCORE_NUM_OF_RX_LANES*32)-1):0] rx_ip_data;
output tx_rst;
output tx_clk_g;
input tx_clk;
input [((PCORE_NUM_OF_LANES*32)-1):0] tx_data;
input [((PCORE_NUM_OF_LANES* 4)-1):0] tx_gt_charisk;
input [((PCORE_NUM_OF_LANES*32)-1):0] tx_gt_data;
output tx_rst_done;
output tx_ip_sync;
input [ 3:0] tx_ip_sof;
output [((PCORE_NUM_OF_LANES*32)-1):0] tx_ip_data;
output tx_rst;
output tx_clk_g;
input tx_clk;
input [((PCORE_NUM_OF_TX_LANES*32)-1):0] tx_data;
input [((PCORE_NUM_OF_TX_LANES* 4)-1):0] tx_gt_charisk;
input [((PCORE_NUM_OF_TX_LANES*32)-1):0] tx_gt_data;
output tx_rst_done;
output tx_ip_sync;
input [ 3:0] tx_ip_sof;
output [((PCORE_NUM_OF_TX_LANES*32)-1):0] tx_ip_data;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [ 31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [ 31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [ 31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [ 31:0] s_axi_rdata;
output [ 1:0] s_axi_rresp;
input s_axi_rready;
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [ 31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [ 31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [ 31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [ 31:0] s_axi_rdata;
output [ 1:0] s_axi_rresp;
input s_axi_rready;
// master interface
input m_axi_aclk;
input m_axi_aresetn;
output m_axi_awvalid;
output [ 31:0] m_axi_awaddr;
output [ 2:0] m_axi_awprot;
input m_axi_awready;
output m_axi_wvalid;
output [ 31:0] m_axi_wdata;
output [ 3:0] m_axi_wstrb;
input m_axi_wready;
input m_axi_bvalid;
input [ 1:0] m_axi_bresp;
output m_axi_bready;
output m_axi_arvalid;
output [ 31:0] m_axi_araddr;
output [ 2:0] m_axi_arprot;
input m_axi_arready;
input m_axi_rvalid;
input [ 31:0] m_axi_rdata;
input [ 1:0] m_axi_rresp;
output m_axi_rready;
input m_axi_aclk;
input m_axi_aresetn;
output m_axi_awvalid;
output [ 31:0] m_axi_awaddr;
output [ 2:0] m_axi_awprot;
input m_axi_awready;
output m_axi_wvalid;
output [ 31:0] m_axi_wdata;
output [ 3:0] m_axi_wstrb;
input m_axi_wready;
input m_axi_bvalid;
input [ 1:0] m_axi_bresp;
output m_axi_bready;
output m_axi_arvalid;
output [ 31:0] m_axi_araddr;
output [ 2:0] m_axi_arprot;
input m_axi_arready;
input m_axi_rvalid;
input [ 31:0] m_axi_rdata;
input [ 1:0] m_axi_rresp;
output m_axi_rready;
// drp clock
input drp_clk;
input drp_clk;
// es debug interface
output [275:0] es_dbg_data;
output [ 7:0] es_dbg_trigger;
output [275:0] es_dbg_data;
output [ 7:0] es_dbg_trigger;
// jesd debug interface
output [((PCORE_NUM_OF_LANES*82)+5):0] rx_mon_data;
output [((PCORE_NUM_OF_LANES* 1)+1):0] rx_mon_trigger;
output [((PCORE_NUM_OF_RX_LANES*82)+5):0] rx_mon_data;
output [((PCORE_NUM_OF_RX_LANES* 1)+1):0] rx_mon_trigger;
output [((PCORE_NUM_OF_LANES*36)+5):0] tx_mon_data;
output [ 5:0] tx_mon_trigger;
output [((PCORE_NUM_OF_TX_LANES*36)+5):0] tx_mon_data;
output [ 5:0] tx_mon_trigger;
// reset and clocks
wire gt_pll_rst;
wire gt_rx_rst;
wire gt_tx_rst;
wire qpll_clk_0;
wire qpll_ref_clk_0;
wire qpll_clk_1;
wire qpll_ref_clk_1;
wire [ 7:0] qpll_clk;
wire [ 7:0] qpll_ref_clk;
wire [((PCORE_NUM_OF_LANES* 1)-1):0] rx_out_clk;
wire [((PCORE_NUM_OF_LANES* 1)-1):0] tx_out_clk;
wire axi_rstn;
wire axi_clk;
wire up_rstn;
wire up_clk;
wire drp_rst;
wire gt_pll_rst;
wire gt_rx_rst;
wire gt_tx_rst;
wire qpll_clk_0;
wire qpll_ref_clk_0;
wire qpll_clk_1;
wire qpll_ref_clk_1;
wire [ 7:0] qpll_clk;
wire [ 7:0] qpll_ref_clk;
wire [((PCORE_NUM_OF_LANES* 1)-1):0] rx_out_clk;
wire [((PCORE_NUM_OF_LANES* 1)-1):0] tx_out_clk;
wire axi_rstn;
wire axi_clk;
wire up_rstn;
wire up_clk;
wire drp_rst;
// internal signals
wire [ 8:0] up_status_extn_s;
wire [ 8:0] rx_rst_done_extn_s;
wire [ 8:0] rx_pll_locked_extn_s;
wire [ 8:0] tx_rst_done_extn_s;
wire [ 8:0] tx_pll_locked_extn_s;
wire [((PCORE_NUM_OF_LANES* 1)-1):0] rx_mon_trigger_s;
wire [((PCORE_NUM_OF_LANES*50)-1):0] rx_mon_data_s;
wire [ 15:0] drp_rdata_gt_s[15:0];
wire drp_ready_gt_s[15:0];
wire [ 7:0] drp_rx_rate_gt_s[15:0];
wire qpll_locked_0_s;
wire qpll_locked_1_s;
wire [ 7:0] qpll_locked_s;
wire [((PCORE_NUM_OF_LANES* 1)-1):0] rx_rst_done_s;
wire [((PCORE_NUM_OF_LANES* 1)-1):0] rx_pll_locked_s;
wire [((PCORE_NUM_OF_LANES* 1)-1):0] tx_rst_done_s;
wire [((PCORE_NUM_OF_LANES* 1)-1):0] tx_pll_locked_s;
wire up_cpll_pd_s;
wire [ 1:0] up_rx_sys_clk_sel_s;
wire [ 2:0] up_rx_out_clk_sel_s;
wire [ 1:0] up_tx_sys_clk_sel_s;
wire [ 2:0] up_tx_out_clk_sel_s;
wire drp_sel_s;
wire drp_wr_s;
wire [ 11:0] drp_addr_s;
wire [ 15:0] drp_wdata_s;
wire [ 15:0] drp_rdata_s;
wire drp_ready_s;
wire [ 7:0] drp_lanesel_s;
wire [ 7:0] drp_rx_rate_s;
wire es_sel_s;
wire es_wr_s;
wire [ 11:0] es_addr_s;
wire [ 15:0] es_wdata_s;
wire [ 15:0] es_rdata_s;
wire es_ready_s;
wire es_start_s;
wire es_stop_s;
wire es_init_s;
wire [ 15:0] es_sdata0_s;
wire [ 15:0] es_sdata1_s;
wire [ 15:0] es_sdata2_s;
wire [ 15:0] es_sdata3_s;
wire [ 15:0] es_sdata4_s;
wire [ 15:0] es_qdata0_s;
wire [ 15:0] es_qdata1_s;
wire [ 15:0] es_qdata2_s;
wire [ 15:0] es_qdata3_s;
wire [ 15:0] es_qdata4_s;
wire [ 4:0] es_prescale_s;
wire [ 11:0] es_hoffset_min_s;
wire [ 11:0] es_hoffset_max_s;
wire [ 11:0] es_hoffset_step_s;
wire [ 7:0] es_voffset_min_s;
wire [ 7:0] es_voffset_max_s;
wire [ 7:0] es_voffset_step_s;
wire [ 31:0] es_start_addr_s;
wire es_dmaerr_s;
wire es_status_s;
wire up_sel_s;
wire up_wr_s;
wire [ 13:0] up_addr_s;
wire [ 31:0] up_wdata_s;
wire [ 31:0] up_rdata_s;
wire up_ack_s;
wire [ 8:0] up_status_extn_s;
wire [ 8:0] rx_rst_done_extn_s;
wire [ 8:0] rx_pll_locked_extn_s;
wire [ 8:0] tx_rst_done_extn_s;
wire [ 8:0] tx_pll_locked_extn_s;
wire [((PCORE_NUM_OF_LANES* 1)-1):0] rx_mon_trigger_s;
wire [((PCORE_NUM_OF_LANES*50)-1):0] rx_mon_data_s;
wire [ 15:0] drp_rdata_gt_s[15:0];
wire drp_ready_gt_s[15:0];
wire [ 7:0] drp_rx_rate_gt_s[15:0];
wire [((PCORE_NUM_OF_LANES* 1)-1):0] rx_data_p_s;
wire [((PCORE_NUM_OF_LANES* 1)-1):0] rx_data_n_s;
wire [((PCORE_NUM_OF_LANES*32)-1):0] rx_data_s;
wire [((PCORE_NUM_OF_LANES* 1)-1):0] rx_data_sof_s;
wire [((PCORE_NUM_OF_LANES* 4)-1):0] rx_gt_charisk_s;
wire [((PCORE_NUM_OF_LANES* 4)-1):0] rx_gt_disperr_s;
wire [((PCORE_NUM_OF_LANES* 4)-1):0] rx_gt_notintable_s;
wire [((PCORE_NUM_OF_LANES*32)-1):0] rx_gt_data_s;
wire [((PCORE_NUM_OF_LANES*32)-1):0] rx_ip_data_s;
wire [((PCORE_NUM_OF_LANES* 1)-1):0] tx_data_p_s;
wire [((PCORE_NUM_OF_LANES* 1)-1):0] tx_data_n_s;
wire [((PCORE_NUM_OF_LANES* 4)-1):0] tx_gt_charisk_s;
wire [((PCORE_NUM_OF_LANES*32)-1):0] tx_gt_data_s;
wire [287:0] tx_gt_data_extn_zero_s;
wire [ 35:0] tx_gt_charisk_extn_zero_s;
wire [287:0] tx_gt_data_extn_s;
wire [ 35:0] tx_gt_charisk_extn_s;
wire [287:0] tx_gt_data_mux_s;
wire [ 35:0] tx_gt_charisk_mux_s;
wire qpll_locked_0_s;
wire qpll_locked_1_s;
wire [ 7:0] qpll_locked_s;
wire [((PCORE_NUM_OF_LANES* 1)-1):0] rx_rst_done_s;
wire [((PCORE_NUM_OF_LANES* 1)-1):0] rx_pll_locked_s;
wire [((PCORE_NUM_OF_LANES* 1)-1):0] tx_rst_done_s;
wire [((PCORE_NUM_OF_LANES* 1)-1):0] tx_pll_locked_s;
wire up_cpll_pd_s;
wire [ 1:0] up_rx_sys_clk_sel_s;
wire [ 2:0] up_rx_out_clk_sel_s;
wire [ 1:0] up_tx_sys_clk_sel_s;
wire [ 2:0] up_tx_out_clk_sel_s;
wire drp_sel_s;
wire drp_wr_s;
wire [ 11:0] drp_addr_s;
wire [ 15:0] drp_wdata_s;
wire [ 15:0] drp_rdata_s;
wire drp_ready_s;
wire [ 7:0] drp_lanesel_s;
wire [ 7:0] drp_rx_rate_s;
wire es_sel_s;
wire es_wr_s;
wire [ 11:0] es_addr_s;
wire [ 15:0] es_wdata_s;
wire [ 15:0] es_rdata_s;
wire es_ready_s;
wire es_start_s;
wire es_stop_s;
wire es_init_s;
wire [ 15:0] es_sdata0_s;
wire [ 15:0] es_sdata1_s;
wire [ 15:0] es_sdata2_s;
wire [ 15:0] es_sdata3_s;
wire [ 15:0] es_sdata4_s;
wire [ 15:0] es_qdata0_s;
wire [ 15:0] es_qdata1_s;
wire [ 15:0] es_qdata2_s;
wire [ 15:0] es_qdata3_s;
wire [ 15:0] es_qdata4_s;
wire [ 4:0] es_prescale_s;
wire [ 11:0] es_hoffset_min_s;
wire [ 11:0] es_hoffset_max_s;
wire [ 11:0] es_hoffset_step_s;
wire [ 7:0] es_voffset_min_s;
wire [ 7:0] es_voffset_max_s;
wire [ 7:0] es_voffset_step_s;
wire [ 1:0] es_voffset_range_s;
wire [ 31:0] es_start_addr_s;
wire es_dmaerr_s;
wire es_status_s;
wire up_wreq_s;
wire [ 13:0] up_waddr_s;
wire [ 31:0] up_wdata_s;
wire up_wack_s;
wire up_rreq_s;
wire [ 13:0] up_raddr_s;
wire [ 31:0] up_rdata_s;
wire up_rack_s;
// debug interface
assign rx_mon_data = {rx_sync, rx_sysref, rx_ip_sof, rx_ip_data, rx_mon_data_s};
assign rx_mon_trigger = {rx_sync, rx_sysref, rx_mon_trigger_s};
assign rx_mon_data = {rx_sync, rx_sysref, rx_ip_sof, rx_ip_data, rx_mon_data_s[((PCORE_NUM_OF_RX_LANES*50)-1):0]};
assign rx_mon_trigger = {rx_sync, rx_sysref, rx_mon_trigger_s[((PCORE_NUM_OF_RX_LANES* 1)-1):0]};
assign tx_mon_data = {tx_sync, tx_sysref, tx_ip_sof, tx_gt_charisk, tx_gt_data};
assign tx_mon_trigger = {tx_sync, tx_sysref, tx_ip_sof};
@ -409,8 +446,76 @@ module axi_jesd_gt (
drp_rx_rate_gt_s[ 3] | drp_rx_rate_gt_s[ 2] |
drp_rx_rate_gt_s[ 1] | drp_rx_rate_gt_s[ 0];
// asymmetric widths -- receive
assign rx_data = rx_data_s[((PCORE_NUM_OF_RX_LANES*32)-1):0];
assign rx_data_sof = rx_data_sof_s[((PCORE_NUM_OF_RX_LANES* 1)-1):0];
assign rx_gt_charisk = rx_gt_charisk_s[((PCORE_NUM_OF_RX_LANES* 4)-1):0];
assign rx_gt_disperr = rx_gt_disperr_s[((PCORE_NUM_OF_RX_LANES* 4)-1):0];
assign rx_gt_notintable = rx_gt_notintable_s[((PCORE_NUM_OF_RX_LANES* 4)-1):0];
assign rx_gt_data = rx_gt_data_s[((PCORE_NUM_OF_RX_LANES*32)-1):0];
generate
if (PCORE_NUM_OF_LANES == PCORE_NUM_OF_RX_LANES) begin
assign rx_data_p_s = rx_data_p;
assign rx_data_n_s = rx_data_n;
assign rx_ip_data_s = rx_ip_data;
end else begin
assign rx_data_p_s[((PCORE_NUM_OF_LANES* 1)-1):(PCORE_NUM_OF_RX_LANES* 1)] = 'd0;
assign rx_data_n_s[((PCORE_NUM_OF_LANES* 1)-1):(PCORE_NUM_OF_RX_LANES* 1)] = 'd0;
assign rx_ip_data_s[((PCORE_NUM_OF_LANES*32)-1):(PCORE_NUM_OF_RX_LANES*32)] = 'd0;
assign rx_data_p_s[((PCORE_NUM_OF_RX_LANES* 1)-1):0] = rx_data_p;
assign rx_data_n_s[((PCORE_NUM_OF_RX_LANES* 1)-1):0] = rx_data_n;
assign rx_ip_data_s[((PCORE_NUM_OF_RX_LANES*32)-1):0] = rx_ip_data;
end
endgenerate
// asymmetric widths -- transmit
assign tx_data_p = tx_data_p_s[((PCORE_NUM_OF_TX_LANES* 1)-1):0];
assign tx_data_n = tx_data_n_s[((PCORE_NUM_OF_TX_LANES* 1)-1):0];
generate
if (PCORE_NUM_OF_LANES == PCORE_NUM_OF_TX_LANES) begin
assign tx_gt_charisk_s = tx_gt_charisk;
assign tx_gt_data_s = tx_gt_data;
end else begin
assign tx_gt_charisk_s[((PCORE_NUM_OF_LANES* 4)-1):(PCORE_NUM_OF_TX_LANES* 4)] = 'd0;
assign tx_gt_data_s[((PCORE_NUM_OF_LANES*32)-1):(PCORE_NUM_OF_TX_LANES*32)] = 'd0;
assign tx_gt_charisk_s[((PCORE_NUM_OF_TX_LANES* 4)-1):0] = tx_gt_charisk;
assign tx_gt_data_s[((PCORE_NUM_OF_TX_LANES*32)-1):0] = tx_gt_data;
end
endgenerate
// transmit data interleave -- since transceivers are shared, lane assignments may not match pin assignments
assign tx_ip_data = tx_data;
assign tx_gt_data_extn_zero_s = 288'd0;
assign tx_gt_charisk_extn_zero_s = 36'd0;
assign tx_gt_data_extn_s = {tx_gt_data_extn_zero_s[(((9-PCORE_NUM_OF_LANES)*32)-1):0], tx_gt_data_s};
assign tx_gt_charisk_extn_s = {tx_gt_charisk_extn_zero_s[(((9-PCORE_NUM_OF_LANES)*4)-1):0], tx_gt_charisk_s};
assign tx_gt_data_mux_s[((8*32)+31):(8*32)] = tx_gt_data_extn_s[((PCORE_TX_LANE_SEL_8*32)+31):(PCORE_TX_LANE_SEL_8*32)];
assign tx_gt_data_mux_s[((7*32)+31):(7*32)] = tx_gt_data_extn_s[((PCORE_TX_LANE_SEL_7*32)+31):(PCORE_TX_LANE_SEL_7*32)];
assign tx_gt_data_mux_s[((6*32)+31):(6*32)] = tx_gt_data_extn_s[((PCORE_TX_LANE_SEL_6*32)+31):(PCORE_TX_LANE_SEL_6*32)];
assign tx_gt_data_mux_s[((5*32)+31):(5*32)] = tx_gt_data_extn_s[((PCORE_TX_LANE_SEL_5*32)+31):(PCORE_TX_LANE_SEL_5*32)];
assign tx_gt_data_mux_s[((4*32)+31):(4*32)] = tx_gt_data_extn_s[((PCORE_TX_LANE_SEL_4*32)+31):(PCORE_TX_LANE_SEL_4*32)];
assign tx_gt_data_mux_s[((3*32)+31):(3*32)] = tx_gt_data_extn_s[((PCORE_TX_LANE_SEL_3*32)+31):(PCORE_TX_LANE_SEL_3*32)];
assign tx_gt_data_mux_s[((2*32)+31):(2*32)] = tx_gt_data_extn_s[((PCORE_TX_LANE_SEL_2*32)+31):(PCORE_TX_LANE_SEL_2*32)];
assign tx_gt_data_mux_s[((1*32)+31):(1*32)] = tx_gt_data_extn_s[((PCORE_TX_LANE_SEL_1*32)+31):(PCORE_TX_LANE_SEL_1*32)];
assign tx_gt_data_mux_s[((0*32)+31):(0*32)] = tx_gt_data_extn_s[((PCORE_TX_LANE_SEL_0*32)+31):(PCORE_TX_LANE_SEL_0*32)];
assign tx_gt_charisk_mux_s[((8*4)+3):(8*4)] = tx_gt_charisk_extn_s[((PCORE_TX_LANE_SEL_8*4)+3):(PCORE_TX_LANE_SEL_8*4)];
assign tx_gt_charisk_mux_s[((7*4)+3):(7*4)] = tx_gt_charisk_extn_s[((PCORE_TX_LANE_SEL_7*4)+3):(PCORE_TX_LANE_SEL_7*4)];
assign tx_gt_charisk_mux_s[((6*4)+3):(6*4)] = tx_gt_charisk_extn_s[((PCORE_TX_LANE_SEL_6*4)+3):(PCORE_TX_LANE_SEL_6*4)];
assign tx_gt_charisk_mux_s[((5*4)+3):(5*4)] = tx_gt_charisk_extn_s[((PCORE_TX_LANE_SEL_5*4)+3):(PCORE_TX_LANE_SEL_5*4)];
assign tx_gt_charisk_mux_s[((4*4)+3):(4*4)] = tx_gt_charisk_extn_s[((PCORE_TX_LANE_SEL_4*4)+3):(PCORE_TX_LANE_SEL_4*4)];
assign tx_gt_charisk_mux_s[((3*4)+3):(3*4)] = tx_gt_charisk_extn_s[((PCORE_TX_LANE_SEL_3*4)+3):(PCORE_TX_LANE_SEL_3*4)];
assign tx_gt_charisk_mux_s[((2*4)+3):(2*4)] = tx_gt_charisk_extn_s[((PCORE_TX_LANE_SEL_2*4)+3):(PCORE_TX_LANE_SEL_2*4)];
assign tx_gt_charisk_mux_s[((1*4)+3):(1*4)] = tx_gt_charisk_extn_s[((PCORE_TX_LANE_SEL_1*4)+3):(PCORE_TX_LANE_SEL_1*4)];
assign tx_gt_charisk_mux_s[((0*4)+3):(0*4)] = tx_gt_charisk_extn_s[((PCORE_TX_LANE_SEL_0*4)+3):(PCORE_TX_LANE_SEL_0*4)];
// clock buffers
generate
@ -493,13 +598,21 @@ module axi_jesd_gt (
genvar n;
generate
for (n = PCORE_NUM_OF_LANES; n < 14; n = n + 1) begin: g_unused_1
assign drp_rdata_gt_s[n] = 'd0;
assign drp_ready_gt_s[n] = 'd0;
assign drp_rx_rate_gt_s[n] = 'd0;
end
for (n = 0; n < PCORE_NUM_OF_LANES; n = n + 1) begin: g_lane_1
ad_jesd_align i_jesd_align (
.rx_clk (rx_clk),
.rx_sof (rx_ip_sof),
.rx_ip_data (rx_ip_data[n*32+31:n*32]),
.rx_data (rx_data[n*32+31:n*32]));
.rx_ip_data (rx_ip_data_s[n*32+31:n*32]),
.rx_data_sof(rx_data_sof_s[n]),
.rx_data (rx_data_s[n*32+31:n*32]));
ad_gt_channel_1 #(
.DRP_ID (n),
@ -519,30 +632,30 @@ module axi_jesd_gt (
.qpll_ref_clk (qpll_ref_clk[n]),
.qpll_locked (qpll_locked_s[n]),
.rx_rst (gt_rx_rst),
.rx_p (rx_data_p[n]),
.rx_n (rx_data_n[n]),
.rx_p (rx_data_p_s[n]),
.rx_n (rx_data_n_s[n]),
.rx_sys_clk_sel (up_rx_sys_clk_sel_s),
.rx_out_clk_sel (up_rx_out_clk_sel_s),
.rx_out_clk (rx_out_clk[n]),
.rx_rst_done (rx_rst_done_s[n]),
.rx_pll_locked (rx_pll_locked_s[n]),
.rx_clk (rx_clk),
.rx_charisk (rx_gt_charisk[n*4+3:n*4]),
.rx_disperr (rx_gt_disperr[n*4+3:n*4]),
.rx_notintable (rx_gt_notintable[n*4+3:n*4]),
.rx_data (rx_gt_data[n*32+31:n*32]),
.rx_charisk (rx_gt_charisk_s[n*4+3:n*4]),
.rx_disperr (rx_gt_disperr_s[n*4+3:n*4]),
.rx_notintable (rx_gt_notintable_s[n*4+3:n*4]),
.rx_data (rx_gt_data_s[n*32+31:n*32]),
.rx_comma_align_enb (rx_ip_comma_align),
.tx_rst (gt_tx_rst),
.tx_p (tx_data_p[n]),
.tx_n (tx_data_n[n]),
.tx_p (tx_data_p_s[n]),
.tx_n (tx_data_n_s[n]),
.tx_sys_clk_sel (up_tx_sys_clk_sel_s),
.tx_out_clk_sel (up_tx_out_clk_sel_s),
.tx_out_clk (tx_out_clk[n]),
.tx_rst_done (tx_rst_done_s[n]),
.tx_pll_locked (tx_pll_locked_s[n]),
.tx_clk (tx_clk),
.tx_charisk (tx_gt_charisk[n*4+3:n*4]),
.tx_data (tx_gt_data[n*32+31:n*32]),
.tx_charisk (tx_gt_charisk_mux_s[n*4+3:n*4]),
.tx_data (tx_gt_data_mux_s[n*32+31:n*32]),
.drp_clk (drp_clk),
.drp_sel (drp_sel_s),
.drp_addr (drp_addr_s),
@ -559,7 +672,7 @@ module axi_jesd_gt (
// eye scan
ad_gt_es #(.GTH_GTX_N(0)) i_gt_es (
ad_gt_es #(.GTH_GTX_N(PCORE_DEVICE_TYPE)) i_gt_es (
.drp_rst (drp_rst),
.drp_clk (drp_clk),
.es_sel (es_sel_s),
@ -609,6 +722,7 @@ module axi_jesd_gt (
.es_voffset_min (es_voffset_min_s),
.es_voffset_max (es_voffset_max_s),
.es_voffset_step (es_voffset_step_s),
.es_voffset_range (es_voffset_range_s),
.es_start_addr (es_start_addr_s),
.es_dmaerr (es_dmaerr_s),
.es_status (es_status_s),
@ -664,6 +778,7 @@ module axi_jesd_gt (
.es_stop (es_stop_s),
.es_init (es_init_s),
.es_prescale (es_prescale_s),
.es_voffset_range (es_voffset_range_s),
.es_voffset_step (es_voffset_step_s),
.es_voffset_max (es_voffset_max_s),
.es_voffset_min (es_voffset_min_s),
@ -685,12 +800,14 @@ module axi_jesd_gt (
.es_status (es_status_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_ack (up_ack_s));
.up_rack (up_rack_s));
// axi interface
@ -714,12 +831,14 @@ module axi_jesd_gt (
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_ack (up_ack_s));
.up_rack (up_rack_s));
endmodule

14
library/axi_jesd_gt/axi_jesd_gt_constr.xdc
View File

@ -1,14 +1,4 @@
set_clock_group -asynchronous -group [get_clocks -of_objects [get_ports rx_clk]]
set_clock_group -asynchronous -group [get_clocks -of_objects [get_ports tx_clk]]
set_clock_group -asynchronous -group [get_clocks -of_objects [get_ports s_axi_aclk]]
set_clock_group -asynchronous -group [get_clocks -of_objects [get_ports m_axi_aclk]]
set_false_path -through [get_pins */i_up_gt/i_drp_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins */i_up_gt/i_gt_pll_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins */i_up_gt/i_gt_rx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins */i_up_gt/i_gt_tx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins */i_up_gt/i_rx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins */i_up_gt/i_tx_rst_reg/i_rst_reg/PRE]

3
library/axi_jesd_gt/axi_jesd_gt_ip.tcl
View File

@ -15,7 +15,8 @@ adi_ip_files axi_jesd_gt [list \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/up_drp_cntrl.v" \
"$ad_hdl_dir/library/common/up_gt.v" \
"axi_jesd_gt.v" ]
"axi_jesd_gt.v" \
"axi_jesd_gt_constr.xdc" ]
adi_ip_properties axi_jesd_gt
adi_ip_constraints axi_jesd_gt [list \

440
library/axi_mc_controller/axi_mc_controller.v
View File

@ -42,94 +42,94 @@ module axi_mc_controller
parameter C_S_AXI_MIN_SIZE = 32'hffff
)
(
input ref_clk, // 100 MHz
input ctrl_data_clk,
input ref_clk, // 100 MHz
input ctrl_data_clk,
// physical interface
input fmc_m1_fault_i,
output fmc_m1_en_o,
output pwm_ah_o,
output pwm_al_o,
output pwm_bh_o,
output pwm_bl_o,
output pwm_ch_o,
output pwm_cl_o,
output [7:0] gpo_o,
input fmc_m1_fault_i,
output fmc_m1_en_o,
output pwm_ah_o,
output pwm_al_o,
output pwm_bh_o,
output pwm_bl_o,
output pwm_ch_o,
output pwm_cl_o,
output [7:0] gpo_o,
// controller connections
input pwm_a_i,
input pwm_b_i,
input pwm_c_i,
input ctrl_data_valid_i,
input [31:0] ctrl_data0_i,
input [31:0] ctrl_data1_i,
input [31:0] ctrl_data2_i,
input [31:0] ctrl_data3_i,
input [31:0] ctrl_data4_i,
input [31:0] ctrl_data5_i,
input [31:0] ctrl_data6_i,
input [31:0] ctrl_data7_i,
input pwm_a_i,
input pwm_b_i,
input pwm_c_i,
input ctrl_data_valid_i,
input [31:0] ctrl_data0_i,
input [31:0] ctrl_data1_i,
input [31:0] ctrl_data2_i,
input [31:0] ctrl_data3_i,
input [31:0] ctrl_data4_i,
input [31:0] ctrl_data5_i,
input [31:0] ctrl_data6_i,
input [31:0] ctrl_data7_i,
// interconnection with other modules
output [1:0] sensors_o,
input [2:0] position_i,
output[1:0] sensors_o,
input [2:0] position_i,
// dma interface
output adc_clk_o,
input adc_dovf_i,
input adc_dunf_i,
output adc_enable_c0,
output adc_enable_c1,
output adc_enable_c2,
output adc_enable_c3,
output adc_enable_c4,
output adc_enable_c5,
output adc_enable_c6,
output adc_enable_c7,
output adc_valid_c0,
output adc_valid_c1,
output adc_valid_c2,
output adc_valid_c3,
output adc_valid_c4,
output adc_valid_c5,
output adc_valid_c6,
output adc_valid_c7,
output [31:0] adc_data_c0,
output [31:0] adc_data_c1,
output [31:0] adc_data_c2,
output [31:0] adc_data_c3,
output [31:0] adc_data_c4,
output [31:0] adc_data_c5,
output [31:0] adc_data_c6,
output [31:0] adc_data_c7,
output adc_clk_o,
input adc_dovf_i,
input adc_dunf_i,
output adc_enable_c0,
output adc_enable_c1,
output adc_enable_c2,
output adc_enable_c3,
output adc_enable_c4,
output adc_enable_c5,
output adc_enable_c6,
output adc_enable_c7,
output adc_valid_c0,
output adc_valid_c1,
output adc_valid_c2,
output adc_valid_c3,
output adc_valid_c4,
output adc_valid_c5,
output adc_valid_c6,
output adc_valid_c7,
output [31:0] adc_data_c0,
output [31:0] adc_data_c1,
output [31:0] adc_data_c2,
output [31:0] adc_data_c3,
output [31:0] adc_data_c4,
output [31:0] adc_data_c5,
output [31:0] adc_data_c6,
output [31:0] adc_data_c7,
// axi interface
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [31:0] s_axi_awaddr,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [31:0] s_axi_araddr,
output s_axi_arready,
output s_axi_rvalid,
output [1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
input s_axi_rready
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [31:0] s_axi_awaddr,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [31:0] s_axi_araddr,
output s_axi_arready,
output s_axi_rvalid,
output [1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
input s_axi_rready
);
//------------------------------------------------------------------------------
@ -140,7 +140,8 @@ module axi_mc_controller
reg adc_valid = 'd0;
reg [31:0] adc_data = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_ack = 'd0;
reg up_wack = 'd0;
reg up_rack = 'd0;
reg pwm_gen_clk = 'd0;
reg one_chan_reg = 'd0;
@ -155,9 +156,10 @@ wire up_clk;
// internal signals
wire up_sel_s;
wire up_wr_s;
wire [13:0] up_addr_s;
wire up_rreq_s;
wire up_wreq_s;
wire [13:0] up_raddr_s;
wire [13:0] up_waddr_s;
wire [31:0] up_wdata_s;
wire [31:0] up_adc_common_rdata_s;
wire [31:0] up_control_rdata_s;
@ -169,16 +171,26 @@ wire [31:0] rdata_c4_s;
wire [31:0] rdata_c5_s;
wire [31:0] rdata_c6_s;
wire [31:0] rdata_c7_s;
wire up_adc_common_ack_s;
wire up_control_ack_s;
wire ack_c0_s;
wire ack_c1_s;
wire ack_c2_s;
wire ack_c3_s;
wire ack_c4_s;
wire ack_c5_s;
wire ack_c6_s;
wire ack_c7_s;
wire up_adc_common_wack_s;
wire up_adc_common_rack_s;
wire up_control_wack_s;
wire up_control_rack_s;
wire wack_c0_s;
wire rack_c0_s;
wire wack_c1_s;
wire rack_c1_s;
wire wack_c2_s;
wire rack_c2_s;
wire wack_c3_s;
wire rack_c3_s;
wire wack_c4_s;
wire rack_c4_s;
wire wack_c5_s;
wire rack_c5_s;
wire wack_c6_s;
wire rack_c6_s;
wire wack_c7_s;
wire rack_c7_s;
wire run_s;
wire star_delta_s;
wire dir_s;
@ -187,14 +199,14 @@ wire [10:0] pwm_s;
wire [10:0] gpo_s;
wire dpwm_ah_s;
wire dpwm_al_s;
wire dpwm_bh_s;
wire dpwm_bl_s;
wire dpwm_ch_s;
wire dpwm_cl_s;
wire dpwm_ah_s;
wire dpwm_al_s;
wire dpwm_bh_s;
wire dpwm_bl_s;
wire dpwm_ch_s;
wire dpwm_cl_s;
wire foc_ctrl_s;
wire foc_ctrl_s;
//------------------------------------------------------------------------------
//----------- Assign/Always Blocks ---------------------------------------------
@ -207,23 +219,23 @@ assign up_rstn = s_axi_aresetn;
assign adc_clk_o = ctrl_data_clk;
assign adc_valid_c0 = ctrl_data_valid_i;
assign adc_valid_c1 = ctrl_data_valid_i;
assign adc_valid_c2 = ctrl_data_valid_i;
assign adc_valid_c3 = ctrl_data_valid_i;
assign adc_valid_c4 = ctrl_data_valid_i;
assign adc_valid_c5 = ctrl_data_valid_i;
assign adc_valid_c6 = ctrl_data_valid_i;
assign adc_valid_c7 = ctrl_data_valid_i;
assign adc_valid_c0 = ctrl_data_valid_i;
assign adc_valid_c1 = ctrl_data_valid_i;
assign adc_valid_c2 = ctrl_data_valid_i;
assign adc_valid_c3 = ctrl_data_valid_i;
assign adc_valid_c4 = ctrl_data_valid_i;
assign adc_valid_c5 = ctrl_data_valid_i;
assign adc_valid_c6 = ctrl_data_valid_i;
assign adc_valid_c7 = ctrl_data_valid_i;
assign adc_data_c0 = ctrl_data0_i;
assign adc_data_c1 = ctrl_data1_i;
assign adc_data_c2 = ctrl_data2_i;
assign adc_data_c3 = ctrl_data3_i;
assign adc_data_c4 = ctrl_data4_i;
assign adc_data_c5 = ctrl_data5_i;
assign adc_data_c6 = ctrl_data6_i;
assign adc_data_c7 = ctrl_data7_i;
assign adc_data_c0 = ctrl_data0_i;
assign adc_data_c1 = ctrl_data1_i;
assign adc_data_c2 = ctrl_data2_i;
assign adc_data_c3 = ctrl_data3_i;
assign adc_data_c4 = ctrl_data4_i;
assign adc_data_c5 = ctrl_data5_i;
assign adc_data_c6 = ctrl_data6_i;
assign adc_data_c7 = ctrl_data7_i;
assign ctrl_rst_o = !run_s;
@ -258,10 +270,12 @@ end
always @(negedge up_rstn or posedge up_clk) begin
if(up_rstn == 0) begin
up_rdata <= 'd0;
up_ack <= 'd0;
up_wack <= 'd0;
up_rack <= 'd0;
end else begin
up_rdata <= up_control_rdata_s | up_adc_common_rdata_s | rdata_c0_s | rdata_c1_s | rdata_c2_s | rdata_c3_s | rdata_c4_s | rdata_c5_s | rdata_c6_s | rdata_c7_s;
up_ack <= up_control_ack_s | up_adc_common_ack_s | ack_c0_s | ack_c1_s | ack_c2_s | ack_c3_s | ack_c4_s | ack_c5_s | ack_c6_s | ack_c7_s;
up_rack <= up_control_rack_s | up_adc_common_rack_s | rack_c0_s | rack_c1_s | rack_c2_s | rack_c3_s | rack_c4_s | rack_c5_s | rack_c6_s | rack_c7_s;
up_wack <= up_control_wack_s | up_adc_common_wack_s | wack_c0_s | wack_c1_s | wack_c2_s | wack_c3_s | wack_c4_s | wack_c5_s | wack_c6_s | wack_c7_s;
end
end
@ -288,30 +302,32 @@ motor_driver_inst(
control_registers control_reg_inst(
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_sel(up_sel_s),
.up_wr(up_wr_s),
.up_addr(up_addr_s),
.up_wdata(up_wdata_s),
.up_rdata(up_control_rdata_s),
.up_ack(up_control_ack_s),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_control_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_control_rdata_s),
.up_rack (up_control_rack_s),
.run_o(run_s),
.break_o(),
.dir_o(dir_s),
.star_delta_o(star_delta_s),
.sensors_o(sensors_o),
.kp_o(kp_o),
.ki_o(ki_o),
.kd_o(kd_o),
.kp_o(),
.ki_o(),
.kd_o(),
.kp1_o(),
.ki1_o(),
.kd1_o(),
.gpo_o(gpo_s),
.reference_speed_o(ref_speed_o),
.reference_speed_o(),
.oloop_matlab_o(foc_ctrl_s),
.err_i(err_i),
.err_i(),
.calibrate_adcs_o(),
.pwm_open_o( pwm_open_s));
.pwm_open_o(pwm_open_s));
up_adc_channel #(.PCORE_ADC_CHID(0)) adc_channel0(
.adc_clk(ref_clk),
@ -326,6 +342,8 @@ up_adc_channel #(.PCORE_ADC_CHID(0)) adc_channel0(
.adc_dcfilt_coeff(),
.adc_iqcor_coeff_1(),
.adc_iqcor_coeff_2(),
.adc_pnseq_sel(),
.adc_data_sel(),
.adc_pn_err(1'b0),
.adc_pn_oos(1'b0),
.adc_or(1'b0),
@ -348,12 +366,14 @@ up_adc_channel #(.PCORE_ADC_CHID(0)) adc_channel0(
.adc_usr_decimation_n(16'd1),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_sel(up_sel_s),
.up_wr(up_wr_s),
.up_addr(up_addr_s),
.up_wdata(up_wdata_s),
.up_rdata(rdata_c0_s),
.up_ack(ack_c0_s));
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (wack_c0_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (rdata_c0_s),
.up_rack (rack_c0_s));
up_adc_channel #(.PCORE_ADC_CHID(1)) adc_channel1(
.adc_clk(ref_clk),
@ -368,6 +388,8 @@ up_adc_channel #(.PCORE_ADC_CHID(1)) adc_channel1(
.adc_dcfilt_coeff(),
.adc_iqcor_coeff_1(),
.adc_iqcor_coeff_2(),
.adc_pnseq_sel(),
.adc_data_sel(),
.adc_pn_err(1'b0),
.adc_pn_oos(1'b0),
.adc_or(1'b0),
@ -390,13 +412,15 @@ up_adc_channel #(.PCORE_ADC_CHID(1)) adc_channel1(
.adc_usr_decimation_n(16'd1),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_sel(up_sel_s),
.up_wr(up_wr_s),
.up_addr(up_addr_s),
.up_wdata(up_wdata_s),
.up_rdata(rdata_c1_s),
.up_ack(ack_c1_s));
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (wack_c1_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (rdata_c1_s),
.up_rack (rack_c1_s));
up_adc_channel #(.PCORE_ADC_CHID(2)) adc_channel2(
.adc_clk(ref_clk),
.adc_rst(adc_rst),
@ -410,6 +434,8 @@ up_adc_channel #(.PCORE_ADC_CHID(2)) adc_channel2(
.adc_dcfilt_coeff(),
.adc_iqcor_coeff_1(),
.adc_iqcor_coeff_2(),
.adc_pnseq_sel(),
.adc_data_sel(),
.adc_pn_err(1'b0),
.adc_pn_oos(1'b0),
.adc_or(1'b0),
@ -432,12 +458,14 @@ up_adc_channel #(.PCORE_ADC_CHID(2)) adc_channel2(
.adc_usr_decimation_n(16'd1),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_sel(up_sel_s),
.up_wr(up_wr_s),
.up_addr(up_addr_s),
.up_wdata(up_wdata_s),
.up_rdata(rdata_c2_s),
.up_ack(ack_c2_s));
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (wack_c2_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (rdata_c2_s),
.up_rack (rack_c2_s));
up_adc_channel #(.PCORE_ADC_CHID(3)) adc_channel3(
.adc_clk(ref_clk),
@ -452,6 +480,8 @@ up_adc_channel #(.PCORE_ADC_CHID(3)) adc_channel3(
.adc_dcfilt_coeff(),
.adc_iqcor_coeff_1(),
.adc_iqcor_coeff_2(),
.adc_pnseq_sel(),
.adc_data_sel(),
.adc_pn_err(1'b0),
.adc_pn_oos(1'b0),
.adc_or(1'b0),
@ -474,12 +504,14 @@ up_adc_channel #(.PCORE_ADC_CHID(3)) adc_channel3(
.adc_usr_decimation_n(16'd1),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_sel(up_sel_s),
.up_wr(up_wr_s),
.up_addr(up_addr_s),
.up_wdata(up_wdata_s),
.up_rdata(rdata_c3_s),
.up_ack(ack_c3_s));
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (wack_c3_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (rdata_c3_s),
.up_rack (rack_c3_s));
up_adc_channel #(.PCORE_ADC_CHID(4)) adc_channel4(
.adc_clk(ref_clk),
@ -494,6 +526,8 @@ up_adc_channel #(.PCORE_ADC_CHID(4)) adc_channel4(
.adc_dcfilt_coeff(),
.adc_iqcor_coeff_1(),
.adc_iqcor_coeff_2(),
.adc_pnseq_sel(),
.adc_data_sel(),
.adc_pn_err(1'b0),
.adc_pn_oos(1'b0),
.adc_or(1'b0),
@ -516,13 +550,15 @@ up_adc_channel #(.PCORE_ADC_CHID(4)) adc_channel4(
.adc_usr_decimation_n(16'd1),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_sel(up_sel_s),
.up_wr(up_wr_s),
.up_addr(up_addr_s),
.up_wdata(up_wdata_s),
.up_rdata(rdata_c4_s),
.up_ack(ack_c4_s));
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (wack_c4_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (rdata_c4_s),
.up_rack (rack_c4_s));
up_adc_channel #(.PCORE_ADC_CHID(5)) adc_channel5(
.adc_clk(ref_clk),
.adc_rst(adc_rst),
@ -536,6 +572,8 @@ up_adc_channel #(.PCORE_ADC_CHID(5)) adc_channel5(
.adc_dcfilt_coeff(),
.adc_iqcor_coeff_1(),
.adc_iqcor_coeff_2(),
.adc_pnseq_sel(),
.adc_data_sel(),
.adc_pn_err(1'b0),
.adc_pn_oos(1'b0),
.adc_or(1'b0),
@ -558,12 +596,14 @@ up_adc_channel #(.PCORE_ADC_CHID(5)) adc_channel5(
.adc_usr_decimation_n(16'd1),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_sel(up_sel_s),
.up_wr(up_wr_s),
.up_addr(up_addr_s),
.up_wdata(up_wdata_s),
.up_rdata(rdata_c5_s),
.up_ack(ack_c5_s));
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (wack_c5_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (rdata_c5_s),
.up_rack (rack_c5_s));
up_adc_channel #(.PCORE_ADC_CHID(6)) adc_channel6(
.adc_clk(ref_clk),
@ -578,6 +618,8 @@ up_adc_channel #(.PCORE_ADC_CHID(6)) adc_channel6(
.adc_dcfilt_coeff(),
.adc_iqcor_coeff_1(),
.adc_iqcor_coeff_2(),
.adc_pnseq_sel(),
.adc_data_sel(),
.adc_pn_err(1'b0),
.adc_pn_oos(1'b0),
.adc_or(1'b0),
@ -600,13 +642,15 @@ up_adc_channel #(.PCORE_ADC_CHID(6)) adc_channel6(
.adc_usr_decimation_n(16'd1),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_sel(up_sel_s),
.up_wr(up_wr_s),
.up_addr(up_addr_s),
.up_wdata(up_wdata_s),
.up_rdata(rdata_c6_s),
.up_ack(ack_c6_s));
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (wack_c6_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (rdata_c6_s),
.up_rack (rack_c6_s));
up_adc_channel #(.PCORE_ADC_CHID(7)) adc_channel7(
.adc_clk(ref_clk),
.adc_rst(adc_rst),
@ -620,6 +664,8 @@ up_adc_channel #(.PCORE_ADC_CHID(7)) adc_channel7(
.adc_dcfilt_coeff(),
.adc_iqcor_coeff_1(),
.adc_iqcor_coeff_2(),
.adc_pnseq_sel(),
.adc_data_sel(),
.adc_pn_err(1'b0),
.adc_pn_oos(1'b0),
.adc_or(1'b0),
@ -642,13 +688,15 @@ up_adc_channel #(.PCORE_ADC_CHID(7)) adc_channel7(
.adc_usr_decimation_n(16'd1),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_sel(up_sel_s),
.up_wr(up_wr_s),
.up_addr(up_addr_s),
.up_wdata(up_wdata_s),
.up_rdata(rdata_c7_s),
.up_ack(ack_c7_s));
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (wack_c7_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (rdata_c7_s),
.up_rack (rack_c7_s));
// common processor control
up_adc_common i_up_adc_common(
@ -659,9 +707,15 @@ up_adc_common i_up_adc_common(
.adc_ddr_edgesel(),
.adc_pin_mode(),
.adc_status(1'b1),
.adc_sync_status(1'b0),
.adc_status_ovf(adc_dovf_i),
.adc_status_unf(adc_dunf_i),
.adc_clk_ratio(32'd1),
.adc_start_code(),
.adc_sync(),
.up_status_pn_err(1'b0),
.up_status_pn_oos(1'b0),
.up_status_or(1'b0),
.delay_clk(1'b0),
.delay_rst(),
.delay_sel(),
@ -682,14 +736,18 @@ up_adc_common i_up_adc_common(
.drp_locked(1'b0),
.up_usr_chanmax(),
.adc_usr_chanmax(8'd0),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_sel(up_sel_s),
.up_wr(up_wr_s),
.up_addr(up_addr_s),
.up_wdata(up_wdata_s),
.up_rdata(up_adc_common_rdata_s),
.up_ack(up_adc_common_ack_s));
.up_adc_gpio_in(32'h0),
.up_adc_gpio_out(),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_adc_common_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_adc_common_rdata_s),
.up_rack (up_adc_common_rack_s));
// up bus interface
@ -713,12 +771,14 @@ up_axi i_up_axi(
.up_axi_rresp(s_axi_rresp),
.up_axi_rdata(s_axi_rdata),
.up_axi_rready(s_axi_rready),
.up_sel(up_sel_s),
.up_wr(up_wr_s),
.up_addr(up_addr_s),
.up_wdata(up_wdata_s),
.up_rdata(up_rdata),
.up_ack(up_ack));
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule

56
library/axi_mc_controller/control_registers.v
View File

@ -42,17 +42,19 @@ module control_registers
input up_rstn,
input up_clk,
input up_sel,
input up_wr,
input [13:0] up_addr,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output reg up_wack,
input up_rreq,
input [13:0] up_raddr,
output reg [31:0] up_rdata,
output reg up_ack,
output reg up_rack,
//control
input [31:0] err_i,
output [31:0] pwm_open_o,
output [10:0] pwm_open_o,
output [31:0] reference_speed_o,
output [31:0] kp_o,
output [31:0] ki_o,
@ -96,15 +98,15 @@ reg [10:0] gpo_r;
//internal signals
wire up_sel_s;
wire up_wr_s;
wire up_wreq_s;
wire up_rreq_s;
//------------------------------------------------------------------------------
//----------- Assign/Always Blocks ---------------------------------------------
//------------------------------------------------------------------------------
assign up_sel_s = (up_addr[13:4] == 10'h00) ? up_sel : 1'b0;
assign up_wr_s = up_sel_s & up_wr;
assign up_wreq_s = (up_waddr[13:4] == 10'h00) ? up_wreq : 1'b0;
assign up_rreq_s = (up_raddr[13:4] == 10'h00) ? up_rreq : 1'b0;
assign run_o = control_r[0]; // Run the motor
assign break_o = control_r[2]; // Activate the Break circuit
@ -115,7 +117,7 @@ assign calibrate_adcs_o = control_r[16];
assign oloop_matlab_o = control_r[12]; // Select between open loop control [0] and matlab control [1]
assign gpo_o = control_r[30:20];
assign pwm_open_o = pwm_open_r; // PWM value, for open loop control
assign pwm_open_o = pwm_open_r[10:0]; // PWM value, for open loop control
assign reference_speed_o = reference_speed_r;
assign kp_o = kp_r; // KP controller parameter
assign ki_o = ki_r; // KI controller parameter
@ -130,6 +132,7 @@ always @(negedge up_rstn or posedge up_clk)
begin
if (up_rstn == 0)
begin
up_wack <= 1'b0;
control_r <= 'h0;
reference_speed_r <= 'd1000;
kp_r <= 'd6554;
@ -144,51 +147,52 @@ begin
end
else
begin
if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h3))
up_wack <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h3))
begin
reserved_r1 <= up_wdata;
end
if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h4))
if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h4))
begin
control_r <= up_wdata;
end
if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h5))
if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h5))
begin
reference_speed_r <= up_wdata;
end
if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h6))
if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h6))
begin
kp_r <= up_wdata;
end
if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h7))
if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h7))
begin
ki_r <= up_wdata;
end
if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h8))
if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h8))
begin
kd_r <= up_wdata;
end
if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h9))
if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h9))
begin
kp1_r <= up_wdata;
end
if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'ha))
if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'ha))
begin
ki1_r <= up_wdata;
end
if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'hb))
if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'hb))
begin
kd1_r <= up_wdata;
end
if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'hc))
if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'hc))
begin
pwm_open_r <= up_wdata;
end
if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'hd))
if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'hd))
begin
pwm_break_r <= up_wdata;
end
if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'he))
if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'he))
begin
status_r <= up_wdata;
end
@ -200,14 +204,14 @@ end
always @(negedge up_rstn or posedge up_clk)
begin
if (up_rstn == 0) begin
up_ack <= 'd0;
up_rack <= 'd0;
up_rdata <= 'd0;
end
else
begin
up_ack <= up_sel_s;
if (up_sel_s == 1'b1) begin
case (up_addr[3:0])
up_rack <= up_rreq_s;
if (up_rreq_s == 1'b1) begin
case (up_raddr[3:0])
4'h3: up_rdata <= reserved_r1;
4'h4: up_rdata <= control_r;
4'h5: up_rdata <= reference_speed_r;

135
library/axi_mc_current_monitor/axi_mc_current_monitor.v
View File

@ -45,16 +45,16 @@ module axi_mc_current_monitor
// physical interface
input adc_ia_dat_i,
output adc_ia_clk_o,
input adc_ib_dat_i,
output adc_ib_clk_o,
input adc_it_dat_i,
output adc_it_clk_o,
input adc_vbus_dat_i,
output adc_vbus_clk_o,
input adc_ia_dat_i,
output adc_ia_clk_o,
input adc_ib_dat_i,
output adc_ib_clk_o,
input adc_it_dat_i,
output adc_it_clk_o,
input adc_vbus_dat_i,
output adc_vbus_clk_o,
input ref_clk,
input ref_clk,
output [17:0] ia_o,
output [17:0] ib_o,
@ -106,7 +106,8 @@ reg adc_valid = 'd0;
reg [63:0] adc_data = 'd0;
reg [47:0] adc_data_3 = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_ack = 'd0;
reg up_wack = 'd0;
reg up_rack = 'd0;
reg [1:0] adc_data_cnt = 'd0;
reg [9:0] adc_clk_cnt = 'd0; // used to generate 10 MHz clock for ADCs
reg adc_clk_reg = 'd0; // used to generate 10 MHz clock for ADCs
@ -136,9 +137,10 @@ wire up_clk;
// internal signals
wire up_sel_s;
wire up_wr_s;
wire [13:0] up_addr_s;
wire up_rreq_s;
wire up_wreq_s;
wire [13:0] up_waddr_s;
wire [13:0] up_raddr_s;
wire [31:0] up_wdata_s;
wire [31:0] up_adc_common_rdata_s;
wire up_adc_common_ack_s;
@ -483,12 +485,14 @@ begin
if(up_rstn == 0)
begin
up_rdata <= 'd0;
up_ack <= 'd0;
up_rack <= 'd0;
up_wack <= 'd0;
end
else
begin
up_rdata <= up_adc_common_rdata_s | up_rdata_0_s | up_rdata_1_s | up_rdata_2_s | up_rdata_3_s ;
up_ack <= up_adc_common_ack_s | up_ack_0_s | up_ack_1_s | up_ack_2_s | up_ack_3_s ;
up_rack <= up_adc_common_rack_s | up_rack_0_s | up_rack_1_s | up_rack_2_s | up_rack_3_s ;
up_wack <= up_adc_common_wack_s | up_wack_0_s | up_wack_1_s | up_wack_2_s | up_wack_3_s ;
end
end
@ -547,6 +551,8 @@ up_adc_channel #(.PCORE_ADC_CHID(0)) i_up_adc_channel_ia(
.adc_dcfilt_coeff(),
.adc_iqcor_coeff_1(),
.adc_iqcor_coeff_2(),
.adc_pnseq_sel(),
.adc_data_sel(),
.adc_pn_err(1'b0),
.adc_pn_oos(1'b0),
.adc_or(1'b0),
@ -569,12 +575,14 @@ up_adc_channel #(.PCORE_ADC_CHID(0)) i_up_adc_channel_ia(
.adc_usr_decimation_n(16'd1),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_sel(up_sel_s),
.up_wr(up_wr_s),
.up_addr(up_addr_s),
.up_wdata(up_wdata_s),
.up_rdata(up_rdata_0_s),
.up_ack(up_ack_0_s));
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_0_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_0_s),
.up_rack (up_rack_0_s));
up_adc_channel #(.PCORE_ADC_CHID(1)) i_up_adc_channel_ib(
.adc_clk(adc_clk_s),
@ -611,12 +619,14 @@ up_adc_channel #(.PCORE_ADC_CHID(1)) i_up_adc_channel_ib(
.adc_usr_decimation_n(16'd1),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_sel(up_sel_s),
.up_wr(up_wr_s),
.up_addr(up_addr_s),
.up_wdata(up_wdata_s),
.up_rdata(up_rdata_1_s),
.up_ack(up_ack_1_s));
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_1_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_1_s),
.up_rack (up_rack_1_s));
up_adc_channel #(.PCORE_ADC_CHID(2)) i_up_adc_channel_it(
.adc_clk(adc_clk_s),
@ -653,12 +663,14 @@ up_adc_channel #(.PCORE_ADC_CHID(2)) i_up_adc_channel_it(
.adc_usr_decimation_n(16'd1),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_sel(up_sel_s),
.up_wr(up_wr_s),
.up_addr(up_addr_s),
.up_wdata(up_wdata_s),
.up_rdata(up_rdata_2_s),
.up_ack(up_ack_2_s));
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_2_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_2_s),
.up_rack (up_rack_2_s));
up_adc_channel #(.PCORE_ADC_CHID(3)) i_up_adc_channel_vbus(
.adc_clk(adc_clk_s),
@ -695,13 +707,14 @@ up_adc_channel #(.PCORE_ADC_CHID(3)) i_up_adc_channel_vbus(
.adc_usr_decimation_n(16'd1),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_sel(up_sel_s),
.up_wr(up_wr_s),
.up_addr(up_addr_s),
.up_wdata(up_wdata_s),
.up_rdata(up_rdata_3_s),
.up_ack(up_ack_3_s));
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_3_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_3_s),
.up_rack (up_rack_3_s));
// common processor control
@ -713,9 +726,16 @@ up_adc_common i_up_adc_common(
.adc_ddr_edgesel(),
.adc_pin_mode(),
.adc_status(1'b1),
.adc_sync_status(1'b0),
.adc_status_ovf(adc_dovf_i),
.adc_status_unf(adc_dunf_i),
.adc_clk_ratio(32'd1),
.adc_start_code(),
.adc_sync(),
.up_status_pn_err(1'b0),
.up_status_pn_oos(1'b0),
.up_status_or(1'b0),
.delay_clk(1'b0),
.delay_rst(),
@ -739,16 +759,19 @@ up_adc_common i_up_adc_common(
.up_usr_chanmax(),
.adc_usr_chanmax(8'd0),
.up_adc_gpio_in(32'h0),
.up_adc_gpio_out(),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_sel(up_sel_s),
.up_wr(up_wr_s),
.up_addr(up_addr_s),
.up_wdata(up_wdata_s),
.up_rdata(up_adc_common_rdata_s),
.up_ack(up_adc_common_ack_s)
);
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_adc_common_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_adc_common_rdata_s),
.up_rack (up_adc_common_rack_s));
// up bus interface
@ -772,12 +795,14 @@ up_axi i_up_axi(
.up_axi_rresp(s_axi_rresp),
.up_axi_rdata(s_axi_rdata),
.up_axi_rready(s_axi_rready),
.up_sel(up_sel_s),
.up_wr(up_wr_s),
.up_addr(up_addr_s),
.up_wdata(up_wdata_s),
.up_rdata(up_rdata),
.up_ack(up_ack));
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule

51
library/axi_mc_speed/axi_mc_speed.v
View File

@ -96,7 +96,8 @@ module axi_mc_speed
reg adc_valid = 'd0;
reg [31:0] adc_data = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_ack = 'd0;
reg up_wack = 'd0;
reg up_rack = 'd0;
//------------------------------------------------------------------------------
//----------- Wires Declarations -----------------------------------------------
@ -113,12 +114,14 @@ wire adc_start_s;
wire [31:0] speed_data_s;
wire adc_enable_s;
wire adc_status_s;
wire up_sel_s;
wire up_wr_s;
wire [13:0] up_addr_s;
wire up_rreq_s;
wire up_wreq_s;
wire [13:0] up_waddr_s;
wire [13:0] up_raddr_s;
wire [31:0] up_wdata_s;
wire [31:0] up_adc_common_rdata_s;
wire up_adc_common_ack_s;
wire up_adc_common_wack_s;
wire up_adc_common_rack_s;
wire [31:0] pid_s;
wire [ 2:0] position_s;
@ -164,11 +167,13 @@ begin
if(up_rstn == 0)
begin
up_rdata <= 'd0;
up_ack <= 'd0;
up_wack <= 'd0;
up_rack <= 'd0;
end else
begin
up_rdata <= up_adc_common_rdata_s;
up_ack <= up_adc_common_ack_s;
up_wack <= up_adc_common_wack_s;
up_rack <= up_adc_common_rack_s;
end
end
@ -275,15 +280,19 @@ up_adc_common i_up_adc_common(
.drp_locked(1'b0),
.up_usr_chanmax(),
.adc_usr_chanmax(8'd0),
.up_adc_gpio_in(),
.up_adc_gpio_out(),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_sel(up_sel_s),
.up_wr(up_wr_s),
.up_addr(up_addr_s),
.up_wdata(up_wdata_s),
.up_rdata(up_adc_common_rdata_s),
.up_ack(up_adc_common_ack_s)
);
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_adc_common_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_adc_common_rdata_s),
.up_rack (up_adc_common_rack_s));
// up bus interface
up_axi i_up_axi(
@ -306,12 +315,14 @@ up_axi i_up_axi(
.up_axi_rresp(s_axi_rresp),
.up_axi_rdata(s_axi_rdata),
.up_axi_rready(s_axi_rready),
.up_sel(up_sel_s),
.up_wr(up_wr_s),
.up_addr(up_addr_s),
.up_wdata(up_wdata_s),
.up_rdata(up_rdata),
.up_ack(up_ack));
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule

6
library/axi_spdif_tx/axi_spdif_tx_constr.xdc
View File

@ -1,8 +1,4 @@
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports spdif_data_clk]]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports S_AXIS_ACLK]]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports DMA_REQ_ACLK]]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports S_AXI_ACLK]]

3
library/axi_spdif_tx/axi_spdif_tx_ip.tcl
View File

@ -11,7 +11,8 @@ adi_ip_files axi_spdif_tx [list \
"$ad_hdl_dir/library/common/dma_fifo.vhd" \
"tx_package.vhd" \
"tx_encoder.vhd" \
"axi_spdif_tx.vhd" ]
"axi_spdif_tx.vhd" \
"axi_spdif_tx_constr.xdc" ]
adi_ip_properties_lite axi_spdif_tx

54
library/common/ad_gt_es.v
View File

@ -96,6 +96,7 @@ module ad_gt_es (
es_voffset_min,
es_voffset_max,
es_voffset_step,
es_voffset_range,
es_start_addr,
es_dmaerr,
es_status,
@ -111,22 +112,22 @@ module ad_gt_es (
// gt address
localparam ES_DRP_CTRL_ADDR = (GTH_GTX_N == 1) ? 12'h03d : 12'h03d;
localparam ES_DRP_SDATA0_ADDR = (GTH_GTX_N == 1) ? 12'h036 : 12'h036;
localparam ES_DRP_SDATA1_ADDR = (GTH_GTX_N == 1) ? 12'h037 : 12'h037;
localparam ES_DRP_SDATA2_ADDR = (GTH_GTX_N == 1) ? 12'h038 : 12'h038;
localparam ES_DRP_SDATA3_ADDR = (GTH_GTX_N == 1) ? 12'h039 : 12'h039;
localparam ES_DRP_SDATA4_ADDR = (GTH_GTX_N == 1) ? 12'h03a : 12'h03a;
localparam ES_DRP_QDATA0_ADDR = (GTH_GTX_N == 1) ? 12'h031 : 12'h031;
localparam ES_DRP_QDATA1_ADDR = (GTH_GTX_N == 1) ? 12'h032 : 12'h032;
localparam ES_DRP_QDATA2_ADDR = (GTH_GTX_N == 1) ? 12'h033 : 12'h033;
localparam ES_DRP_QDATA3_ADDR = (GTH_GTX_N == 1) ? 12'h034 : 12'h034;
localparam ES_DRP_QDATA4_ADDR = (GTH_GTX_N == 1) ? 12'h035 : 12'h035;
localparam ES_DRP_HOFFSET_ADDR = (GTH_GTX_N == 1) ? 12'h03c : 12'h03c;
localparam ES_DRP_VOFFSET_ADDR = (GTH_GTX_N == 1) ? 12'h03b : 12'h03b;
localparam ES_DRP_STATUS_ADDR = (GTH_GTX_N == 1) ? 12'h153 : 12'h151;
localparam ES_DRP_SCNT_ADDR = (GTH_GTX_N == 1) ? 12'h152 : 12'h150;
localparam ES_DRP_ECNT_ADDR = (GTH_GTX_N == 1) ? 12'h151 : 12'h14f;
localparam ES_DRP_CTRL_ADDR = (GTH_GTX_N == 1) ? 12'h03c : 12'h03d; // GTH-7 12'h03d
localparam ES_DRP_SDATA0_ADDR = (GTH_GTX_N == 1) ? 12'h049 : 12'h036; // GTH-7 12'h036
localparam ES_DRP_SDATA1_ADDR = (GTH_GTX_N == 1) ? 12'h04a : 12'h037; // GTH-7 12'h037
localparam ES_DRP_SDATA2_ADDR = (GTH_GTX_N == 1) ? 12'h04b : 12'h038; // GTH-7 12'h038
localparam ES_DRP_SDATA3_ADDR = (GTH_GTX_N == 1) ? 12'h04c : 12'h039; // GTH-7 12'h039
localparam ES_DRP_SDATA4_ADDR = (GTH_GTX_N == 1) ? 12'h04d : 12'h03a; // GTH-7 12'h03a
localparam ES_DRP_QDATA0_ADDR = (GTH_GTX_N == 1) ? 12'h044 : 12'h031; // GTH-7 12'h031
localparam ES_DRP_QDATA1_ADDR = (GTH_GTX_N == 1) ? 12'h045 : 12'h032; // GTH-7 12'h032
localparam ES_DRP_QDATA2_ADDR = (GTH_GTX_N == 1) ? 12'h046 : 12'h033; // GTH-7 12'h033
localparam ES_DRP_QDATA3_ADDR = (GTH_GTX_N == 1) ? 12'h047 : 12'h034; // GTH-7 12'h034
localparam ES_DRP_QDATA4_ADDR = (GTH_GTX_N == 1) ? 12'h048 : 12'h035; // GTH-7 12'h035
localparam ES_DRP_HOFFSET_ADDR = (GTH_GTX_N == 1) ? 12'h04f : 12'h03c; // GTH-7 12'h03c
localparam ES_DRP_VOFFSET_ADDR = (GTH_GTX_N == 1) ? 12'h097 : 12'h03b; // GTH-7 12'h03b
localparam ES_DRP_STATUS_ADDR = (GTH_GTX_N == 1) ? 12'h153 : 12'h151; // GTH-7 12'h153
localparam ES_DRP_SCNT_ADDR = (GTH_GTX_N == 1) ? 12'h152 : 12'h150; // GTH-7 12'h152
localparam ES_DRP_ECNT_ADDR = (GTH_GTX_N == 1) ? 12'h151 : 12'h14f; // GTH-7 12'h151
// state machine
@ -238,6 +239,7 @@ module ad_gt_es (
input [ 7:0] es_voffset_min;
input [ 7:0] es_voffset_max;
input [ 7:0] es_voffset_step;
input [ 1:0] es_voffset_range;
input [31:0] es_start_addr;
output es_dmaerr;
output es_status;
@ -745,7 +747,11 @@ module ad_gt_es (
es_sel <= 1'b1;
es_wr <= 1'b1;
es_addr <= ES_DRP_CTRL_ADDR;
if (GTH_GTX_N == 1) begin
es_wdata <= {es_ctrl_rdata[15:10], 2'b11, es_ctrl_rdata[7:5], es_prescale};
end else begin
es_wdata <= {es_ctrl_rdata[15:10], 2'b11, es_ctrl_rdata[7:0]};
end
end
ES_FSM_SDATA0_WRITE: begin
es_sel <= 1'b1;
@ -817,7 +823,11 @@ module ad_gt_es (
es_sel <= 1'b1;
es_wr <= 1'b1;
es_addr <= ES_DRP_HOFFSET_ADDR;
if (GTH_GTX_N == 1) begin
es_wdata <= {es_hoffset, es_hoffset_rdata[3:0]};
end else begin
es_wdata <= {es_hoffset_rdata[15:12], es_hoffset};
end
end
ES_FSM_VOFFSET_READ: begin
es_sel <= 1'b1;
@ -829,7 +839,11 @@ module ad_gt_es (
es_sel <= 1'b1;
es_wr <= 1'b1;
es_addr <= ES_DRP_VOFFSET_ADDR;
if (GTH_GTX_N == 1) begin
es_wdata <= {es_voffset_rdata[15:11], es_voffset_s[7], es_ut, es_voffset_s[6:0], es_voffset_range};
end else begin
es_wdata <= {es_prescale, es_voffset_rdata[10:9], es_ut, es_voffset_s};
end
end
ES_FSM_CTRLSTART_READ: begin
es_sel <= 1'b1;
@ -841,7 +855,11 @@ module ad_gt_es (
es_sel <= 1'b1;
es_wr <= 1'b1;
es_addr <= ES_DRP_CTRL_ADDR;
if (GTH_GTX_N == 1) begin
es_wdata <= {6'd1, es_ctrl_rdata[9:0]};
end else begin
es_wdata <= {es_ctrl_rdata[15:6], 6'd1};
end
end
ES_FSM_STATUS_READ: begin
es_sel <= 1'b1;
@ -859,7 +877,11 @@ module ad_gt_es (
es_sel <= 1'b1;
es_wr <= 1'b1;
es_addr <= ES_DRP_CTRL_ADDR;
if (GTH_GTX_N == 1) begin
es_wdata <= {6'd0, es_ctrl_rdata[9:0]};
end else begin
es_wdata <= {es_ctrl_rdata[15:6], 6'd0};
end
end
ES_FSM_SCNT_READ: begin
es_sel <= 1'b1;

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