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jesd204: Update Makefiles 

Fix jesd204 library build.
main
AndreiGrozav 2018-06-11 08:35:13 +01:00 committed by AndreiGrozav
parent 146f85c8fd
commit b6663c6e0d
3 changed files with 13 additions and 24 deletions
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4
library/Makefile
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@ -35,7 +35,6 @@ clean:
$(MAKE) -C axi_ad9265 clean
$(MAKE) -C axi_ad9361 clean
$(MAKE) -C axi_ad9371 clean
$(MAKE) -C axi_adrv9009 clean
$(MAKE) -C axi_ad9434 clean
$(MAKE) -C axi_ad9467 clean
$(MAKE) -C axi_ad9625 clean
@ -46,6 +45,7 @@ clean:
$(MAKE) -C axi_ad9963 clean
$(MAKE) -C axi_adc_decimate clean
$(MAKE) -C axi_adc_trigger clean
$(MAKE) -C axi_adrv9009 clean
$(MAKE) -C axi_clkgen clean
$(MAKE) -C axi_dac_interpolate clean
$(MAKE) -C axi_dmac clean
@ -143,7 +143,6 @@ lib:
$(MAKE) -C axi_ad9265
$(MAKE) -C axi_ad9361
$(MAKE) -C axi_ad9371
$(MAKE) -C axi_adrv9009
$(MAKE) -C axi_ad9434
$(MAKE) -C axi_ad9467
$(MAKE) -C axi_ad9625
@ -154,6 +153,7 @@ lib:
$(MAKE) -C axi_ad9963
$(MAKE) -C axi_adc_decimate
$(MAKE) -C axi_adc_trigger
$(MAKE) -C axi_adrv9009
$(MAKE) -C axi_clkgen
$(MAKE) -C axi_dac_interpolate
$(MAKE) -C axi_dmac

18
library/jesd204/ad_ip_jesd204_tpl_adc/Makefile
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@ -15,25 +15,19 @@ GENERIC_DEPS += ../../common/up_axi.v
GENERIC_DEPS += ../../common/up_clock_mon.v
GENERIC_DEPS += ../../common/up_xfer_cntrl.v
GENERIC_DEPS += ../../common/up_xfer_status.v
GENERIC_DEPS += ad_ip_jesd204_tpl_adc.v
GENERIC_DEPS += ad_ip_jesd204_tpl_adc_channel.v
GENERIC_DEPS += ad_ip_jesd204_tpl_adc_core.v
GENERIC_DEPS += ad_ip_jesd204_tpl_adc_deframer.v
GENERIC_DEPS += ad_ip_jesd204_tpl_adc_pnmon.v
GENERIC_DEPS += ad_ip_jesd204_tpl_adc_regmap.v
XILINX_DEPS += ../../xilinx/common/ad_rst_constr.xdc
XILINX_DEPS += ../../xilinx/common/up_clock_mon_constr.xdc
XILINX_DEPS += ../../xilinx/common/up_xfer_cntrl_constr.xdc
XILINX_DEPS += ../../xilinx/common/up_xfer_status_constr.xdc
XILINX_DEPS += ad_ip_jesd204_tpl_adc.v
XILINX_DEPS += ad_ip_jesd204_tpl_adc_channel.v
XILINX_DEPS += ad_ip_jesd204_tpl_adc_core.v
XILINX_DEPS += ad_ip_jesd204_tpl_adc_deframer.v
XILINX_DEPS += ad_ip_jesd204_tpl_adc_ip.tcl
XILINX_DEPS += ad_ip_jesd204_tpl_adc_pnmon.v
XILINX_DEPS += ad_ip_jesd204_tpl_adc_regmap.v
ALTERA_DEPS += ../../ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.v
ALTERA_DEPS += ../../ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_channel.v
ALTERA_DEPS += ../../ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_core.v
ALTERA_DEPS += ../../ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_deframer.v
ALTERA_DEPS += ../../ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_pnmon.v
ALTERA_DEPS += ../../ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v
ALTERA_DEPS += ../../altera/common/up_clock_mon_constr.sdc
ALTERA_DEPS += ../../altera/common/up_rst_constr.sdc
ALTERA_DEPS += ../../altera/common/up_xfer_cntrl_constr.sdc

15
library/jesd204/ad_ip_jesd204_tpl_dac/Makefile
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@ -15,24 +15,19 @@ GENERIC_DEPS += ../../common/up_dac_channel.v
GENERIC_DEPS += ../../common/up_dac_common.v
GENERIC_DEPS += ../../common/up_xfer_cntrl.v
GENERIC_DEPS += ../../common/up_xfer_status.v
GENERIC_DEPS += ad_ip_jesd204_tpl_dac.v
GENERIC_DEPS += ad_ip_jesd204_tpl_dac_channel.v
GENERIC_DEPS += ad_ip_jesd204_tpl_dac_core.v
GENERIC_DEPS += ad_ip_jesd204_tpl_dac_framer.v
GENERIC_DEPS += ad_ip_jesd204_tpl_dac_regmap.v
XILINX_DEPS += ../../xilinx/common/ad_mul.v
XILINX_DEPS += ../../xilinx/common/ad_rst_constr.xdc
XILINX_DEPS += ../../xilinx/common/up_clock_mon_constr.xdc
XILINX_DEPS += ../../xilinx/common/up_xfer_cntrl_constr.xdc
XILINX_DEPS += ../../xilinx/common/up_xfer_status_constr.xdc
XILINX_DEPS += ad_ip_jesd204_tpl_dac.v
XILINX_DEPS += ad_ip_jesd204_tpl_dac_channel.v
XILINX_DEPS += ad_ip_jesd204_tpl_dac_core.v
XILINX_DEPS += ad_ip_jesd204_tpl_dac_framer.v
XILINX_DEPS += ad_ip_jesd204_tpl_dac_ip.tcl
XILINX_DEPS += ad_ip_jesd204_tpl_dac_regmap.v
ALTERA_DEPS += ../../ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.v
ALTERA_DEPS += ../../ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_channel.v
ALTERA_DEPS += ../../ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_core.v
ALTERA_DEPS += ../../ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_framer.v
ALTERA_DEPS += ../../ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v
ALTERA_DEPS += ../../altera/common/ad_mul.v
ALTERA_DEPS += ../../altera/common/up_clock_mon_constr.sdc
ALTERA_DEPS += ../../altera/common/up_rst_constr.sdc