From b622b6592ebf559907d1f1dbbea2da91ef7a1310 Mon Sep 17 00:00:00 2001 From: Nick Pillitteri Date: Fri, 13 Jan 2017 07:47:16 -0500 Subject: [PATCH] FMCOMMS5/ZCU102 : Merge from njpillitteri/hdl:dev Pull request Dev #26 --- projects/fmcomms5/Makefile | 3 + projects/fmcomms5/zcu102/Makefile | 81 +++++ projects/fmcomms5/zcu102/system_bd.tcl | 10 + projects/fmcomms5/zcu102/system_constr.xdc | 135 ++++++++ projects/fmcomms5/zcu102/system_project.tcl | 17 ++ projects/fmcomms5/zcu102/system_top.v | 323 ++++++++++++++++++++ 6 files changed, 569 insertions(+) create mode 100644 projects/fmcomms5/zcu102/Makefile create mode 100644 projects/fmcomms5/zcu102/system_bd.tcl create mode 100644 projects/fmcomms5/zcu102/system_constr.xdc create mode 100644 projects/fmcomms5/zcu102/system_project.tcl create mode 100644 projects/fmcomms5/zcu102/system_top.v diff --git a/projects/fmcomms5/Makefile b/projects/fmcomms5/Makefile index 1aadef09e..f7de0659c 100644 --- a/projects/fmcomms5/Makefile +++ b/projects/fmcomms5/Makefile @@ -9,16 +9,19 @@ all: -make -C zc702 all -make -C zc706 all + -make -C zcu102 all clean: make -C zc702 clean make -C zc706 clean + make -C zcu102 clean clean-all: make -C zc702 clean-all make -C zc706 clean-all + make -C zcu102 clean-all #################################################################################### #################################################################################### diff --git a/projects/fmcomms5/zcu102/Makefile b/projects/fmcomms5/zcu102/Makefile new file mode 100644 index 000000000..9ec988e1f --- /dev/null +++ b/projects/fmcomms5/zcu102/Makefile @@ -0,0 +1,81 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS += system_top.v +M_DEPS += system_project.tcl +M_DEPS += system_constr.xdc +M_DEPS += system_bd.tcl +M_DEPS += ../common/fmcomms5_bd.tcl +M_DEPS += ../../scripts/adi_project.tcl +M_DEPS += ../../scripts/adi_env.tcl +M_DEPS += ../../scripts/adi_board.tcl +M_DEPS += ../../common/zcu102/zcu102_system_constr.xdc +M_DEPS += ../../common/zcu102/zcu102_system_bd.tcl +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v +M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr +M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr +M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr +M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr +M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr +M_DEPS += ../../../library/util_cpack/util_cpack.xpr +M_DEPS += ../../../library/util_upack/util_upack.xpr +M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.cache +M_FLIST += *.data +M_FLIST += *.xpr +M_FLIST += *.log +M_FLIST += *.jou +M_FLIST += xgui +M_FLIST += *.runs +M_FLIST += *.srcs +M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim +M_FLIST += .Xil +M_FLIST += *.ip_user_files + + + +.PHONY: all lib clean clean-all +all: lib fmcomms5_zcu102.sdk/system_top.hdf + + +clean: + rm -rf $(M_FLIST) + + +clean-all:clean + make -C ../../../library/axi_ad9361 clean + make -C ../../../library/axi_clkgen clean + make -C ../../../library/axi_dmac clean + make -C ../../../library/axi_hdmi_tx clean + make -C ../../../library/axi_spdif_tx clean + make -C ../../../library/util_cpack clean + make -C ../../../library/util_upack clean + make -C ../../../library/util_wfifo clean + + +fmcomms5_zcu102.sdk/system_top.hdf: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) system_project.tcl >> fmcomms5_zcu102_vivado.log 2>&1 + + +lib: + make -C ../../../library/axi_ad9361 + make -C ../../../library/axi_clkgen + make -C ../../../library/axi_dmac + make -C ../../../library/axi_hdmi_tx + make -C ../../../library/axi_spdif_tx + make -C ../../../library/util_cpack + make -C ../../../library/util_upack + make -C ../../../library/util_wfifo + +#################################################################################### +#################################################################################### diff --git a/projects/fmcomms5/zcu102/system_bd.tcl b/projects/fmcomms5/zcu102/system_bd.tcl new file mode 100644 index 000000000..202c3155f --- /dev/null +++ b/projects/fmcomms5/zcu102/system_bd.tcl @@ -0,0 +1,10 @@ + +source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl + +set_property -dict [list CONFIG.PSU__FPGA_PL2_ENABLE {1}] $sys_ps8 +set_property -dict [list CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {200}] $sys_ps8 +ad_connect sys_dma_clk sys_ps8/pl_clk2 +source ../common/fmcomms5_bd.tcl + +set_property CONFIG.DEVICE_TYPE 2 [get_bd_cells axi_ad9361_0] +set_property CONFIG.DEVICE_TYPE 2 [get_bd_cells axi_ad9361_1] diff --git a/projects/fmcomms5/zcu102/system_constr.xdc b/projects/fmcomms5/zcu102/system_constr.xdc new file mode 100644 index 000000000..137c1a62d --- /dev/null +++ b/projects/fmcomms5/zcu102/system_constr.xdc @@ -0,0 +1,135 @@ + +# constraints + +# ad9361 master + +set_property -dict {PACKAGE_PIN P11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports ref_clk_p] ; ## D20 FMC_HPC0_LA17_CC_P +set_property -dict {PACKAGE_PIN N11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports ref_clk_n] ; ## D21 FMC_HPC0_LA17_CC_N + +set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_clk_in_0_p] ; ## G06 FMC_HPC0_LA00_CC_P +set_property -dict {PACKAGE_PIN Y3 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_clk_in_0_n] ; ## G07 FMC_HPC0_LA00_CC_N +set_property -dict {PACKAGE_PIN W2 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_frame_in_0_p] ; ## D08 FMC_HPC0_LA01_CC_P +set_property -dict {PACKAGE_PIN W1 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_frame_in_0_n] ; ## D09 FMC_HPC0_LA01_CC_N +set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_0_p[0]] ; ## H07 FMC_HPC0_LA02_P +set_property -dict {PACKAGE_PIN V1 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_0_n[0]] ; ## H08 FMC_HPC0_LA02_N +set_property -dict {PACKAGE_PIN Y2 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_0_p[1]] ; ## G09 FMC_HPC0_LA03_P +set_property -dict {PACKAGE_PIN Y1 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_0_n[1]] ; ## G10 FMC_HPC0_LA03_N +set_property -dict {PACKAGE_PIN AA2 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_0_p[2]] ; ## H10 FMC_HPC0_LA04_P +set_property -dict {PACKAGE_PIN AA1 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_0_n[2]] ; ## H11 FMC_HPC0_LA04_N +set_property -dict {PACKAGE_PIN AB3 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_0_p[3]] ; ## D11 FMC_HPC0_LA05_P +set_property -dict {PACKAGE_PIN AC3 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_0_n[3]] ; ## D12 FMC_HPC0_LA05_N +set_property -dict {PACKAGE_PIN AC2 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_0_p[4]] ; ## C10 FMC_HPC0_LA06_P +set_property -dict {PACKAGE_PIN AC1 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_0_n[4]] ; ## C11 FMC_HPC0_LA06_N +set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_0_p[5]] ; ## H13 FMC_HPC0_LA07_P +set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_0_n[5]] ; ## H14 FMC_HPC0_LA07_N +set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVDS} [get_ports tx_clk_out_0_p] ; ## G12 FMC_HPC0_LA08_P +set_property -dict {PACKAGE_PIN V3 IOSTANDARD LVDS} [get_ports tx_clk_out_0_n] ; ## G13 FMC_HPC0_LA08_N +set_property -dict {PACKAGE_PIN AB4 IOSTANDARD LVDS} [get_ports tx_frame_out_0_p] ; ## D14 FMC_HPC0_LA09_P +set_property -dict {PACKAGE_PIN AC4 IOSTANDARD LVDS} [get_ports tx_frame_out_0_n] ; ## D15 FMC_HPC0_LA09_N +set_property -dict {PACKAGE_PIN W5 IOSTANDARD LVDS} [get_ports tx_data_out_0_p[0]] ; ## C14 FMC_HPC0_LA10_P +set_property -dict {PACKAGE_PIN W4 IOSTANDARD LVDS} [get_ports tx_data_out_0_n[0]] ; ## C15 FMC_HPC0_LA10_N +set_property -dict {PACKAGE_PIN AB6 IOSTANDARD LVDS} [get_ports tx_data_out_0_p[1]] ; ## H16 FMC_HPC0_LA11_P +set_property -dict {PACKAGE_PIN AB5 IOSTANDARD LVDS} [get_ports tx_data_out_0_n[1]] ; ## H17 FMC_HPC0_LA11_N +set_property -dict {PACKAGE_PIN W7 IOSTANDARD LVDS} [get_ports tx_data_out_0_p[2]] ; ## G15 FMC_HPC0_LA12_P +set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVDS} [get_ports tx_data_out_0_n[2]] ; ## G16 FMC_HPC0_LA12_N +set_property -dict {PACKAGE_PIN AB8 IOSTANDARD LVDS} [get_ports tx_data_out_0_p[3]] ; ## D17 FMC_HPC0_LA13_P +set_property -dict {PACKAGE_PIN AC8 IOSTANDARD LVDS} [get_ports tx_data_out_0_n[3]] ; ## D18 FMC_HPC0_LA13_N +set_property -dict {PACKAGE_PIN AC7 IOSTANDARD LVDS} [get_ports tx_data_out_0_p[4]] ; ## C18 FMC_HPC0_LA14_P +set_property -dict {PACKAGE_PIN AC6 IOSTANDARD LVDS} [get_ports tx_data_out_0_n[4]] ; ## C19 FMC_HPC0_LA14_N +set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVDS} [get_ports tx_data_out_0_p[5]] ; ## H19 FMC_HPC0_LA15_P +set_property -dict {PACKAGE_PIN Y9 IOSTANDARD LVDS} [get_ports tx_data_out_0_n[5]] ; ## H20 FMC_HPC0_LA15_N + +set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS18} [get_ports gpio_status_0[0]] ; ## H22 FMC_HPC0_LA19_P +set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS18} [get_ports gpio_status_0[1]] ; ## H23 FMC_HPC0_LA19_N +set_property -dict {PACKAGE_PIN N13 IOSTANDARD LVCMOS18} [get_ports gpio_status_0[2]] ; ## G21 FMC_HPC0_LA20_P +set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVCMOS18} [get_ports gpio_status_0[3]] ; ## G22 FMC_HPC0_LA20_N +set_property -dict {PACKAGE_PIN P12 IOSTANDARD LVCMOS18} [get_ports gpio_status_0[4]] ; ## H25 FMC_HPC0_LA21_P +set_property -dict {PACKAGE_PIN N12 IOSTANDARD LVCMOS18} [get_ports gpio_status_0[5]] ; ## H26 FMC_HPC0_LA21_N +set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS18} [get_ports gpio_status_0[6]] ; ## G24 FMC_HPC0_LA22_P +set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS18} [get_ports gpio_status_0[7]] ; ## G25 FMC_HPC0_LA22_N +set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS18} [get_ports gpio_ctl_0[0]] ; ## D23 FMC_HPC0_LA23_P +set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS18} [get_ports gpio_ctl_0[1]] ; ## D24 FMC_HPC0_LA23_N +set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVCMOS18} [get_ports gpio_ctl_0[2]] ; ## H28 FMC_HPC0_LA24_P +set_property -dict {PACKAGE_PIN K12 IOSTANDARD LVCMOS18} [get_ports gpio_ctl_0[3]] ; ## H29 FMC_HPC0_LA24_N +set_property -dict {PACKAGE_PIN M11 IOSTANDARD LVCMOS18} [get_ports gpio_en_agc_0] ; ## G27 FMC_HPC0_LA25_P +set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS18} [get_ports mcs_sync] ; ## C22 FMC_HPC0_LA18_CC_P +set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS18} [get_ports gpio_resetb_0] ; ## C23 FMC_HPC0_LA18_CC_N +set_property -dict {PACKAGE_PIN Y12 IOSTANDARD LVCMOS18} [get_ports enable_0] ; ## G18 FMC_HPC0_LA16_P +set_property -dict {PACKAGE_PIN AA12 IOSTANDARD LVCMOS18} [get_ports txnrx_0] ; ## G19 FMC_HPC0_LA16_N +set_property -dict {PACKAGE_PIN M10 IOSTANDARD LVCMOS18} [get_ports gpio_debug_1_0] ; ## C26 FMC_HPC0_LA27_P +set_property -dict {PACKAGE_PIN L10 IOSTANDARD LVCMOS18} [get_ports gpio_debug_2_0] ; ## C27 FMC_HPC0_LA27_N +set_property -dict {PACKAGE_PIN N9 IOSTANDARD LVCMOS18} [get_ports gpio_calsw_1_0] ; ## D26 FMC_HPC0_LA26_P +set_property -dict {PACKAGE_PIN N8 IOSTANDARD LVCMOS18} [get_ports gpio_calsw_2_0] ; ## D27 FMC_HPC0_LA26_N +set_property -dict {PACKAGE_PIN T7 IOSTANDARD LVCMOS18} [get_ports gpio_ad5355_rfen] ; ## H31 FMC_HPC0_LA28_P +set_property -dict {PACKAGE_PIN T6 IOSTANDARD LVCMOS18} [get_ports gpio_ad5355_lock] ; ## H37 FMC_HPC0_LA32_P + +# spi + +set_property -dict {PACKAGE_PIN U9 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports spi_ad9361_0] ; ## G30 FMC_HPC0_LA29_P +set_property -dict {PACKAGE_PIN U8 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports spi_ad9361_1] ; ## G31 FMC_HPC0_LA29_N +set_property -dict {PACKAGE_PIN V6 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports spi_ad5355] ; ## H34 FMC_HPC0_LA30_P +set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS18} [get_ports spi_clk] ; ## H35 FMC_HPC0_LA30_N +set_property -dict {PACKAGE_PIN V8 IOSTANDARD LVCMOS18} [get_ports spi_mosi] ; ## G33 FMC_HPC0_LA31_P +set_property -dict {PACKAGE_PIN V7 IOSTANDARD LVCMOS18} [get_ports spi_miso] ; ## G34 FMC_HPC0_LA31_N + +# ad9361 slave + +set_property -dict {PACKAGE_PIN AE5 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_clk_in_1_p] ; ## G06 FMC_HPC1_LA00_CC_P +set_property -dict {PACKAGE_PIN AF5 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_clk_in_1_n] ; ## G07 FMC_HPC1_LA00_CC_N +set_property -dict {PACKAGE_PIN AE2 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_frame_in_1_p] ; ## D08 FMC_HPC1_LA01_CC_P +set_property -dict {PACKAGE_PIN AE1 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_frame_in_1_n] ; ## D09 FMC_HPC1_LA01_CC_N +set_property -dict {PACKAGE_PIN AD2 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_1_p[0]] ; ## H07 FMC_HPC1_LA02_P +set_property -dict {PACKAGE_PIN AD1 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_1_n[0]] ; ## H08 FMC_HPC1_LA02_N +set_property -dict {PACKAGE_PIN AH1 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_1_p[1]] ; ## G09 FMC_HPC1_LA03_P +set_property -dict {PACKAGE_PIN AJ1 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_1_n[1]] ; ## G10 FMC_HPC1_LA03_N +set_property -dict {PACKAGE_PIN AF2 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_1_p[2]] ; ## H10 FMC_HPC1_LA04_P +set_property -dict {PACKAGE_PIN AF1 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_1_n[2]] ; ## H11 FMC_HPC1_LA04_N +set_property -dict {PACKAGE_PIN AG3 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_1_p[3]] ; ## D11 FMC_HPC1_LA05_P +set_property -dict {PACKAGE_PIN AH3 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_1_n[3]] ; ## D12 FMC_HPC1_LA05_N +set_property -dict {PACKAGE_PIN AH2 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_1_p[4]] ; ## C10 FMC_HPC1_LA06_P +set_property -dict {PACKAGE_PIN AJ2 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_1_n[4]] ; ## C11 FMC_HPC1_LA06_N +set_property -dict {PACKAGE_PIN AD4 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_1_p[5]] ; ## H13 FMC_HPC1_LA07_P +set_property -dict {PACKAGE_PIN AE4 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_1_n[5]] ; ## H14 FMC_HPC1_LA07_N +set_property -dict {PACKAGE_PIN AE3 IOSTANDARD LVDS} [get_ports tx_clk_out_1_p] ; ## G12 FMC_HPC1_LA08_P +set_property -dict {PACKAGE_PIN AF3 IOSTANDARD LVDS} [get_ports tx_clk_out_1_n] ; ## G13 FMC_HPC1_LA08_N +set_property -dict {PACKAGE_PIN AJ6 IOSTANDARD LVDS} [get_ports tx_frame_out_1_p] ; ## D14 FMC_HPC1_LA09_P +set_property -dict {PACKAGE_PIN AJ5 IOSTANDARD LVDS} [get_ports tx_frame_out_1_n] ; ## D15 FMC_HPC1_LA09_N +set_property -dict {PACKAGE_PIN AH4 IOSTANDARD LVDS} [get_ports tx_data_out_1_p[0]] ; ## C14 FMC_HPC1_LA10_P +set_property -dict {PACKAGE_PIN AJ4 IOSTANDARD LVDS} [get_ports tx_data_out_1_n[0]] ; ## C15 FMC_HPC1_LA10_N +set_property -dict {PACKAGE_PIN AE8 IOSTANDARD LVDS} [get_ports tx_data_out_1_p[1]] ; ## H16 FMC_HPC1_LA11_P +set_property -dict {PACKAGE_PIN AF8 IOSTANDARD LVDS} [get_ports tx_data_out_1_n[1]] ; ## H17 FMC_HPC1_LA11_N +set_property -dict {PACKAGE_PIN AD7 IOSTANDARD LVDS} [get_ports tx_data_out_1_p[2]] ; ## G15 FMC_HPC1_LA12_P +set_property -dict {PACKAGE_PIN AD6 IOSTANDARD LVDS} [get_ports tx_data_out_1_n[2]] ; ## G16 FMC_HPC1_LA12_N +set_property -dict {PACKAGE_PIN AG8 IOSTANDARD LVDS} [get_ports tx_data_out_1_p[3]] ; ## D17 FMC_HPC1_LA13_P +set_property -dict {PACKAGE_PIN AH8 IOSTANDARD LVDS} [get_ports tx_data_out_1_n[3]] ; ## D18 FMC_HPC1_LA13_N +set_property -dict {PACKAGE_PIN AH7 IOSTANDARD LVDS} [get_ports tx_data_out_1_p[4]] ; ## C18 FMC_HPC1_LA14_P +set_property -dict {PACKAGE_PIN AH6 IOSTANDARD LVDS} [get_ports tx_data_out_1_n[4]] ; ## C19 FMC_HPC1_LA14_N +set_property -dict {PACKAGE_PIN AD10 IOSTANDARD LVDS} [get_ports tx_data_out_1_p[5]] ; ## H19 FMC_HPC1_LA15_P +set_property -dict {PACKAGE_PIN AE9 IOSTANDARD LVDS} [get_ports tx_data_out_1_n[5]] ; ## H20 FMC_HPC1_LA15_N + +set_property -dict {PACKAGE_PIN AA11 IOSTANDARD LVCMOS18} [get_ports gpio_status_1[0]] ; ## H22 FMC_HPC1_LA19_P +set_property -dict {PACKAGE_PIN AA10 IOSTANDARD LVCMOS18} [get_ports gpio_status_1[1]] ; ## H23 FMC_HPC1_LA19_N +set_property -dict {PACKAGE_PIN AB11 IOSTANDARD LVCMOS18} [get_ports gpio_status_1[2]] ; ## G21 FMC_HPC1_LA20_P +set_property -dict {PACKAGE_PIN AB10 IOSTANDARD LVCMOS18} [get_ports gpio_status_1[3]] ; ## G22 FMC_HPC1_LA20_N +set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVCMOS18} [get_ports gpio_status_1[4]] ; ## H25 FMC_HPC1_LA21_P +set_property -dict {PACKAGE_PIN AC11 IOSTANDARD LVCMOS18} [get_ports gpio_status_1[5]] ; ## H26 FMC_HPC1_LA21_N +set_property -dict {PACKAGE_PIN AF11 IOSTANDARD LVCMOS18} [get_ports gpio_status_1[6]] ; ## G24 FMC_HPC1_LA22_P +set_property -dict {PACKAGE_PIN AG11 IOSTANDARD LVCMOS18} [get_ports gpio_status_1[7]] ; ## G25 FMC_HPC1_LA22_N +set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVCMOS18} [get_ports gpio_ctl_1[0]] ; ## D23 FMC_HPC1_LA23_P +set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVCMOS18} [get_ports gpio_ctl_1[1]] ; ## D24 FMC_HPC1_LA23_N +set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVCMOS18} [get_ports gpio_ctl_1[2]] ; ## H28 FMC_HPC1_LA24_P +set_property -dict {PACKAGE_PIN AH11 IOSTANDARD LVCMOS18} [get_ports gpio_ctl_1[3]] ; ## H29 FMC_HPC1_LA24_N +set_property -dict {PACKAGE_PIN AE10 IOSTANDARD LVCMOS18} [get_ports gpio_en_agc_1] ; ## G27 FMC_HPC1_LA25_P +set_property -dict {PACKAGE_PIN W12 IOSTANDARD LVCMOS18} [get_ports gpio_resetb_1] ; ## G30 FMC_HPC1_LA29_P +set_property -dict {PACKAGE_PIN AG10 IOSTANDARD LVCMOS18} [get_ports enable_1] ; ## G18 FMC_HPC1_LA16_P +set_property -dict {PACKAGE_PIN AG9 IOSTANDARD LVCMOS18} [get_ports txnrx_1] ; ## G19 FMC_HPC1_LA16_N +set_property -dict {PACKAGE_PIN U10 IOSTANDARD LVCMOS18} [get_ports gpio_debug_3_1] ; ## C26 FMC_HPC1_LA27_P +set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS18} [get_ports gpio_debug_4_1] ; ## C27 FMC_HPC1_LA27_N +set_property -dict {PACKAGE_PIN T12 IOSTANDARD LVCMOS18} [get_ports gpio_calsw_3_1] ; ## D26 FMC_HPC1_LA26_P +set_property -dict {PACKAGE_PIN R12 IOSTANDARD LVCMOS18} [get_ports gpio_calsw_4_1] ; ## D27 FMC_HPC1_LA26_N + +# clocks + +create_clock -name rx_0_clk -period 4.00 [get_ports rx_clk_in_0_p] +create_clock -name rx_1_clk -period 4.00 [get_ports rx_clk_in_1_p] +create_clock -name ad9361_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_ad9361_0/clk] diff --git a/projects/fmcomms5/zcu102/system_project.tcl b/projects/fmcomms5/zcu102/system_project.tcl new file mode 100644 index 000000000..053a7b985 --- /dev/null +++ b/projects/fmcomms5/zcu102/system_project.tcl @@ -0,0 +1,17 @@ + + + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +adi_project_create fmcomms5_zcu102 +adi_project_files fmcomms5_zcu102 [list \ + "system_top.v" \ + "system_constr.xdc"\ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ + "$ad_hdl_dir/projects/common/zcu102/zcu102_system_constr.xdc" ] + +adi_project_run fmcomms5_zcu102 + + diff --git a/projects/fmcomms5/zcu102/system_top.v b/projects/fmcomms5/zcu102/system_top.v new file mode 100644 index 000000000..5c665f94e --- /dev/null +++ b/projects/fmcomms5/zcu102/system_top.v @@ -0,0 +1,323 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + gpio_bd_i, + gpio_bd_o, + + rx_clk_in_0_p, + rx_clk_in_0_n, + rx_frame_in_0_p, + rx_frame_in_0_n, + rx_data_in_0_p, + rx_data_in_0_n, + tx_clk_out_0_p, + tx_clk_out_0_n, + tx_frame_out_0_p, + tx_frame_out_0_n, + tx_data_out_0_p, + tx_data_out_0_n, + gpio_status_0, + gpio_ctl_0, + gpio_en_agc_0, + mcs_sync, + gpio_resetb_0, + enable_0, + txnrx_0, + gpio_debug_1_0, + gpio_debug_2_0, + gpio_calsw_1_0, + gpio_calsw_2_0, + gpio_ad5355_rfen, + gpio_ad5355_lock, + + rx_clk_in_1_p, + rx_clk_in_1_n, + rx_frame_in_1_p, + rx_frame_in_1_n, + rx_data_in_1_p, + rx_data_in_1_n, + tx_clk_out_1_p, + tx_clk_out_1_n, + tx_frame_out_1_p, + tx_frame_out_1_n, + tx_data_out_1_p, + tx_data_out_1_n, + gpio_status_1, + gpio_ctl_1, + gpio_en_agc_1, + gpio_resetb_1, + enable_1, + txnrx_1, + gpio_debug_3_1, + gpio_debug_4_1, + gpio_calsw_3_1, + gpio_calsw_4_1, + + spi_ad9361_0, + spi_ad9361_1, + spi_ad5355, + spi_clk, + spi_mosi, + spi_miso, + + ref_clk_p, + ref_clk_n); + + input [12:0] gpio_bd_i; + output [ 7:0] gpio_bd_o; + + input rx_clk_in_0_p; + input rx_clk_in_0_n; + input rx_frame_in_0_p; + input rx_frame_in_0_n; + input [ 5:0] rx_data_in_0_p; + input [ 5:0] rx_data_in_0_n; + output tx_clk_out_0_p; + output tx_clk_out_0_n; + output tx_frame_out_0_p; + output tx_frame_out_0_n; + output [ 5:0] tx_data_out_0_p; + output [ 5:0] tx_data_out_0_n; + input [ 7:0] gpio_status_0; + output [ 3:0] gpio_ctl_0; + output gpio_en_agc_0; + output mcs_sync; + output gpio_resetb_0; + output enable_0; + output txnrx_0; + output gpio_debug_1_0; + output gpio_debug_2_0; + output gpio_calsw_1_0; + output gpio_calsw_2_0; + output gpio_ad5355_rfen; + input gpio_ad5355_lock; + + input rx_clk_in_1_p; + input rx_clk_in_1_n; + input rx_frame_in_1_p; + input rx_frame_in_1_n; + input [ 5:0] rx_data_in_1_p; + input [ 5:0] rx_data_in_1_n; + output tx_clk_out_1_p; + output tx_clk_out_1_n; + output tx_frame_out_1_p; + output tx_frame_out_1_n; + output [ 5:0] tx_data_out_1_p; + output [ 5:0] tx_data_out_1_n; + input [ 7:0] gpio_status_1; + output [ 3:0] gpio_ctl_1; + output gpio_en_agc_1; + output gpio_resetb_1; + output enable_1; + output txnrx_1; + output gpio_debug_3_1; + output gpio_debug_4_1; + output gpio_calsw_3_1; + output gpio_calsw_4_1; + + output spi_ad9361_0; + output spi_ad9361_1; + output spi_ad5355; + output spi_clk; + output spi_mosi; + input spi_miso; + + input ref_clk_p; + input ref_clk_n; + + // internal registers + + reg [ 2:0] mcs_sync_m = 'd0; + reg mcs_sync = 'd0; + + // internal signals + + wire sys_100m_resetn; + wire ref_clk_s; + wire ref_clk; + wire [ 94:0] gpio_i; + wire [ 94:0] gpio_o; + wire gpio_sync; + wire gpio_open_44_44; + wire gpio_open_15_15; + wire [ 2:0] spi0_csn; + wire spi0_clk; + wire spi0_mosi; + wire spi0_miso; + wire [ 2:0] spi1_csn; + wire spi1_clk; + wire spi1_mosi; + wire spi1_miso; + wire txnrx_0; + wire enable_0; + wire txnrx_1; + wire enable_1; + + // multi-chip synchronization + + always @(posedge ref_clk or negedge sys_100m_resetn) begin + if (sys_100m_resetn == 1'b0) begin + mcs_sync_m <= 3'd0; + mcs_sync <= 1'd0; + end else begin + mcs_sync_m <= {mcs_sync_m[1:0], gpio_sync}; + mcs_sync <= mcs_sync_m[2] & ~mcs_sync_m[1]; + end + end + + // instantiations + + IBUFGDS i_ref_clk_ibuf ( + .I (ref_clk_p), + .IB (ref_clk_n), + .O (ref_clk_s)); + + BUFR #(.BUFR_DIVIDE("BYPASS")) i_ref_clk_rbuf ( + .CLR (1'b0), + .CE (1'b1), + .I (ref_clk_s), + .O (ref_clk)); + + assign gpio_resetb_1 = gpio_o[65]; + assign gpio_i[64] = gpio_ad5355_lock; + assign gpio_ad5355_rfen = gpio_o[63]; + assign gpio_calsw_4_1 = gpio_o[62]; + assign gpio_calsw_3_1 = gpio_o[61]; + assign gpio_calsw_2_0 = gpio_o[60]; + assign gpio_calsw_1_0 = gpio_o[59]; + assign gpio_txnrx_1 = gpio_o[58]; + assign gpio_enable_1 = gpio_o[57]; + assign gpio_en_agc_1 = gpio_o[56]; + assign gpio_txnrx_0 = gpio_o[55]; + assign gpio_enable_0 = gpio_o[54]; + assign gpio_en_agc_0 = gpio_o[53]; + assign gpio_resetb_0 = gpio_o[52]; + assign gpio_sync = gpio_o[51]; + assign gpio_open_44_44 = gpio_o[50]; + assign gpio_debug_4_0 = gpio_o[49]; + assign gpio_debug_3_0 = gpio_o[48]; + assign gpio_debug_2_0 = gpio_o[47]; + assign gpio_debug_1_0 = gpio_o[46]; + assign gpio_ctl_1 = gpio_o[45:42]; + assign gpio_ctl_0 = gpio_o[41:38]; + assign gpio_i[37:30] = gpio_status_1; + assign gpio_i[29:22] = gpio_status_0; + assign gpio_open_15_15 = gpio_o[21]; + assign gpio_bd_o = gpio_o[20:13]; + assign gpio_i[12: 0] = gpio_bd_i; + + assign gpio_i[94:65] = gpio_o[94:65]; + assign gpio_i[63:38] = gpio_o[63:38]; + assign gpio_i[21:14] = gpio_o[21:14]; + + assign spi_ad9361_0 = spi0_csn[0]; + assign spi_ad9361_1 = spi0_csn[1]; + assign spi_ad5355 = spi0_csn[2]; + assign spi_clk = spi0_clk; + assign spi_mosi = spi0_mosi; + assign spi0_miso = spi_miso; + assign spi1_miso = 1'b0; + + system_wrapper i_system_wrapper ( + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .ps_intr_00 (1'b0), + .ps_intr_01 (1'b0), + .ps_intr_02 (1'b0), + .ps_intr_03 (1'b0), + .ps_intr_04 (1'b0), + .ps_intr_05 (1'b0), + .ps_intr_06 (1'b0), + .ps_intr_07 (1'b0), + .ps_intr_08 (1'b0), + .ps_intr_09 (1'b0), + .ps_intr_10 (1'b0), + .ps_intr_11 (1'b0), + .ps_intr_14 (1'b0), + .ps_intr_15 (1'b0), + .rx_clk_in_0_n (rx_clk_in_0_n), + .rx_clk_in_0_p (rx_clk_in_0_p), + .rx_clk_in_1_n (rx_clk_in_1_n), + .rx_clk_in_1_p (rx_clk_in_1_p), + .rx_data_in_0_n (rx_data_in_0_n), + .rx_data_in_0_p (rx_data_in_0_p), + .rx_data_in_1_n (rx_data_in_1_n), + .rx_data_in_1_p (rx_data_in_1_p), + .rx_frame_in_0_n (rx_frame_in_0_n), + .rx_frame_in_0_p (rx_frame_in_0_p), + .rx_frame_in_1_n (rx_frame_in_1_n), + .rx_frame_in_1_p (rx_frame_in_1_p), + .spi0_csn (spi0_csn), + .spi0_miso (spi0_miso), + .spi0_mosi (spi0_mosi), + .spi0_sclk (spi0_clk), + .spi1_csn (spi1_csn), + .spi1_miso (spi1_miso), + .spi1_mosi (spi1_mosi), + .spi1_sclk (spi1_clk), + .sys_100m_resetn (sys_100m_resetn), + .tx_clk_out_0_n (tx_clk_out_0_n), + .tx_clk_out_0_p (tx_clk_out_0_p), + .tx_clk_out_1_n (tx_clk_out_1_n), + .tx_clk_out_1_p (tx_clk_out_1_p), + .tx_data_out_0_n (tx_data_out_0_n), + .tx_data_out_0_p (tx_data_out_0_p), + .tx_data_out_1_n (tx_data_out_1_n), + .tx_data_out_1_p (tx_data_out_1_p), + .tx_frame_out_0_n (tx_frame_out_0_n), + .tx_frame_out_0_p (tx_frame_out_0_p), + .tx_frame_out_1_n (tx_frame_out_1_n), + .tx_frame_out_1_p (tx_frame_out_1_p), + .txnrx_0 (txnrx_0), + .enable_0 (enable_0), + .up_enable_0 (gpio_enable_0), + .up_txnrx_0 (gpio_txnrx_0), + .txnrx_1 (txnrx_1), + .enable_1 (enable_1), + .up_enable_1 (gpio_enable_1), + .up_txnrx_1 (gpio_txnrx_1)); + +endmodule + +// *************************************************************************** +// ***************************************************************************