axi_adc_trigger: Add cascade support.
- Add embedded trigger as an option. The use of the embedded trigger as an option in the data stream is done for further processing, keeping the data synchronized with the trigger. When instrument (module) trigger is desired (logic_analyzer - adc_trigger), a small propagation time is required, hence the need to remove the util_extract(trigger extract) module from the data path. - Add more options for the IO triggering. This will open the door for multiple M2k synchronization(triggering). trigger_o mux: 1 - trigger flag (from regmap) 2 - external pin trigger (Ti) 3 - external pin trigger (To) 4 - internal adc trigger 5 - logic analyzer trigger The signal passed to trigger_o must not be delayed, but the new value has to be kept for a short period, 1ms (100000 clock cycles), to reduce switch noises in the system. The axi_adc_trigger handles 3 output triggers: - trigger_o - external trigger (1 clock cycle delay) - trigger_out - signals on dmac/fifo_wr_sync the start of a new transfer. A variable fifo depth is present in the data path, which delays the data arriving at the DMA with 3 clock cycles. By coincidence, the external trigger is synchronized and detected on 3 clock cycles. To get a maximum optimization the trigger_out will be delayed with 3 clock cycles for internal triggers and directly forwarded in the case of an external trigger. - trigger_out_la (cascade trigger for logic_analyzer - m2k example) Because the trigger_out_la must have a small delay, to get a realible instrument triggering mechanism, a 1 delay clock cycle must be added on the trigger paths, to avoid creating a closed combinatorial loop. Increase pcore version. The major version 3 is used to describe the instrument trigger updates.main
AndreiGrozav
AndreiGrozav
parent
baacc906a6
commit
b5dfdcfb84
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@ -45,8 +45,10 @@ module axi_adc_trigger #(
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input clk,
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input trigger_in,
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input [ 1:0] trigger_i,
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output [ 1:0] trigger_o,
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output reg [ 1:0] trigger_o,
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output [ 1:0] trigger_t,
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input [15:0] data_a,
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@ -58,6 +60,8 @@ module axi_adc_trigger #(
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output [15:0] data_b_trig,
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output data_valid_a_trig,
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output data_valid_b_trig,
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output reg trigger_out,
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output reg trigger_out_la,
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output [31:0] fifo_depth,
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@ -101,7 +105,7 @@ module axi_adc_trigger #(
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wire up_rreq;
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wire [ 4:0] up_raddr;
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wire [ 1:0] io_selection;
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wire [ 7:0] io_selection;
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wire [ 1:0] low_level;
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wire [ 1:0] high_level;
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@ -119,7 +123,7 @@ module axi_adc_trigger #(
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wire [31:0] hysteresis_b;
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wire [ 3:0] trigger_l_mix_b;
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wire [ 2:0] trigger_out_mix;
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wire [16:0] trigger_out_control;
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wire [31:0] trigger_delay;
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wire signed [DW:0] data_a_cmp;
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@ -140,7 +144,11 @@ module axi_adc_trigger #(
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wire trigger_a_any_edge;
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wire trigger_b_any_edge;
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wire trigger_out_delayed;
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wire [ 1:0] trigger_up_o_s;
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wire streaming;
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wire trigger_out_s;
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wire embedded_trigger;
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wire external_trigger;
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reg trigger_a_d1; // synchronization flip flop
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reg trigger_a_d2; // synchronization flip flop
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@ -163,6 +171,13 @@ module axi_adc_trigger #(
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reg trigger_pin_a;
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reg trigger_pin_b;
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reg [ 1:0] trigger_o_m;
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reg [ 1:0] trigger_o_m_1;
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reg trig_o_hold_0;
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reg trig_o_hold_1;
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reg [16:0] trig_o_hold_cnt_0;
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reg [16:0] trig_o_hold_cnt_1;
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reg trigger_adc_a;
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reg trigger_adc_b;
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@ -180,13 +195,9 @@ module axi_adc_trigger #(
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reg up_triggered_reset_d1;
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reg up_triggered_reset_d2;
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reg [14:0] data_a_r;
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reg [14:0] data_b_r;
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reg data_valid_a_r;
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reg data_valid_b_r;
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reg [31:0] trigger_delay_counter;
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reg triggered;
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reg trigger_out_m1;
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reg streaming_on;
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@ -195,7 +206,7 @@ module axi_adc_trigger #(
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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assign trigger_t = io_selection;
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assign trigger_t = io_selection[1:0];
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assign trigger_a_fall_edge = (trigger_a_d2 == 1'b0 && trigger_a_d3 == 1'b1) ? 1'b1: 1'b0;
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assign trigger_a_rise_edge = (trigger_a_d2 == 1'b1 && trigger_a_d3 == 1'b0) ? 1'b1: 1'b0;
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@ -209,10 +220,76 @@ module axi_adc_trigger #(
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assign limit_a_cmp = limit_a[DW:0];
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assign limit_b_cmp = limit_b[DW:0];
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assign data_a_trig = trigger_delay == 32'h0 ? {trigger_out_mixed | streaming_on, data_a_r} : {trigger_out_delayed |streaming_on, data_a_r};
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assign data_b_trig = trigger_delay == 32'h0 ? {trigger_out_mixed | streaming_on, data_b_r} : {trigger_out_delayed |streaming_on, data_b_r};
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assign data_valid_a_trig = data_valid_a_r;
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assign data_valid_b_trig = data_valid_b_r;
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always @(*) begin
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case(io_selection[4:2])
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3'h0: trigger_o_m[0] = trigger_up_o_s[0];
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3'h1: trigger_o_m[0] = trigger_i[0];
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3'h2: trigger_o_m[0] = trigger_i[1];
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3'h3: trigger_o_m[0] = trigger_out_mixed;
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3'h4: trigger_o_m[0] = trigger_in;
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default: trigger_o_m[0] = trigger_up_o_s[0];
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endcase
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case(io_selection[7:5])
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3'h0: trigger_o_m[1] = trigger_up_o_s[1];
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3'h1: trigger_o_m[1] = trigger_i[1];
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3'h2: trigger_o_m[1] = trigger_i[0];
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3'h3: trigger_o_m[1] = trigger_out_mixed;
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3'h4: trigger_o_m[1] = trigger_in;
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default: trigger_o_m[1] = trigger_up_o_s[1];
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endcase
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end
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// External trigger output hold 100000 clock cycles(1ms) on polarity change.
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// All trigger signals that are to be outputted on the external trigger after a
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// trigger out is acknowledged by the hold counter will be disregarded for 1ms.
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// This was done to avoid noise created by high frequency switches on long
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// wires.
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always @(posedge clk) begin
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// trigger_o[0] hold start
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if ((trigger_o_m[0] != trigger_o_m_1[0]) & (trig_o_hold_cnt_0 == 17'd0)) begin
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trig_o_hold_cnt_0 <= 17'd100000;
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trig_o_hold_0 <= trigger_o_m[0];
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end
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if (trig_o_hold_cnt_0 != 17'd0) begin
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trig_o_hold_cnt_0 <= trig_o_hold_cnt_0 - 17'd1;
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end
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trigger_o_m_1[0] <= trigger_o_m[0];
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// trigger_o[1] hold start
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if ((trigger_o_m[1] != trigger_o_m_1[1]) & (trig_o_hold_cnt_1 == 17'd0)) begin
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trig_o_hold_cnt_1 <= 17'd100000;
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trig_o_hold_1 <= trigger_o_m[1];
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end
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if (trig_o_hold_cnt_1 != 17'd0) begin
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trig_o_hold_cnt_1 <= trig_o_hold_cnt_1 - 17'd1;
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end
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trigger_o_m_1[1] <= trigger_o_m[1];
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// hold
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trigger_o[0] <= (trig_o_hold_cnt_0 == 'd0) ? trigger_o_m[0] : trig_o_hold_0;
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trigger_o[1] <= (trig_o_hold_cnt_1 == 'd0) ? trigger_o_m[1] : trig_o_hold_1;
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end
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// - keep data in sync with the trigger. The trigger bypasses the variable fifo.
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// The data goes through and it is delayed with 4 clock cycles)
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always @(posedge clk) begin
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trigger_out_m1 <= trigger_out_s;
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trigger_out <= trigger_out_m1;
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// triggers logic analyzer
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trigger_out_la <= trigger_out_mixed;
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end
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// the embedded trigger does not require any extra delay, since the util_extract
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// present in this case, delays the trigger with 2 clock cycles
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assign data_a_trig = (embedded_trigger == 1'h0) ? {data_a[14],data_a[14:0]} : {trigger_out_s,data_a[14:0]};
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assign data_b_trig = (embedded_trigger == 1'h0) ? {data_b[14],data_b[14:0]} : {trigger_out_s,data_b[14:0]};
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assign embedded_trigger = trigger_out_control[16];
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assign trigger_out_s = (trigger_delay == 32'h0) ? (trigger_out_mixed | streaming_on) :
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(trigger_out_delayed | streaming_on);
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assign data_valid_a_trig = data_valid_a;
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assign data_valid_b_trig = data_valid_b;
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assign trigger_out_delayed = (trigger_delay_counter == 32'h0) ? 1 : 0;
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@ -220,7 +297,7 @@ module axi_adc_trigger #(
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if (trigger_delay == 0) begin
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trigger_delay_counter <= 32'h0;
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end else begin
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if (data_valid_a_r == 1'b1) begin
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if (data_valid_a == 1'b1) begin
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triggered <= trigger_out_mixed | triggered;
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if (trigger_delay_counter == 0) begin
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trigger_delay_counter <= trigger_delay;
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@ -236,13 +313,13 @@ module axi_adc_trigger #(
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always @(posedge clk) begin
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if (trigger_delay == 0) begin
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if (streaming == 1'b1 && data_valid_a_r == 1'b1 && trigger_out_mixed == 1'b1) begin
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if (streaming == 1'b1 && data_valid_a == 1'b1 && trigger_out_mixed == 1'b1) begin
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streaming_on <= 1'b1;
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end else if (streaming == 1'b0) begin
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streaming_on <= 1'b0;
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end
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end else begin
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if (streaming == 1'b1 && data_valid_a_r == 1'b1 && trigger_out_delayed == 1'b1) begin
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if (streaming == 1'b1 && data_valid_a == 1'b1 && trigger_out_delayed == 1'b1) begin
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streaming_on <= 1'b1;
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end else if (streaming == 1'b0) begin
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streaming_on <= 1'b0;
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@ -251,7 +328,7 @@ module axi_adc_trigger #(
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end
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always @(posedge clk) begin
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if (data_valid_a_r == 1'b1 && trigger_out_mixed == 1'b1) begin
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if (data_valid_a == 1'b1 && trigger_out_mixed == 1'b1) begin
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up_triggered_set <= 1'b1;
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end else if (up_triggered_reset == 1'b1) begin
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up_triggered_set <= 1'b0;
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@ -267,13 +344,6 @@ module axi_adc_trigger #(
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up_triggered <= up_triggered_d2;
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end
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always @(posedge clk) begin
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data_a_r <= data_a[14:0];
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data_valid_a_r <= data_valid_a;
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data_b_r <= data_b[14:0];
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data_valid_b_r <= data_valid_b;
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end
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always @(*) begin
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case(trigger_l_mix_a)
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4'h0: trigger_a = 1'b1;
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@ -350,12 +420,16 @@ module axi_adc_trigger #(
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end
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always @(*) begin
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case(trigger_out_mix)
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3'h0: trigger_out_mixed = trigger_a;
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3'h1: trigger_out_mixed = trigger_b;
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3'h2: trigger_out_mixed = trigger_a | trigger_b;
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3'h3: trigger_out_mixed = trigger_a & trigger_b;
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3'h4: trigger_out_mixed = trigger_a ^ trigger_b;
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case(trigger_out_control[3:0])
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4'h0: trigger_out_mixed = trigger_a;
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4'h1: trigger_out_mixed = trigger_b;
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4'h2: trigger_out_mixed = trigger_a | trigger_b;
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4'h3: trigger_out_mixed = trigger_a & trigger_b;
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4'h4: trigger_out_mixed = trigger_a ^ trigger_b;
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4'h5: trigger_out_mixed = trigger_in;
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4'h6: trigger_out_mixed = trigger_a | trigger_in;
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4'h7: trigger_out_mixed = trigger_b | trigger_in;
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4'h8: trigger_out_mixed = trigger_a | trigger_b | trigger_in;
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default: trigger_out_mixed = trigger_a;
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endcase
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end
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@ -417,7 +491,7 @@ module axi_adc_trigger #(
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.clk(clk),
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.io_selection(io_selection),
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.trigger_o(trigger_o),
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.trigger_o(trigger_up_o_s),
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.triggered(up_triggered),
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.low_level(low_level),
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@ -436,8 +510,9 @@ module axi_adc_trigger #(
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.hysteresis_b(hysteresis_b),
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.trigger_l_mix_b(trigger_l_mix_b),
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.trigger_out_mix(trigger_out_mix),
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.trigger_out_control(trigger_out_control),
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.trigger_delay(trigger_delay),
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.fifo_depth(fifo_depth),
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.streaming(streaming),
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@ -39,8 +39,8 @@ module axi_adc_trigger_reg (
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input clk,
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output reg [ 1:0] io_selection,
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output reg [ 1:0] trigger_o,
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output [ 7:0] io_selection,
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output [ 1:0] trigger_o,
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input triggered,
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output [ 1:0] low_level,
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@ -59,9 +59,10 @@ module axi_adc_trigger_reg (
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output [31:0] hysteresis_b,
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output [ 3:0] trigger_l_mix_b,
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output [ 2:0] trigger_out_mix,
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output [16:0] trigger_out_control,
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output [31:0] fifo_depth,
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output [31:0] trigger_delay,
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output streaming,
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// bus interface
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@ -79,40 +80,42 @@ module axi_adc_trigger_reg (
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// internal signals
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wire [ 9:0] config_trigger;
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wire [ 9:0] config_trigger_i;
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// internal registers
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reg [31:0] up_version = 32'h00010000;
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reg [31:0] up_version = 32'h00030000;
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reg [31:0] up_scratch = 32'h0;
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reg [ 9:0] up_config_trigger = 10'h0;
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reg [ 7:0] up_io_selection = 8'h0;
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reg [ 1:0] up_trigger_o = 2'h0;
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reg [ 9:0] up_config_trigger_i = 10'h0;
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reg [15:0] up_limit_a = 16'h0;
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reg [ 1:0] up_function_a = 2'h0;
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reg [31:0] up_hysteresis_a = 32'h0;
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reg [ 3:0] up_trigger_l_mix_a = 32'h0;
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reg [ 3:0] up_trigger_l_mix_a = 4'h0;
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reg [15:0] up_limit_b = 16'h0;
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reg [ 1:0] up_function_b = 2'h0;
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reg [31:0] up_hysteresis_b = 32'h0;
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reg [ 3:0] up_trigger_l_mix_b = 32'h0;
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reg [ 2:0] up_trigger_out_mix = 32'h0;
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reg [ 3:0] up_trigger_l_mix_b = 4'h0;
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reg [16:0] up_trigger_out_control = 17'h0;
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reg [31:0] up_fifo_depth = 32'h0;
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reg [31:0] up_trigger_delay = 32'h0;
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reg up_triggered = 1'h0;
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reg up_streaming = 1'h0;
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assign low_level = config_trigger[1:0];
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assign high_level = config_trigger[3:2];
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assign any_edge = config_trigger[5:4];
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assign rise_edge = config_trigger[7:6];
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assign fall_edge = config_trigger[9:8];
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assign low_level = config_trigger_i[1:0];
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assign high_level = config_trigger_i[3:2];
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assign any_edge = config_trigger_i[5:4];
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assign rise_edge = config_trigger_i[7:6];
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assign fall_edge = config_trigger_i[9:8];
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_wack <= 'd0;
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up_scratch <= 'd0;
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io_selection <= 'd3;
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trigger_o <= 'd0;
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up_config_trigger <= 'd0;
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up_trigger_o <= 'd0;
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up_io_selection <= 'd1;
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up_config_trigger_i <= 'd0;
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up_limit_a <= 'd0;
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up_function_a <= 'd0;
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up_hysteresis_a <= 'd0;
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@ -123,7 +126,7 @@ module axi_adc_trigger_reg (
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up_trigger_delay <= 'd0;
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up_trigger_l_mix_a <= 'd0;
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up_trigger_l_mix_b <= 'd0;
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up_trigger_out_mix <= 'd0;
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up_trigger_out_control <= 'd0;
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up_triggered <= 1'd0;
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up_streaming <= 1'd0;
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end else begin
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@ -132,13 +135,13 @@ module axi_adc_trigger_reg (
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up_scratch <= up_wdata;
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end
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h2)) begin
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trigger_o <= up_wdata[1:0];
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up_trigger_o <= up_wdata[1:0];
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end
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h3)) begin
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io_selection <= up_wdata[1:0];
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up_io_selection <= up_wdata[7:0];
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end
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h4)) begin
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up_config_trigger <= up_wdata[9:0];
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up_config_trigger_i <= up_wdata[9:0];
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end
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h5)) begin
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up_limit_a <= up_wdata[15:0];
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@ -165,7 +168,7 @@ module axi_adc_trigger_reg (
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up_trigger_l_mix_b <= up_wdata[3:0];
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end
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'hd)) begin
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up_trigger_out_mix <= up_wdata[2:0];
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up_trigger_out_control <= up_wdata[16:0];
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end
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'he)) begin
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up_fifo_depth <= up_wdata;
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@ -196,9 +199,9 @@ module axi_adc_trigger_reg (
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case (up_raddr[4:0])
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5'h0: up_rdata <= up_version;
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5'h1: up_rdata <= up_scratch;
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5'h2: up_rdata <= {30'h0,trigger_o};
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5'h3: up_rdata <= {30'h0,io_selection};
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5'h4: up_rdata <= {22'h0,up_config_trigger};
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5'h2: up_rdata <= {30'h0,up_trigger_o};
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5'h3: up_rdata <= {24'h0,up_io_selection};
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5'h4: up_rdata <= {22'h0,up_config_trigger_i};
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5'h5: up_rdata <= {16'h0,up_limit_a};
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5'h6: up_rdata <= {30'h0,up_function_a};
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5'h7: up_rdata <= up_hysteresis_a;
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@ -207,7 +210,7 @@ module axi_adc_trigger_reg (
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5'ha: up_rdata <= {30'h0,up_function_b};
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5'hb: up_rdata <= up_hysteresis_b;
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5'hc: up_rdata <= {28'h0,up_trigger_l_mix_b};
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5'hd: up_rdata <= {29'h0,up_trigger_out_mix};
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5'hd: up_rdata <= {15'h0,up_trigger_out_control};
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5'he: up_rdata <= up_fifo_depth;
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5'hf: up_rdata <= {31'h0,up_triggered};
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5'h10: up_rdata <= up_trigger_delay;
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@ -220,28 +223,32 @@ module axi_adc_trigger_reg (
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end
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end
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up_xfer_cntrl #(.DATA_WIDTH(186)) i_xfer_cntrl (
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up_xfer_cntrl #(.DATA_WIDTH(210)) i_xfer_cntrl (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_data_cntrl ({ up_streaming, // 1
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up_config_trigger, // 10
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up_limit_a, // 16
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up_function_a, // 2
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up_hysteresis_a, // 32
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up_trigger_l_mix_a, // 4
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up_limit_b, // 16
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up_function_b, // 2
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up_hysteresis_b, // 32
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||||
up_trigger_l_mix_b, // 4
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up_trigger_out_mix, // 3
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up_fifo_depth, // 32
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||||
up_trigger_delay}), // 32
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||||
.up_data_cntrl ({ up_streaming, // 1
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up_trigger_o, // 2
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up_io_selection, // 8
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||||
up_config_trigger_i, // 10
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||||
up_limit_a, // 16
|
||||
up_function_a, // 2
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||||
up_hysteresis_a, // 32
|
||||
up_trigger_l_mix_a, // 4
|
||||
up_limit_b, // 16
|
||||
up_function_b, // 2
|
||||
up_hysteresis_b, // 32
|
||||
up_trigger_l_mix_b, // 4
|
||||
up_trigger_out_control, // 17
|
||||
up_fifo_depth, // 32
|
||||
up_trigger_delay}), // 32
|
||||
|
||||
.up_xfer_done (),
|
||||
.d_rst (1'b0),
|
||||
.d_clk (clk),
|
||||
.d_data_cntrl ({ streaming, // 1
|
||||
config_trigger, // 10
|
||||
trigger_o, // 2
|
||||
io_selection, // 8
|
||||
config_trigger_i, // 10
|
||||
limit_a, // 16
|
||||
function_a, // 2
|
||||
hysteresis_a, // 32
|
||||
|
|
@ -250,7 +257,7 @@ module axi_adc_trigger_reg (
|
|||
function_b, // 2
|
||||
hysteresis_b, // 32
|
||||
trigger_l_mix_b, // 4
|
||||
trigger_out_mix, // 3
|
||||
trigger_out_control,// 17
|
||||
fifo_depth, // 32
|
||||
trigger_delay})); // 32
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue