From b5552181529c488ca94dd244814a7d39ce058712 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Wed, 11 Apr 2018 14:01:48 +0200 Subject: [PATCH] util_dacfifo: Fix Quartus warnings Fix the following warnings that are generated by Quartus: Warning (10236): Verilog HDL Implicit Net warning at util_dacfifo.v(257): created implicit net for "dac_mem_ren_s" Warning (10230): Verilog HDL assignment warning at util_dacfifo.v(166): truncated value with size 32 to match size of target (10) Warning (10230): Verilog HDL assignment warning at util_dacfifo.v(266): truncated value with size 32 to match size of target (10) Warning (10230): Verilog HDL assignment warning at util_dacfifo.v(268): truncated value with size 32 to match size of target (10) No functional changes. Signed-off-by: Lars-Peter Clausen --- library/util_dacfifo/util_dacfifo.v | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/library/util_dacfifo/util_dacfifo.v b/library/util_dacfifo/util_dacfifo.v index 7e302917c..62a0e5e36 100644 --- a/library/util_dacfifo/util_dacfifo.v +++ b/library/util_dacfifo/util_dacfifo.v @@ -108,6 +108,7 @@ module util_dacfifo #( wire [(ADDRESS_WIDTH-1):0] dma_raddr_g2b_s; wire [(ADDRESS_WIDTH-1):0] dac_waddr_g2b_s; wire [(ADDRESS_WIDTH-1):0] dac_lastaddr_g2b_s; + wire dac_mem_ren_s; // DMA / Write interface @@ -163,7 +164,7 @@ module util_dacfifo #( dma_xfer_out_bypass <= 1'b0; end else begin if (dma_wren_s == 1'b1) begin - dma_waddr <= dma_waddr + 1; + dma_waddr <= dma_waddr + 1'b1; dma_xfer_out_fifo <= 1'b0; end if (dma_xfer_last == 1'b1) begin @@ -262,10 +263,10 @@ module util_dacfifo #( dac_raddr_g <= 'b0; end else begin if (dac_mem_ren_s == 1'b1) begin - if (dac_lastaddr == 'b0) begin - dac_raddr <= dac_raddr + 1; + if (dac_lastaddr == 'b0 || dac_raddr < dac_lastaddr) begin + dac_raddr <= dac_raddr + 1'b1; end else begin - dac_raddr <= (dac_raddr < dac_lastaddr) ? (dac_raddr + 1) : 'b0; + dac_raddr <= 'b0; end end dac_raddr_g <= dac_raddr_b2g_s;