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ad_ip_jesd204_tpl_adc: Refactor external sync 

- Add EXT_SYNC option
- Gate valid while in reset
main
Laszlo Nagy 2022-01-27 11:39:54 +00:00 committed by Laszlo Nagy
parent 8c7cca4277
commit b5092662d5
5 changed files with 51 additions and 20 deletions
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1
library/jesd204/ad_ip_jesd204_tpl_adc/Makefile
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@ -17,6 +17,7 @@ GENERIC_DEPS += ../../common/up_axi.v
GENERIC_DEPS += ../../common/up_clock_mon.v
GENERIC_DEPS += ../../common/up_xfer_cntrl.v
GENERIC_DEPS += ../../common/up_xfer_status.v
GENERIC_DEPS += ../../common/util_ext_sync.v
GENERIC_DEPS += ad_ip_jesd204_tpl_adc.v
GENERIC_DEPS += ad_ip_jesd204_tpl_adc_channel.v
GENERIC_DEPS += ad_ip_jesd204_tpl_adc_core.v

19
library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.v
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@ -37,7 +37,8 @@ module ad_ip_jesd204_tpl_adc #(
parameter DMA_BITS_PER_SAMPLE = 16,
parameter OCTETS_PER_BEAT = 4,
parameter EN_FRAME_ALIGN = 1,
parameter TWOS_COMPLEMENT = 1
parameter TWOS_COMPLEMENT = 1,
parameter EXT_SYNC = 0
) (
// jesd interface
// link_clk is (line-rate/40)
@ -57,6 +58,9 @@ module ad_ip_jesd204_tpl_adc #(
input adc_dovf,
input adc_sync_in,
output adc_sync_manual_req_out,
input adc_sync_manual_req_in,
output adc_rst,
// axi interface
@ -120,7 +124,8 @@ module ad_ip_jesd204_tpl_adc #(
.DEV_PACKAGE (DEV_PACKAGE),
.NUM_CHANNELS (NUM_CHANNELS),
.DATA_PATH_WIDTH (DATA_PATH_WIDTH),
.NUM_PROFILES(1)
.NUM_PROFILES(1),
.EXT_SYNC (EXT_SYNC)
) i_regmap (
.s_axi_aclk (s_axi_aclk),
.s_axi_aresetn (s_axi_aresetn),
@ -158,6 +163,9 @@ module ad_ip_jesd204_tpl_adc #(
.adc_sync (adc_sync),
.adc_sync_status (adc_sync_status),
.adc_ext_sync_arm (adc_ext_sync_arm),
.adc_ext_sync_disarm (adc_ext_sync_disarm),
.adc_ext_sync_manual_req (adc_sync_manual_req_out),
.adc_rst (adc_rst_s),
@ -184,7 +192,8 @@ module ad_ip_jesd204_tpl_adc #(
.DMA_DATA_WIDTH (DMA_DATA_WIDTH),
.TWOS_COMPLEMENT (TWOS_COMPLEMENT),
.DATA_PATH_WIDTH (DATA_PATH_WIDTH),
.DMA_BITS_PER_SAMPLE (DMA_BITS_PER_SAMPLE)
.DMA_BITS_PER_SAMPLE (DMA_BITS_PER_SAMPLE),
.EXT_SYNC (EXT_SYNC)
) i_core (
.clk (link_clk),
@ -204,8 +213,12 @@ module ad_ip_jesd204_tpl_adc #(
.adc_sync (adc_sync),
.adc_sync_status (adc_sync_status),
.adc_sync_in (adc_sync_in),
.adc_ext_sync_arm (adc_ext_sync_arm),
.adc_ext_sync_disarm (adc_ext_sync_disarm),
.adc_sync_manual_req (adc_sync_manual_req_in),
.adc_rst_sync (adc_rst_sync_s),
.adc_valid (adc_valid),
.adc_data (adc_data)
);

30
library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_core.v
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@ -35,7 +35,8 @@ module ad_ip_jesd204_tpl_adc_core #(
parameter DATA_PATH_WIDTH = 1,
parameter LINK_DATA_WIDTH = NUM_LANES * OCTETS_PER_BEAT * 8,
parameter DMA_DATA_WIDTH = DATA_PATH_WIDTH * DMA_BITS_PER_SAMPLE * NUM_CHANNELS,
parameter TWOS_COMPLEMENT = 1
parameter TWOS_COMPLEMENT = 1,
parameter EXT_SYNC = 0
) (
input clk,
@ -52,7 +53,10 @@ module ad_ip_jesd204_tpl_adc_core #(
input adc_sync,
output adc_sync_status,
input adc_ext_sync_arm,
input adc_ext_sync_disarm,
input adc_sync_in,
input adc_sync_manual_req,
output adc_rst_sync,
input link_valid,
@ -68,14 +72,11 @@ module ad_ip_jesd204_tpl_adc_core #(
wire [ADC_DATA_WIDTH-1:0] raw_data_s;
wire link_valid_tmp;
reg adc_sync_armed = 1'b0;
reg adc_sync_in_d1 = 1'b0;
reg adc_sync_d1 = 1'b0;
reg link_valid_d = 1'b0;
assign link_ready = 1'b1;
assign link_valid_tmp = EN_FRAME_ALIGN ? link_valid_d : link_valid;
assign adc_valid = {NUM_CHANNELS{link_valid_tmp}};
assign adc_valid = {NUM_CHANNELS{link_valid_tmp & ~adc_sync_armed}};
assign adc_sync_status = adc_sync_armed;
assign adc_rst_sync = adc_sync_armed;
@ -83,17 +84,16 @@ module ad_ip_jesd204_tpl_adc_core #(
link_valid_d <= link_valid;
end
always @(posedge clk) begin
adc_sync_in_d1 <= adc_sync_in;
adc_sync_d1 <= adc_sync;
if ((~adc_sync_d1 & adc_sync) == 1'b1) begin
adc_sync_armed <= ~adc_sync_armed;
end else if ((~adc_sync_in_d1 & adc_sync_in) == 1'b1) begin
adc_sync_armed <= 1'b0;
end
end
// synchronization logic
util_ext_sync #(
.ENABLED (EXT_SYNC)
) i_util_ext_sync (
.clk (clk),
.ext_sync_arm (adc_ext_sync_arm),
.ext_sync_disarm (adc_ext_sync_disarm),
.sync_in (adc_sync_in | adc_sync_manual_req),
.sync_armed (adc_sync_armed)
);
ad_ip_jesd204_tpl_adc_deframer #(
.NUM_LANES (NUM_LANES),

6
library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_ip.tcl
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@ -36,6 +36,7 @@ adi_ip_files ad_ip_jesd204_tpl_adc [list \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"$ad_hdl_dir/library/common/util_ext_sync.v" \
"$ad_hdl_dir/library/common/ad_xcvr_rx_if.v" \
"$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
@ -72,6 +73,10 @@ adi_add_bus "link" "master" \
]
adi_add_bus_clock "link_clk" "link"
adi_set_ports_dependency "adc_sync_in" "EXT_SYNC == 1"
adi_set_ports_dependency "adc_sync_manual_req_out" "EXT_SYNC == 1"
adi_set_ports_dependency "adc_sync_manual_req_in" "EXT_SYNC == 1"
foreach {p v} {
"NUM_LANES" "1 2 3 4 6 8 12 16" \
"NUM_CHANNELS" "1 2 4 6 8 16 32 64" \
@ -128,6 +133,7 @@ set i 0
foreach {k v w} {
"TWOS_COMPLEMENT" "Use twos complement" "checkBox" \
"EXT_SYNC" "Enable external sync" "checkBox" \
} { \
set p [ipgui::get_guiparamspec -name $k -component $cc]
ipgui::move_param -component $cc -order $i $p -parent $datapath_group

15
library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v
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@ -31,7 +31,8 @@ module ad_ip_jesd204_tpl_adc_regmap #(
parameter DEV_PACKAGE = 0,
parameter NUM_CHANNELS = 1,
parameter DATA_PATH_WIDTH = 1,
parameter NUM_PROFILES = 1 // Number of supported JESD profiles
parameter NUM_PROFILES = 1, // Number of supported JESD profiles
parameter EXT_SYNC = 0
) (
// axi interface
input s_axi_aclk,
@ -73,6 +74,9 @@ module ad_ip_jesd204_tpl_adc_regmap #(
input adc_sync_status,
output adc_sync,
output adc_ext_sync_arm,
output adc_ext_sync_disarm,
output adc_ext_sync_manual_req,
output adc_rst,
// Underflow
@ -195,6 +199,9 @@ module ad_ip_jesd204_tpl_adc_regmap #(
end
// common processor control
//
localparam CONFIG = (EXT_SYNC << 12);
up_adc_common #(
.COMMON_ID (6'h0),
@ -206,7 +213,8 @@ module ad_ip_jesd204_tpl_adc_regmap #(
.DRP_DISABLE (1),
.USERPORTS_DISABLE (1),
.GPIO_DISABLE (1),
.START_CODE_DISABLE (1)
.START_CODE_DISABLE (1),
.CONFIG (CONFIG)
) i_up_adc_common (
.mmcm_rst (),
.adc_clk (link_clk),
@ -221,6 +229,9 @@ module ad_ip_jesd204_tpl_adc_regmap #(
.adc_start_code (),
.adc_sref_sync (),
.adc_sync (adc_sync),
.adc_ext_sync_arm (adc_ext_sync_arm),
.adc_ext_sync_disarm (adc_ext_sync_disarm),
.adc_ext_sync_manual_req (adc_ext_sync_manual_req),
.up_status_pn_err (up_status_pn_err),
.up_status_pn_oos (up_status_pn_oos),