ad_ip_jesd204_tpl_adc: Refactor external sync
- Add EXT_SYNC option - Gate valid while in resetmain
parent
8c7cca4277
commit
b5092662d5
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@ -17,6 +17,7 @@ GENERIC_DEPS += ../../common/up_axi.v
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GENERIC_DEPS += ../../common/up_clock_mon.v
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GENERIC_DEPS += ../../common/up_clock_mon.v
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GENERIC_DEPS += ../../common/up_xfer_cntrl.v
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GENERIC_DEPS += ../../common/up_xfer_cntrl.v
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GENERIC_DEPS += ../../common/up_xfer_status.v
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GENERIC_DEPS += ../../common/up_xfer_status.v
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GENERIC_DEPS += ../../common/util_ext_sync.v
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GENERIC_DEPS += ad_ip_jesd204_tpl_adc.v
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GENERIC_DEPS += ad_ip_jesd204_tpl_adc.v
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GENERIC_DEPS += ad_ip_jesd204_tpl_adc_channel.v
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GENERIC_DEPS += ad_ip_jesd204_tpl_adc_channel.v
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GENERIC_DEPS += ad_ip_jesd204_tpl_adc_core.v
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GENERIC_DEPS += ad_ip_jesd204_tpl_adc_core.v
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@ -37,7 +37,8 @@ module ad_ip_jesd204_tpl_adc #(
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parameter DMA_BITS_PER_SAMPLE = 16,
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parameter DMA_BITS_PER_SAMPLE = 16,
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parameter OCTETS_PER_BEAT = 4,
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parameter OCTETS_PER_BEAT = 4,
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parameter EN_FRAME_ALIGN = 1,
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parameter EN_FRAME_ALIGN = 1,
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parameter TWOS_COMPLEMENT = 1
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parameter TWOS_COMPLEMENT = 1,
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parameter EXT_SYNC = 0
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) (
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) (
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// jesd interface
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// jesd interface
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// link_clk is (line-rate/40)
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// link_clk is (line-rate/40)
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@ -57,6 +58,9 @@ module ad_ip_jesd204_tpl_adc #(
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input adc_dovf,
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input adc_dovf,
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input adc_sync_in,
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input adc_sync_in,
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output adc_sync_manual_req_out,
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input adc_sync_manual_req_in,
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output adc_rst,
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output adc_rst,
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// axi interface
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// axi interface
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@ -120,7 +124,8 @@ module ad_ip_jesd204_tpl_adc #(
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.DEV_PACKAGE (DEV_PACKAGE),
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.DEV_PACKAGE (DEV_PACKAGE),
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.NUM_CHANNELS (NUM_CHANNELS),
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.NUM_CHANNELS (NUM_CHANNELS),
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.DATA_PATH_WIDTH (DATA_PATH_WIDTH),
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.DATA_PATH_WIDTH (DATA_PATH_WIDTH),
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.NUM_PROFILES(1)
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.NUM_PROFILES(1),
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.EXT_SYNC (EXT_SYNC)
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) i_regmap (
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) i_regmap (
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.s_axi_aclk (s_axi_aclk),
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.s_axi_aclk (s_axi_aclk),
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.s_axi_aresetn (s_axi_aresetn),
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.s_axi_aresetn (s_axi_aresetn),
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@ -158,6 +163,9 @@ module ad_ip_jesd204_tpl_adc #(
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.adc_sync (adc_sync),
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.adc_sync (adc_sync),
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.adc_sync_status (adc_sync_status),
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.adc_sync_status (adc_sync_status),
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.adc_ext_sync_arm (adc_ext_sync_arm),
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.adc_ext_sync_disarm (adc_ext_sync_disarm),
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.adc_ext_sync_manual_req (adc_sync_manual_req_out),
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.adc_rst (adc_rst_s),
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.adc_rst (adc_rst_s),
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@ -184,7 +192,8 @@ module ad_ip_jesd204_tpl_adc #(
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.DMA_DATA_WIDTH (DMA_DATA_WIDTH),
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.DMA_DATA_WIDTH (DMA_DATA_WIDTH),
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.TWOS_COMPLEMENT (TWOS_COMPLEMENT),
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.TWOS_COMPLEMENT (TWOS_COMPLEMENT),
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.DATA_PATH_WIDTH (DATA_PATH_WIDTH),
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.DATA_PATH_WIDTH (DATA_PATH_WIDTH),
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.DMA_BITS_PER_SAMPLE (DMA_BITS_PER_SAMPLE)
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.DMA_BITS_PER_SAMPLE (DMA_BITS_PER_SAMPLE),
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.EXT_SYNC (EXT_SYNC)
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) i_core (
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) i_core (
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.clk (link_clk),
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.clk (link_clk),
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@ -204,8 +213,12 @@ module ad_ip_jesd204_tpl_adc #(
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.adc_sync (adc_sync),
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.adc_sync (adc_sync),
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.adc_sync_status (adc_sync_status),
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.adc_sync_status (adc_sync_status),
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.adc_sync_in (adc_sync_in),
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.adc_sync_in (adc_sync_in),
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.adc_ext_sync_arm (adc_ext_sync_arm),
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.adc_ext_sync_disarm (adc_ext_sync_disarm),
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.adc_sync_manual_req (adc_sync_manual_req_in),
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.adc_rst_sync (adc_rst_sync_s),
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.adc_rst_sync (adc_rst_sync_s),
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.adc_valid (adc_valid),
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.adc_valid (adc_valid),
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.adc_data (adc_data)
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.adc_data (adc_data)
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);
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);
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@ -35,7 +35,8 @@ module ad_ip_jesd204_tpl_adc_core #(
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parameter DATA_PATH_WIDTH = 1,
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parameter DATA_PATH_WIDTH = 1,
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parameter LINK_DATA_WIDTH = NUM_LANES * OCTETS_PER_BEAT * 8,
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parameter LINK_DATA_WIDTH = NUM_LANES * OCTETS_PER_BEAT * 8,
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parameter DMA_DATA_WIDTH = DATA_PATH_WIDTH * DMA_BITS_PER_SAMPLE * NUM_CHANNELS,
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parameter DMA_DATA_WIDTH = DATA_PATH_WIDTH * DMA_BITS_PER_SAMPLE * NUM_CHANNELS,
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parameter TWOS_COMPLEMENT = 1
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parameter TWOS_COMPLEMENT = 1,
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parameter EXT_SYNC = 0
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) (
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) (
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input clk,
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input clk,
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@ -52,7 +53,10 @@ module ad_ip_jesd204_tpl_adc_core #(
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input adc_sync,
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input adc_sync,
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output adc_sync_status,
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output adc_sync_status,
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input adc_ext_sync_arm,
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input adc_ext_sync_disarm,
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input adc_sync_in,
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input adc_sync_in,
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input adc_sync_manual_req,
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output adc_rst_sync,
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output adc_rst_sync,
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input link_valid,
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input link_valid,
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@ -68,14 +72,11 @@ module ad_ip_jesd204_tpl_adc_core #(
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wire [ADC_DATA_WIDTH-1:0] raw_data_s;
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wire [ADC_DATA_WIDTH-1:0] raw_data_s;
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wire link_valid_tmp;
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wire link_valid_tmp;
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reg adc_sync_armed = 1'b0;
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reg adc_sync_in_d1 = 1'b0;
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reg adc_sync_d1 = 1'b0;
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reg link_valid_d = 1'b0;
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reg link_valid_d = 1'b0;
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assign link_ready = 1'b1;
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assign link_ready = 1'b1;
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assign link_valid_tmp = EN_FRAME_ALIGN ? link_valid_d : link_valid;
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assign link_valid_tmp = EN_FRAME_ALIGN ? link_valid_d : link_valid;
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assign adc_valid = {NUM_CHANNELS{link_valid_tmp}};
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assign adc_valid = {NUM_CHANNELS{link_valid_tmp & ~adc_sync_armed}};
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assign adc_sync_status = adc_sync_armed;
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assign adc_sync_status = adc_sync_armed;
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assign adc_rst_sync = adc_sync_armed;
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assign adc_rst_sync = adc_sync_armed;
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@ -83,17 +84,16 @@ module ad_ip_jesd204_tpl_adc_core #(
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link_valid_d <= link_valid;
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link_valid_d <= link_valid;
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end
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end
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always @(posedge clk) begin
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adc_sync_in_d1 <= adc_sync_in;
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adc_sync_d1 <= adc_sync;
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if ((~adc_sync_d1 & adc_sync) == 1'b1) begin
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adc_sync_armed <= ~adc_sync_armed;
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end else if ((~adc_sync_in_d1 & adc_sync_in) == 1'b1) begin
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adc_sync_armed <= 1'b0;
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end
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end
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// synchronization logic
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// synchronization logic
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util_ext_sync #(
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.ENABLED (EXT_SYNC)
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) i_util_ext_sync (
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.clk (clk),
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.ext_sync_arm (adc_ext_sync_arm),
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.ext_sync_disarm (adc_ext_sync_disarm),
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.sync_in (adc_sync_in | adc_sync_manual_req),
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.sync_armed (adc_sync_armed)
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);
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ad_ip_jesd204_tpl_adc_deframer #(
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ad_ip_jesd204_tpl_adc_deframer #(
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.NUM_LANES (NUM_LANES),
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.NUM_LANES (NUM_LANES),
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@ -36,6 +36,7 @@ adi_ip_files ad_ip_jesd204_tpl_adc [list \
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"$ad_hdl_dir/library/common/up_clock_mon.v" \
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"$ad_hdl_dir/library/common/up_clock_mon.v" \
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"$ad_hdl_dir/library/common/up_adc_common.v" \
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"$ad_hdl_dir/library/common/up_adc_common.v" \
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"$ad_hdl_dir/library/common/up_adc_channel.v" \
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"$ad_hdl_dir/library/common/up_adc_channel.v" \
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"$ad_hdl_dir/library/common/util_ext_sync.v" \
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"$ad_hdl_dir/library/common/ad_xcvr_rx_if.v" \
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"$ad_hdl_dir/library/common/ad_xcvr_rx_if.v" \
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"$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
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"$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
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"$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
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"$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
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@ -72,6 +73,10 @@ adi_add_bus "link" "master" \
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]
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]
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adi_add_bus_clock "link_clk" "link"
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adi_add_bus_clock "link_clk" "link"
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adi_set_ports_dependency "adc_sync_in" "EXT_SYNC == 1"
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adi_set_ports_dependency "adc_sync_manual_req_out" "EXT_SYNC == 1"
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adi_set_ports_dependency "adc_sync_manual_req_in" "EXT_SYNC == 1"
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foreach {p v} {
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foreach {p v} {
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"NUM_LANES" "1 2 3 4 6 8 12 16" \
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"NUM_LANES" "1 2 3 4 6 8 12 16" \
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"NUM_CHANNELS" "1 2 4 6 8 16 32 64" \
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"NUM_CHANNELS" "1 2 4 6 8 16 32 64" \
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@ -128,6 +133,7 @@ set i 0
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foreach {k v w} {
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foreach {k v w} {
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"TWOS_COMPLEMENT" "Use twos complement" "checkBox" \
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"TWOS_COMPLEMENT" "Use twos complement" "checkBox" \
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"EXT_SYNC" "Enable external sync" "checkBox" \
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} { \
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} { \
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set p [ipgui::get_guiparamspec -name $k -component $cc]
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set p [ipgui::get_guiparamspec -name $k -component $cc]
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ipgui::move_param -component $cc -order $i $p -parent $datapath_group
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ipgui::move_param -component $cc -order $i $p -parent $datapath_group
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@ -31,7 +31,8 @@ module ad_ip_jesd204_tpl_adc_regmap #(
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parameter DEV_PACKAGE = 0,
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parameter DEV_PACKAGE = 0,
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parameter NUM_CHANNELS = 1,
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parameter NUM_CHANNELS = 1,
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parameter DATA_PATH_WIDTH = 1,
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parameter DATA_PATH_WIDTH = 1,
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parameter NUM_PROFILES = 1 // Number of supported JESD profiles
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parameter NUM_PROFILES = 1, // Number of supported JESD profiles
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parameter EXT_SYNC = 0
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) (
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) (
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// axi interface
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// axi interface
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input s_axi_aclk,
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input s_axi_aclk,
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@ -73,6 +74,9 @@ module ad_ip_jesd204_tpl_adc_regmap #(
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input adc_sync_status,
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input adc_sync_status,
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output adc_sync,
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output adc_sync,
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output adc_ext_sync_arm,
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output adc_ext_sync_disarm,
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output adc_ext_sync_manual_req,
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output adc_rst,
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output adc_rst,
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// Underflow
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// Underflow
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@ -195,6 +199,9 @@ module ad_ip_jesd204_tpl_adc_regmap #(
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end
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end
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// common processor control
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// common processor control
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//
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localparam CONFIG = (EXT_SYNC << 12);
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up_adc_common #(
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up_adc_common #(
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.COMMON_ID (6'h0),
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.COMMON_ID (6'h0),
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@ -206,7 +213,8 @@ module ad_ip_jesd204_tpl_adc_regmap #(
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.DRP_DISABLE (1),
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.DRP_DISABLE (1),
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.USERPORTS_DISABLE (1),
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.USERPORTS_DISABLE (1),
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.GPIO_DISABLE (1),
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.GPIO_DISABLE (1),
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.START_CODE_DISABLE (1)
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.START_CODE_DISABLE (1),
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.CONFIG (CONFIG)
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) i_up_adc_common (
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) i_up_adc_common (
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.mmcm_rst (),
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.mmcm_rst (),
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.adc_clk (link_clk),
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.adc_clk (link_clk),
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@ -221,6 +229,9 @@ module ad_ip_jesd204_tpl_adc_regmap #(
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.adc_start_code (),
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.adc_start_code (),
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.adc_sref_sync (),
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.adc_sref_sync (),
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.adc_sync (adc_sync),
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.adc_sync (adc_sync),
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.adc_ext_sync_arm (adc_ext_sync_arm),
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.adc_ext_sync_disarm (adc_ext_sync_disarm),
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.adc_ext_sync_manual_req (adc_ext_sync_manual_req),
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.up_status_pn_err (up_status_pn_err),
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.up_status_pn_err (up_status_pn_err),
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.up_status_pn_oos (up_status_pn_oos),
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.up_status_pn_oos (up_status_pn_oos),
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