axi_ad9361- independent disables
Rejeesh Kutty
parent
f7fb3ccaca
commit
b4fac96aad
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@ -37,263 +37,159 @@
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`timescale 1ns/100ps
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module axi_ad9361 (
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// physical interface (receive-lvds)
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rx_clk_in_p,
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rx_clk_in_n,
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rx_frame_in_p,
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rx_frame_in_n,
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rx_data_in_p,
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rx_data_in_n,
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// physical interface (receive-cmos)
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rx_clk_in,
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rx_frame_in,
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rx_data_in,
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// physical interface (transmit-lvds)
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tx_clk_out_p,
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tx_clk_out_n,
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tx_frame_out_p,
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tx_frame_out_n,
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tx_data_out_p,
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tx_data_out_n,
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// physical interface (transmit-cmos)
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tx_clk_out,
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tx_frame_out,
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tx_data_out,
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// ensm control
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enable,
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txnrx,
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// transmit master/slave
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dac_sync_in,
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dac_sync_out,
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// tdd sync (1s pulse)
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tdd_sync,
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tdd_sync_cntr,
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// delay clock
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delay_clk,
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// master interface
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l_clk,
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clk,
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rst,
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// dma interface
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adc_enable_i0,
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adc_valid_i0,
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adc_data_i0,
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adc_enable_q0,
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adc_valid_q0,
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adc_data_q0,
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adc_enable_i1,
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adc_valid_i1,
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adc_data_i1,
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adc_enable_q1,
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adc_valid_q1,
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adc_data_q1,
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adc_dovf,
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adc_dunf,
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adc_r1_mode,
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dac_enable_i0,
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dac_valid_i0,
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dac_data_i0,
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dac_enable_q0,
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dac_valid_q0,
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dac_data_q0,
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dac_enable_i1,
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dac_valid_i1,
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dac_data_i1,
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dac_enable_q1,
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dac_valid_q1,
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dac_data_q1,
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dac_dovf,
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dac_dunf,
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dac_r1_mode,
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// axi interface
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s_axi_aclk,
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s_axi_aresetn,
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s_axi_awvalid,
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s_axi_awaddr,
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s_axi_awprot,
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s_axi_awready,
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s_axi_wvalid,
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s_axi_wdata,
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s_axi_wstrb,
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s_axi_wready,
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s_axi_bvalid,
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s_axi_bresp,
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s_axi_bready,
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s_axi_arvalid,
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s_axi_araddr,
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s_axi_arprot,
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s_axi_arready,
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s_axi_rvalid,
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s_axi_rdata,
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s_axi_rresp,
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s_axi_rready,
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// gpio
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up_enable,
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up_txnrx,
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up_dac_gpio_in,
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up_dac_gpio_out,
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up_adc_gpio_in,
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up_adc_gpio_out);
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module axi_ad9361 #(
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// parameters
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parameter ID = 0;
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parameter DEVICE_TYPE = 0;
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parameter CMOS_OR_LVDS_N = 0;
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parameter DAC_IODELAY_ENABLE = 0;
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parameter IO_DELAY_GROUP = "dev_if_delay_group";
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parameter DAC_DATAPATH_DISABLE = 0;
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parameter ADC_DATAPATH_DISABLE = 0;
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parameter TDD_CONTROL_EN = 0;
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parameter R1_MODE_EN = 0;
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parameter ID = 0,
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parameter MODE_1R1T = 0,
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parameter DEVICE_TYPE = 0,
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parameter TDD_DISABLE = 0,
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parameter CMOS_OR_LVDS_N = 0,
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parameter ADC_DATAPATH_DISABLE = 0,
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parameter ADC_USERPORTS_DISABLE = 0,
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parameter ADC_DATAFORMAT_DISABLE = 0,
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parameter ADC_DCFILTER_DISABLE = 0,
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parameter ADC_IQCORRECTION_DISABLE = 0,
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parameter DAC_IODELAY_ENABLE = 0,
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parameter DAC_DATAPATH_DISABLE = 0,
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parameter DAC_DDS_DISABLE = 0,
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parameter DAC_USERPORTS_DISABLE = 0,
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parameter DAC_IQCORRECTION_DISABLE = 0,
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parameter IO_DELAY_GROUP = "dev_if_delay_group") (
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// physical interface (receive-lvds)
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input rx_clk_in_p;
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input rx_clk_in_n;
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input rx_frame_in_p;
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input rx_frame_in_n;
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input [ 5:0] rx_data_in_p;
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input [ 5:0] rx_data_in_n;
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input rx_clk_in_p,
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input rx_clk_in_n,
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input rx_frame_in_p,
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input rx_frame_in_n,
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input [ 5:0] rx_data_in_p,
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input [ 5:0] rx_data_in_n,
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// physical interface (receive-cmos)
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input rx_clk_in;
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input rx_frame_in;
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input [11:0] rx_data_in;
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input rx_clk_in,
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input rx_frame_in,
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input [11:0] rx_data_in,
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// physical interface (transmit-lvds)
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output tx_clk_out_p;
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output tx_clk_out_n;
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output tx_frame_out_p;
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output tx_frame_out_n;
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output [ 5:0] tx_data_out_p;
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output [ 5:0] tx_data_out_n;
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output tx_clk_out_p,
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output tx_clk_out_n,
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output tx_frame_out_p,
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output tx_frame_out_n,
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output [ 5:0] tx_data_out_p,
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output [ 5:0] tx_data_out_n,
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// physical interface (transmit-cmos)
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output tx_clk_out;
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output tx_frame_out;
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output [11:0] tx_data_out;
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output tx_clk_out,
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output tx_frame_out,
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output [11:0] tx_data_out,
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// ensm control
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output enable;
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output txnrx;
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output enable,
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output txnrx,
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// transmit master/slave
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input dac_sync_in;
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output dac_sync_out;
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input dac_sync_in,
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output dac_sync_out,
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// tdd sync
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input tdd_sync;
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output tdd_sync_cntr;
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input tdd_sync,
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output tdd_sync_cntr,
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// delay clock
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input delay_clk;
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input delay_clk,
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// master interface
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output l_clk;
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input clk;
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output rst;
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output l_clk,
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input clk,
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output rst,
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// dma interface
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output adc_enable_i0;
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output adc_valid_i0;
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output [15:0] adc_data_i0;
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output adc_enable_q0;
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output adc_valid_q0;
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output [15:0] adc_data_q0;
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output adc_enable_i1;
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output adc_valid_i1;
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output [15:0] adc_data_i1;
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output adc_enable_q1;
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output adc_valid_q1;
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output [15:0] adc_data_q1;
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input adc_dovf;
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input adc_dunf;
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output adc_r1_mode;
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output adc_enable_i0,
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output adc_valid_i0,
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output [15:0] adc_data_i0,
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output adc_enable_q0,
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output adc_valid_q0,
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output [15:0] adc_data_q0,
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output adc_enable_i1,
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output adc_valid_i1,
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output [15:0] adc_data_i1,
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output adc_enable_q1,
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output adc_valid_q1,
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output [15:0] adc_data_q1,
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input adc_dovf,
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input adc_dunf,
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output adc_r1_mode,
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output dac_enable_i0;
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output dac_valid_i0;
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input [15:0] dac_data_i0;
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output dac_enable_q0;
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output dac_valid_q0;
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input [15:0] dac_data_q0;
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output dac_enable_i1;
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output dac_valid_i1;
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input [15:0] dac_data_i1;
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output dac_enable_q1;
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output dac_valid_q1;
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input [15:0] dac_data_q1;
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input dac_dovf;
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input dac_dunf;
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output dac_r1_mode;
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output dac_enable_i0,
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output dac_valid_i0,
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input [15:0] dac_data_i0,
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output dac_enable_q0,
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output dac_valid_q0,
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input [15:0] dac_data_q0,
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output dac_enable_i1,
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output dac_valid_i1,
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input [15:0] dac_data_i1,
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output dac_enable_q1,
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output dac_valid_q1,
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input [15:0] dac_data_q1,
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input dac_dovf,
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input dac_dunf,
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output dac_r1_mode,
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// axi interface
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input s_axi_aclk;
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input s_axi_aresetn;
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input s_axi_awvalid;
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input [31:0] s_axi_awaddr;
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input [ 2:0] s_axi_awprot;
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output s_axi_awready;
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input s_axi_wvalid;
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input [31:0] s_axi_wdata;
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input [ 3:0] s_axi_wstrb;
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output s_axi_wready;
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output s_axi_bvalid;
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output [ 1:0] s_axi_bresp;
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input s_axi_bready;
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input s_axi_arvalid;
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input [31:0] s_axi_araddr;
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input [ 2:0] s_axi_arprot;
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output s_axi_arready;
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output s_axi_rvalid;
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output [31:0] s_axi_rdata;
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output [ 1:0] s_axi_rresp;
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input s_axi_rready;
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [31:0] s_axi_awaddr,
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input [ 2:0] s_axi_awprot,
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output s_axi_awready,
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input s_axi_wvalid,
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input [31:0] s_axi_wdata,
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input [ 3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [ 1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [31:0] s_axi_araddr,
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input [ 2:0] s_axi_arprot,
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output s_axi_arready,
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output s_axi_rvalid,
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output [31:0] s_axi_rdata,
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output [ 1:0] s_axi_rresp,
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input s_axi_rready,
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// gpio
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input up_enable;
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input up_txnrx;
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input [31:0] up_dac_gpio_in;
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output [31:0] up_dac_gpio_out;
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input [31:0] up_adc_gpio_in;
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output [31:0] up_adc_gpio_out;
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input up_enable,
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input up_txnrx,
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input [31:0] up_dac_gpio_in,
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output [31:0] up_dac_gpio_out,
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input [31:0] up_adc_gpio_in,
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output [31:0] up_adc_gpio_out);
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// derived parameters
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localparam ADC_USERPORTS_DISABLE_INT = (ADC_DATAPATH_DISABLE == 1) ? 1 : ADC_USERPORTS_DISABLE;
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localparam ADC_DATAFORMAT_DISABLE_INT = (ADC_DATAPATH_DISABLE == 1) ? 1 : ADC_DATAFORMAT_DISABLE;
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localparam ADC_DCFILTER_DISABLE_INT = (ADC_DATAPATH_DISABLE == 1) ? 1 : ADC_DCFILTER_DISABLE;
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localparam ADC_IQCORRECTION_DISABLE_INT = (ADC_DATAPATH_DISABLE == 1) ? 1 : ADC_IQCORRECTION_DISABLE;
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localparam DAC_DDS_DISABLE_INT = (DAC_DATAPATH_DISABLE == 1) ? 1 : DAC_DDS_DISABLE;
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localparam DAC_USERPORTS_DISABLE_INT = (DAC_DATAPATH_DISABLE == 1) ? 1 : DAC_USERPORTS_DISABLE;
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localparam DAC_DELAYCNTRL_DISABLE_INT = (DAC_IODELAY_ENABLE == 1) ? 0 : 1;
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localparam DAC_IQCORRECTION_DISABLE_INT = (DAC_DATAPATH_DISABLE == 1) ? 1 : DAC_IQCORRECTION_DISABLE;
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// internal registers
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@ -316,7 +212,6 @@ module axi_ad9361 (
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wire adc_status_s;
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wire dac_clksel_s;
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wire dac_valid_s;
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wire g_dac_valid_s;
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wire [47:0] dac_data_s;
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wire dac_valid_i0_s;
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wire dac_valid_q0_s;
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@ -343,18 +238,20 @@ module axi_ad9361 (
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wire up_wack_tdd_s;
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wire up_rack_tdd_s;
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wire [31:0] up_rdata_tdd_s;
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wire tdd_tx_dp_en_s;
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wire tdd_enable_s;
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wire tdd_txnrx_s;
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wire tdd_mode_s;
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wire tdd_tx_valid_s;
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wire tdd_rx_valid_s;
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wire tdd_rx_vco_en_s;
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wire tdd_tx_vco_en_s;
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wire tdd_rx_rf_en_s;
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wire tdd_tx_rf_en_s;
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wire [ 7:0] tdd_status_s;
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wire adc_valid_i0_s;
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wire adc_valid_q0_s;
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wire adc_valid_i1_s;
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wire adc_valid_q1_s;
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wire [15:0] adc_data_i0_s;
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wire [15:0] adc_data_q0_s;
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wire [15:0] adc_data_i1_s;
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wire [15:0] adc_data_q1_s;
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// signal name changes
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@ -408,7 +305,7 @@ module axi_ad9361 (
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.adc_status (adc_status_s),
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.adc_r1_mode (adc_r1_mode),
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.adc_ddr_edgesel (adc_ddr_edgesel_s),
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.dac_valid (g_dac_valid_s),
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.dac_valid (dac_valid_s),
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.dac_data (dac_data_s),
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.dac_clksel (dac_clksel_s),
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.dac_r1_mode (dac_r1_mode),
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@ -467,7 +364,7 @@ module axi_ad9361 (
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.adc_status (adc_status_s),
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.adc_r1_mode (adc_r1_mode),
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.adc_ddr_edgesel (adc_ddr_edgesel_s),
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.dac_valid (g_dac_valid_s),
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.dac_valid (dac_valid_s),
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.dac_data (dac_data_s),
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.dac_clksel (dac_clksel_s),
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.dac_r1_mode (dac_r1_mode),
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@ -490,83 +387,73 @@ module axi_ad9361 (
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end
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endgenerate
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assign dac_valid_i0 = tdd_tx_valid_s & dac_valid_i0_s;
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assign dac_valid_q0 = tdd_tx_valid_s & dac_valid_q0_s;
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assign dac_valid_i1 = tdd_tx_valid_s & dac_valid_i1_s;
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assign dac_valid_q1 = tdd_tx_valid_s & dac_valid_q1_s;
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assign adc_valid_i0 = tdd_rx_valid_s & adc_valid_i0_s;
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assign adc_valid_q0 = tdd_rx_valid_s & adc_valid_q0_s;
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assign adc_valid_i1 = tdd_rx_valid_s & adc_valid_i1_s;
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assign adc_valid_q1 = tdd_rx_valid_s & adc_valid_q1_s;
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// tdd
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generate
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if (TDD_CONTROL_EN) begin
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if (TDD_DISABLE == 1) begin
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assign tdd_enable_s = 1'b0;
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assign tdd_txnrx_s = 1'b0;
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assign tdd_txnrx_s = 1'b0;
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assign tdd_mode_s = 1'b0;
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assign tdd_rx_vco_en_s = 1'b0;
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assign tdd_tx_vco_en_s = 1'b0;
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assign tdd_rx_rf_en_s = 1'b0;
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assign tdd_tx_rf_en_s = 1'b0;
|
||||
assign tdd_status_s = 8'd0;
|
||||
assign tdd_sync_cntr = 1'b0;
|
||||
assign tdd_tx_valid_s = 1'b1;
|
||||
assign tdd_rx_valid_s = 1'b1;
|
||||
assign up_wack_tdd_s = 1'b0;
|
||||
assign up_rack_tdd_s = 1'b0;
|
||||
assign up_rdata_tdd_s = 32'b0;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
wire tdd_rx_vco_en_s;
|
||||
wire tdd_tx_vco_en_s;
|
||||
wire tdd_rx_rf_en_s;
|
||||
wire tdd_tx_rf_en_s;
|
||||
wire [ 7:0] tdd_status_s;
|
||||
|
||||
axi_ad9361_tdd_if #(.LEVEL_OR_PULSE_N(1)) i_tdd_if (
|
||||
.clk (clk),
|
||||
.rst (rst),
|
||||
.tdd_rx_vco_en (tdd_rx_vco_en_s),
|
||||
.tdd_tx_vco_en (tdd_tx_vco_en_s),
|
||||
.tdd_rx_rf_en (tdd_rx_rf_en_s),
|
||||
.tdd_tx_rf_en (tdd_tx_rf_en_s),
|
||||
.ad9361_txnrx (tdd_txnrx_s),
|
||||
.ad9361_enable (tdd_enable_s),
|
||||
.ad9361_tdd_status (tdd_status_s));
|
||||
|
||||
assign g_dac_valid_s = dac_valid_s;
|
||||
assign dac_valid_i0 = tdd_tx_valid_s & dac_valid_i0_s;
|
||||
assign dac_valid_q0 = tdd_tx_valid_s & dac_valid_q0_s;
|
||||
assign dac_valid_i1 = tdd_tx_valid_s & dac_valid_i1_s;
|
||||
assign dac_valid_q1 = tdd_tx_valid_s & dac_valid_q1_s;
|
||||
assign adc_valid_i0 = tdd_rx_valid_s & adc_valid_i0_s;
|
||||
assign adc_valid_q0 = tdd_rx_valid_s & adc_valid_q0_s;
|
||||
assign adc_valid_i1 = tdd_rx_valid_s & adc_valid_i1_s;
|
||||
assign adc_valid_q1 = tdd_rx_valid_s & adc_valid_q1_s;
|
||||
|
||||
// TDD control
|
||||
|
||||
axi_ad9361_tdd i_tdd (
|
||||
.clk (clk),
|
||||
.rst (rst),
|
||||
.tdd_rx_vco_en (tdd_rx_vco_en_s),
|
||||
.tdd_tx_vco_en (tdd_tx_vco_en_s),
|
||||
.tdd_rx_rf_en (tdd_rx_rf_en_s),
|
||||
.tdd_tx_rf_en (tdd_tx_rf_en_s),
|
||||
.tdd_enabled (tdd_mode_s),
|
||||
.tdd_status (tdd_status_s),
|
||||
.tdd_sync (tdd_sync),
|
||||
.tdd_sync_cntr (tdd_sync_cntr),
|
||||
.tdd_tx_valid (tdd_tx_valid_s),
|
||||
.tdd_rx_valid (tdd_rx_valid_s),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq_s),
|
||||
.up_waddr (up_waddr_s),
|
||||
.up_wdata (up_wdata_s),
|
||||
.up_wack (up_wack_tdd_s),
|
||||
.up_rreq (up_rreq_s),
|
||||
.up_raddr (up_raddr_s),
|
||||
.up_rdata (up_rdata_tdd_s),
|
||||
.up_rack (up_rack_tdd_s));
|
||||
|
||||
end else begin
|
||||
|
||||
// TDD control bypass
|
||||
|
||||
assign tdd_mode_s = 1'b0;
|
||||
assign tdd_enable_s = 1'b0;
|
||||
assign tdd_txnrx_s = 1'b0;
|
||||
assign tdd_sync_cntr = 1'b0;
|
||||
assign g_dac_valid_s = dac_valid_s;
|
||||
assign dac_valid_i0 = dac_valid_i0_s;
|
||||
assign dac_valid_q0 = dac_valid_q0_s;
|
||||
assign dac_valid_i1 = dac_valid_i1_s;
|
||||
assign dac_valid_q1 = dac_valid_q1_s;
|
||||
assign adc_valid_i0 = adc_valid_i0_s;
|
||||
assign adc_valid_q0 = adc_valid_q0_s;
|
||||
assign adc_valid_i1 = adc_valid_i1_s;
|
||||
assign adc_valid_q1 = adc_valid_q1_s;
|
||||
assign up_wack_tdd_s = 1'b0;
|
||||
assign up_rack_tdd_s = 1'b0;
|
||||
assign up_rdata_tdd_s = 32'b0;
|
||||
generate
|
||||
if (TDD_DISABLE == 0) begin
|
||||
axi_ad9361_tdd_if #(.LEVEL_OR_PULSE_N(1)) i_tdd_if (
|
||||
.clk (clk),
|
||||
.rst (rst),
|
||||
.tdd_rx_vco_en (tdd_rx_vco_en_s),
|
||||
.tdd_tx_vco_en (tdd_tx_vco_en_s),
|
||||
.tdd_rx_rf_en (tdd_rx_rf_en_s),
|
||||
.tdd_tx_rf_en (tdd_tx_rf_en_s),
|
||||
.ad9361_txnrx (tdd_txnrx_s),
|
||||
.ad9361_enable (tdd_enable_s),
|
||||
.ad9361_tdd_status (tdd_status_s));
|
||||
|
||||
axi_ad9361_tdd i_tdd (
|
||||
.clk (clk),
|
||||
.rst (rst),
|
||||
.tdd_rx_vco_en (tdd_rx_vco_en_s),
|
||||
.tdd_tx_vco_en (tdd_tx_vco_en_s),
|
||||
.tdd_rx_rf_en (tdd_rx_rf_en_s),
|
||||
.tdd_tx_rf_en (tdd_tx_rf_en_s),
|
||||
.tdd_enabled (tdd_mode_s),
|
||||
.tdd_status (tdd_status_s),
|
||||
.tdd_sync (tdd_sync),
|
||||
.tdd_sync_cntr (tdd_sync_cntr),
|
||||
.tdd_tx_valid (tdd_tx_valid_s),
|
||||
.tdd_rx_valid (tdd_rx_valid_s),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq_s),
|
||||
.up_waddr (up_waddr_s),
|
||||
.up_wdata (up_wdata_s),
|
||||
.up_wack (up_wack_tdd_s),
|
||||
.up_rreq (up_rreq_s),
|
||||
.up_raddr (up_raddr_s),
|
||||
.up_rdata (up_rdata_tdd_s),
|
||||
.up_rack (up_rack_tdd_s));
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
|
@ -574,11 +461,11 @@ module axi_ad9361 (
|
|||
|
||||
axi_ad9361_rx #(
|
||||
.ID (ID),
|
||||
.MODE_1R1T (R1_MODE_EN),
|
||||
.USERPORTS_DISABLE (ADC_DATAPATH_DISABLE),
|
||||
.DATAFORMAT_DISABLE (ADC_DATAPATH_DISABLE),
|
||||
.DCFILTER_DISABLE (ADC_DATAPATH_DISABLE),
|
||||
.IQCORRECTION_DISABLE (ADC_DATAPATH_DISABLE))
|
||||
.MODE_1R1T (MODE_1R1T),
|
||||
.USERPORTS_DISABLE (ADC_USERPORTS_DISABLE_INT),
|
||||
.DATAFORMAT_DISABLE (ADC_DATAFORMAT_DISABLE_INT),
|
||||
.DCFILTER_DISABLE (ADC_DCFILTER_DISABLE_INT),
|
||||
.IQCORRECTION_DISABLE (ADC_IQCORRECTION_DISABLE_INT))
|
||||
i_rx (
|
||||
.mmcm_rst (mmcm_rst),
|
||||
.adc_rst (rst),
|
||||
|
|
@ -626,11 +513,11 @@ module axi_ad9361 (
|
|||
|
||||
axi_ad9361_tx #(
|
||||
.ID (ID),
|
||||
.MODE_1R1T (R1_MODE_EN),
|
||||
.DDS_DISABLE (DAC_DATAPATH_DISABLE),
|
||||
.USERPORTS_DISABLE (DAC_DATAPATH_DISABLE),
|
||||
.DELAYCNTRL_DISABLE (DAC_DATAPATH_DISABLE),
|
||||
.IQCORRECTION_DISABLE (DAC_DATAPATH_DISABLE))
|
||||
.MODE_1R1T (MODE_1R1T),
|
||||
.DDS_DISABLE (DAC_DDS_DISABLE_INT),
|
||||
.USERPORTS_DISABLE (DAC_USERPORTS_DISABLE_INT),
|
||||
.DELAYCNTRL_DISABLE (DAC_DELAYCNTRL_DISABLE_INT),
|
||||
.IQCORRECTION_DISABLE (DAC_IQCORRECTION_DISABLE_INT))
|
||||
i_tx (
|
||||
.dac_clk (clk),
|
||||
.dac_valid (dac_valid_s),
|
||||
|
|
|
|||
Loading…
Reference in New Issue