zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

axi_ad9467: Added CDC and reset constraints

main
Adrian Costina 2015-04-23 10:30:33 +03:00
parent ac79c65b81
commit b4a09daf89
2 changed files with 48 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

44
library/axi_ad9467/axi_ad9467_constr.xdc Normal file
View File

@ -0,0 +1,44 @@
set up_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
set ad9467_clk [get_clocks -of_objects [get_ports adc_clk_in_p]]
set_property ASYNC_REG TRUE \
[get_cells -hier *toggle_m1_reg*] \
[get_cells -hier *toggle_m2_reg*] \
[get_cells -hier *state_m1_reg*] \
[get_cells -hier *state_m2_reg*]
set_false_path \
-from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier d_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}]
set_false_path \
-from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier up_xfer_state_m1_reg* -filter {primitive_subgroup == flop}]
set_max_delay -datapath_only \
-from [get_cells -hier up_xfer_data_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier d_data_cntrl_reg* -filter {primitive_subgroup == flop}] \
[get_property PERIOD $ad9467_clk]
set_false_path \
-from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier up_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}]
set_false_path \
-from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier d_xfer_state_m1_reg* -filter {primitive_subgroup == flop}]
set_max_delay -datapath_only \
-from [get_cells -hier d_xfer_data_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier up_data_status_reg* -filter {primitive_subgroup == flop}] \
[get_property PERIOD $up_clk]
set_false_path \
-from [get_cells -hier up_count_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier d_count_toggle_m1_reg* -filter {primitive_subgroup == flop}]
set_false_path \
-from [get_cells -hier d_count_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier up_count_toggle_m1_reg* -filter {primitive_subgroup == flop}]
set_max_delay -datapath_only \
-from [get_cells -hier d_count_hold_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier up_d_count_reg* -filter {primitive_subgroup == flop}] \
[get_property PERIOD $up_clk]
set_false_path \
-to [get_pins -hier */PRE -filter {NAME =~ *i_*rst_reg*}]

4
library/axi_ad9467/axi_ad9467_ip.tcl
View File

@ -21,8 +21,12 @@ adi_ip_files axi_ad9467 [list \
"axi_ad9467_pnmon.v" \
"axi_ad9467_if.v" \
"axi_ad9467_channel.v" \
"axi_ad9467_constr.xdc" \
"axi_ad9467.v"]
adi_ip_properties axi_ad9467
adi_ip_constraints axi_ad9467 [list \
"axi_ad9467_constr.xdc" ]
ipx::save_core [ipx::current_core]