From b4a09daf8948896cf5d8fd86ff5226327f29c220 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Thu, 23 Apr 2015 10:30:33 +0300
Subject: [PATCH] axi_ad9467: Added CDC and reset constraints

---
 library/axi_ad9467/axi_ad9467_constr.xdc | 44 ++++++++++++++++++++++++
 library/axi_ad9467/axi_ad9467_ip.tcl     |  4 +++
 2 files changed, 48 insertions(+)
 create mode 100644 library/axi_ad9467/axi_ad9467_constr.xdc

diff --git a/library/axi_ad9467/axi_ad9467_constr.xdc b/library/axi_ad9467/axi_ad9467_constr.xdc
new file mode 100644
index 000000000..d62b39f26
--- /dev/null
+++ b/library/axi_ad9467/axi_ad9467_constr.xdc
@@ -0,0 +1,44 @@
+set up_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
+set ad9467_clk [get_clocks -of_objects [get_ports adc_clk_in_p]]
+
+set_property ASYNC_REG TRUE \
+  [get_cells -hier *toggle_m1_reg*] \
+  [get_cells -hier *toggle_m2_reg*] \
+  [get_cells -hier *state_m1_reg*] \
+  [get_cells -hier *state_m2_reg*]
+
+set_false_path \
+  -from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
+  -to [get_cells -hier d_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}]
+set_false_path \
+  -from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
+  -to [get_cells -hier up_xfer_state_m1_reg* -filter {primitive_subgroup == flop}]
+set_max_delay -datapath_only \
+  -from [get_cells -hier up_xfer_data_reg* -filter {primitive_subgroup == flop}] \
+  -to [get_cells -hier d_data_cntrl_reg* -filter {primitive_subgroup == flop}] \
+  [get_property PERIOD $ad9467_clk]
+
+set_false_path \
+  -from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
+  -to [get_cells -hier up_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}]
+set_false_path \
+  -from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
+  -to [get_cells -hier d_xfer_state_m1_reg* -filter {primitive_subgroup == flop}]
+set_max_delay -datapath_only \
+  -from [get_cells -hier d_xfer_data_reg* -filter {primitive_subgroup == flop}] \
+  -to [get_cells -hier up_data_status_reg* -filter {primitive_subgroup == flop}] \
+  [get_property PERIOD $up_clk]
+
+set_false_path \
+  -from [get_cells -hier up_count_toggle_reg* -filter {primitive_subgroup == flop}] \
+  -to [get_cells -hier d_count_toggle_m1_reg* -filter {primitive_subgroup == flop}]
+set_false_path \
+  -from [get_cells -hier d_count_toggle_reg* -filter {primitive_subgroup == flop}] \
+  -to [get_cells -hier up_count_toggle_m1_reg* -filter {primitive_subgroup == flop}]
+set_max_delay -datapath_only \
+  -from [get_cells -hier d_count_hold_reg* -filter {primitive_subgroup == flop}] \
+  -to [get_cells -hier up_d_count_reg* -filter {primitive_subgroup == flop}] \
+  [get_property PERIOD $up_clk]
+
+set_false_path \
+  -to [get_pins -hier */PRE -filter {NAME =~ *i_*rst_reg*}]
diff --git a/library/axi_ad9467/axi_ad9467_ip.tcl b/library/axi_ad9467/axi_ad9467_ip.tcl
index 1f944daf5..1cd0d48b2 100644
--- a/library/axi_ad9467/axi_ad9467_ip.tcl
+++ b/library/axi_ad9467/axi_ad9467_ip.tcl
@@ -21,8 +21,12 @@ adi_ip_files axi_ad9467 [list \
   "axi_ad9467_pnmon.v" \
   "axi_ad9467_if.v" \
   "axi_ad9467_channel.v" \
+  "axi_ad9467_constr.xdc" \
   "axi_ad9467.v"]
 
 adi_ip_properties axi_ad9467
 
+adi_ip_constraints axi_ad9467 [list \
+  "axi_ad9467_constr.xdc" ]
+
 ipx::save_core [ipx::current_core]