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library: local constraints async groups

main
Rejeesh Kutty 2014-08-14 15:08:27 -04:00
parent 01963b01fc
commit b481df0b5f
12 changed files with 55 additions and 116 deletions
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8
library/axi_ad9144/axi_ad9144_constr.xdc
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@ -1,8 +1,6 @@
set ip_dac_clk [get_clocks -of_objects [get_ports dac_clk]]
set ip_cpu_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
set_false_path -from $ip_dac_clk -to $ip_cpu_clk
set_false_path -from $ip_cpu_clk -to $ip_dac_clk
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports dac_clk]]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports s_axi_aclk]]

8
library/axi_ad9680/axi_ad9680_constr.xdc
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@ -1,8 +1,6 @@
set ip_adc_clk [get_clocks -of_objects [get_ports adc_clk]]
set ip_cpu_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
set_false_path -from $ip_adc_clk -to $ip_cpu_clk
set_false_path -from $ip_cpu_clk -to $ip_adc_clk
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports adc_clk]]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports s_axi_aclk]]

31
library/axi_dmac/axi_dmac_constr.xdc
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@ -1,30 +1,9 @@
set ip_device_wr_clk [get_clocks -of_objects [get_ports fifo_wr_clk]]
set ip_dma_wr_clk [get_clocks -of_objects [get_ports m_dest_axi_aclk]]
set ip_device_rd_clk [get_clocks -of_objects [get_ports fifo_rd_clk]]
set ip_dma_rd_clk [get_clocks -of_objects [get_ports m_src_axi_aclk]]
set ip_cpu_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
set_false_path -from $ip_cpu_clk -to $ip_device_wr_clk
set_false_path -from $ip_cpu_clk -to $ip_dma_wr_clk
set_false_path -from $ip_cpu_clk -to $ip_device_rd_clk
set_false_path -from $ip_cpu_clk -to $ip_dma_rd_clk
set_false_path -from $ip_device_wr_clk -to $ip_cpu_clk
set_false_path -from $ip_device_wr_clk -to $ip_dma_wr_clk
set_false_path -from $ip_device_wr_clk -to $ip_device_rd_clk
set_false_path -from $ip_device_wr_clk -to $ip_dma_rd_clk
set_false_path -from $ip_dma_wr_clk -to $ip_device_wr_clk
set_false_path -from $ip_dma_wr_clk -to $ip_cpu_clk
set_false_path -from $ip_dma_wr_clk -to $ip_device_rd_clk
set_false_path -from $ip_dma_wr_clk -to $ip_dma_rd_clk
set_false_path -from $ip_device_rd_clk -to $ip_device_wr_clk
set_false_path -from $ip_device_rd_clk -to $ip_dma_wr_clk
set_false_path -from $ip_device_rd_clk -to $ip_cpu_clk
set_false_path -from $ip_device_rd_clk -to $ip_dma_rd_clk
set_false_path -from $ip_dma_rd_clk -to $ip_device_wr_clk
set_false_path -from $ip_dma_rd_clk -to $ip_dma_wr_clk
set_false_path -from $ip_dma_rd_clk -to $ip_device_rd_clk
set_false_path -from $ip_dma_rd_clk -to $ip_cpu_clk
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports fifo_wr_clk]]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports m_dest_axi_aclk]]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports fifo_rd_clk]]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports m_src_axi_aclk]]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports s_axi_aclk]]

13
library/axi_hdmi_tx/axi_hdmi_tx_constr.xdc
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@ -1,13 +1,6 @@
set ip_hdmi_clk [get_clocks -of_objects [get_ports hdmi_clk]]
set ip_dma_clk [get_clocks -of_objects [get_ports m_axis_mm2s_clk]]
set ip_cpu_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
set_false_path -from $ip_hdmi_clk -to $ip_cpu_clk
set_false_path -from $ip_hdmi_clk -to $ip_dma_clk
set_false_path -from $ip_dma_clk -to $ip_hdmi_clk
set_false_path -from $ip_dma_clk -to $ip_cpu_clk
set_false_path -from $ip_cpu_clk -to $ip_hdmi_clk
set_false_path -from $ip_cpu_clk -to $ip_dma_clk
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports hdmi_clk]]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports m_axis_mm2s_clk]]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports s_axi_aclk]]

26
library/axi_jesd_gt/axi_jesd_gt_constr.xdc
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@ -1,20 +1,14 @@
set ip_rx_clk [get_clocks -of_objects [get_ports rx_clk]]
set ip_tx_clk [get_clocks -of_objects [get_ports tx_clk]]
set ip_cpu_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
set_clock_group -asynchronous -group [get_clocks -of_objects [get_ports rx_clk]]
set_clock_group -asynchronous -group [get_clocks -of_objects [get_ports tx_clk]]
set_clock_group -asynchronous -group [get_clocks -of_objects [get_ports s_axi_aclk]]
set_clock_group -asynchronous -group [get_clocks -of_objects [get_ports m_axi_aclk]]
set_false_path -from $ip_cpu_clk -to $ip_rx_clk
set_false_path -from $ip_cpu_clk -to $ip_tx_clk
set_false_path -from $ip_rx_clk -to $ip_cpu_clk
set_false_path -from $ip_rx_clk -to $ip_cpu_clk
set_false_path -from $ip_tx_clk -to $ip_cpu_clk
set_false_path -from $ip_tx_clk -to $ip_cpu_clk
set_false_path -through [get_pins i_up_gt/i_drp_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_up_gt/i_gt_pll_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_up_gt/i_gt_rx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_up_gt/i_gt_tx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_up_gt/i_rx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_up_gt/i_tx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins */i_up_gt/i_drp_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins */i_up_gt/i_gt_pll_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins */i_up_gt/i_gt_rx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins */i_up_gt/i_gt_tx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins */i_up_gt/i_rx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins */i_up_gt/i_tx_rst_reg/i_rst_reg/PRE]

2
library/axi_jesd_gt/axi_jesd_gt_ip.tcl
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@ -18,6 +18,8 @@ adi_ip_files axi_jesd_gt [list \
"axi_jesd_gt.v" ]
adi_ip_properties axi_jesd_gt
adi_ip_constraints axi_jesd_gt [list \
"axi_jesd_gt_constr.xdc" ]
ipx::save_core [ipx::current_core]

22
library/axi_spdif_tx/axi_spdif_tx_constr.xdc
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@ -1,20 +1,8 @@
set ip_spdif_clk [get_clocks -of_objects [get_ports spdif_data_clk]]
set ip_dma_clk [get_clocks -of_objects [get_ports s_axis_aclk]]
set ip_ps7_clk [get_clocks -of_objects [get_ports DMA_REQ_ACLK]]
set ip_cpu_clk [get_clocks -of_objects [get_ports S_AXI_ACLK]]
set_false_path -from $ip_spdif_clk -to $ip_cpu_clk
set_false_path -from $ip_spdif_clk -to $ip_dma_clk
set_false_path -from $ip_spdif_clk -to $ip_ps7_clk
set_false_path -from $ip_dma_clk -to $ip_spdif_clk
set_false_path -from $ip_dma_clk -to $ip_cpu_clk
set_false_path -from $ip_dma_clk -to $ip_ps7_clk
set_false_path -from $ip_cpu_clk -to $ip_spdif_clk
set_false_path -from $ip_cpu_clk -to $ip_dma_clk
set_false_path -from $ip_cpu_clk -to $ip_ps7_clk
set_false_path -from $ip_ps7_clk -to $ip_spdif_clk
set_false_path -from $ip_ps7_clk -to $ip_cpu_clk
set_false_path -from $ip_ps7_clk -to $ip_dma_clk
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports spdif_data_clk]]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports S_AXIS_ACLK]]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports DMA_REQ_ACLK]]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports S_AXI_ACLK]]

6
library/axi_spdif_tx/axi_spdif_tx_ip.tcl
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@ -15,6 +15,12 @@ adi_ip_files axi_spdif_tx [list \
adi_ip_properties_lite axi_spdif_tx
set ip_constr_files "axi_spdif_tx_constr.xdc"
set proj_filegroup [ipx::get_file_group xilinx_vhdlsynthesis [ipx::current_core]]
ipx::add_file $ip_constr_files $proj_filegroup
set_property type {{xdc}} [ipx::get_file $ip_constr_files $proj_filegroup]
set_property library_name {} [ipx::get_file $ip_constr_files $proj_filegroup]
adi_add_bus "S_AXIS" "axis" "slave" \
[list {"S_AXIS_ACLK" "ACLK"} \
{"S_AXIS_ARESETN" "ARESETN"} \

1
projects/common/kcu105/kcu105_system_bd.tcl
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@ -104,6 +104,7 @@ set_property -dict [list CONFIG.NUM_MI {1}] $axi_mem_interconnect
set_property -dict [list CONFIG.ENABLE_ADVANCED_OPTIONS {1}] $axi_mem_interconnect
set_property -dict [list CONFIG.XBAR_DATA_WIDTH {512}] $axi_mem_interconnect
set_property -dict [list CONFIG.STRATEGY {2}] $axi_mem_interconnect
set_property -dict [list CONFIG.M00_HAS_REGSLICE {4}] $axi_mem_interconnect
# instance: default peripherals

17
projects/common/kcu105/kcu105_system_constr.xdc
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@ -10,13 +10,10 @@ set_false_path -through [get_ports sys_rst]
set_property -dict {PACKAGE_PIN AK17 IOSTANDARD DIFF_SSTL12} [get_ports sys_clk_p]
set_property -dict {PACKAGE_PIN AK16 IOSTANDARD DIFF_SSTL12} [get_ports sys_clk_n]
create_clock -name sys_clk -period 3.33 [get_ports sys_clk_p]
set_property -dict {PACKAGE_PIN P26 IOSTANDARD LVDS_25} [get_ports phy_clk_p]
set_property -dict {PACKAGE_PIN N26 IOSTANDARD LVDS_25} [get_ports phy_clk_n]
create_clock -name phy_clk -period 1.60 [get_ports phy_clk_p]
# ethernet
set_property -dict {PACKAGE_PIN L25 IOSTANDARD LVCMOS18} [get_ports mdio_mdc]
@ -90,17 +87,3 @@ set_property -dict {PACKAGE_PIN AJ11 IOSTANDARD LVCMOS18} [get_ports hdmi_da
set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVCMOS18} [get_ports spdif]
# clocks
#create_clock -name mem_clk -period 5.00 [get_pins i_system_wrapper/system_i/axi_ddr_cntrl/c0_ddr4_ui_clk]
create_clock -name cpu_clk -period 10.00 [get_pins i_system_wrapper/system_i/axi_ddr_cntrl/addn_ui_clkout1]
create_clock -name m200_clk -period 5.00 [get_pins i_system_wrapper/system_i/axi_ddr_cntrl/addn_ui_clkout2]
create_clock -name hdmi_clk -period 6.73 [get_pins i_system_wrapper/system_i/axi_hdmi_clkgen/clk_0]
create_clock -name spdif_clk -period 50.00 [get_pins i_system_wrapper/system_i/sys_audio_clkgen/clk_out1]
#set_clock_groups -asynchronous -group {mem_clk}
set_clock_groups -asynchronous -group {cpu_clk}
set_clock_groups -asynchronous -group {m200_clk}
set_clock_groups -asynchronous -group {hdmi_clk}
set_clock_groups -asynchronous -group {spdif_clk}

2
projects/daq2/kcu105/system_bd.tcl
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@ -161,6 +161,8 @@ if {$sys_zynq == 0} {
if {$sys_zynq == 0} {
set_property -dict [list CONFIG.NUM_SI {11}] $axi_mem_interconnect
set_property -dict [list CONFIG.S09_HAS_REGSLICE {4}] $axi_mem_interconnect
set_property -dict [list CONFIG.S10_HAS_REGSLICE {4}] $axi_mem_interconnect
set_property -dict [list CONFIG.NUM_PORTS {7}] $sys_concat_intc
}

35
projects/daq2/kcu105/system_constr.xdc
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@ -3,29 +3,30 @@
set_property -dict {PACKAGE_PIN H6} [get_ports rx_ref_clk_p] ; ## B20 FMC_HPC_GBTCLK1_M2C_P
set_property -dict {PACKAGE_PIN H5} [get_ports rx_ref_clk_n] ; ## B21 FMC_HPC_GBTCLK1_M2C_N
set_property -dict {PACKAGE_PIN E4} [get_ports rx_data_p[0]] ; ## C06 FMC_HPC_DP0_M2C_P
set_property -dict {PACKAGE_PIN E3} [get_ports rx_data_n[0]] ; ## C07 FMC_HPC_DP0_M2C_N
set_property -dict {PACKAGE_PIN D2} [get_ports rx_data_p[1]] ; ## A02 FMC_HPC_DP1_M2C_P
set_property -dict {PACKAGE_PIN D1} [get_ports rx_data_n[1]] ; ## A03 FMC_HPC_DP1_M2C_N
set_property -dict {PACKAGE_PIN A4} [get_ports rx_data_p[0]] ; ## A10 FMC_HPC_DP3_M2C_P
set_property -dict {PACKAGE_PIN A3} [get_ports rx_data_n[0]] ; ## A11 FMC_HPC_DP3_M2C_N
set_property -dict {PACKAGE_PIN E4} [get_ports rx_data_p[1]] ; ## C06 FMC_HPC_DP0_M2C_P
set_property -dict {PACKAGE_PIN E3} [get_ports rx_data_n[1]] ; ## C07 FMC_HPC_DP0_M2C_N
set_property -dict {PACKAGE_PIN B2} [get_ports rx_data_p[2]] ; ## A06 FMC_HPC_DP2_M2C_P
set_property -dict {PACKAGE_PIN B1} [get_ports rx_data_n[2]] ; ## A07 FMC_HPC_DP2_M2C_N
set_property -dict {PACKAGE_PIN A4} [get_ports rx_data_p[3]] ; ## A10 FMC_HPC_DP3_M2C_P
set_property -dict {PACKAGE_PIN A3} [get_ports rx_data_n[3]] ; ## A11 FMC_HPC_DP3_M2C_N
set_property -dict {PACKAGE_PIN D2} [get_ports rx_data_p[3]] ; ## A02 FMC_HPC_DP1_M2C_P
set_property -dict {PACKAGE_PIN D1} [get_ports rx_data_n[3]] ; ## A03 FMC_HPC_DP1_M2C_N
set_property -dict {PACKAGE_PIN G9 IOSTANDARD LVDS} [get_ports rx_sync_p] ; ## D08 FMC_HPC_LA01_CC_P
set_property -dict {PACKAGE_PIN F9 IOSTANDARD LVDS} [get_ports rx_sync_n] ; ## D09 FMC_HPC_LA01_CC_N
set_property -dict {PACKAGE_PIN A13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_sysref_p] ; ## G09 FMC_HPC_LA03_P
set_property -dict {PACKAGE_PIN A12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_sysref_n] ; ## G10 FMC_HPC_LA03_N
set_property -dict {PACKAGE_PIN K6} [get_ports tx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P
set_property -dict {PACKAGE_PIN K5} [get_ports tx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N
set_property -dict {PACKAGE_PIN F6} [get_ports tx_data_p[0]] ; ## C02 FMC_HPC_DP0_C2M_P
set_property -dict {PACKAGE_PIN F5} [get_ports tx_data_n[0]] ; ## C03 FMC_HPC_DP0_C2M_N
set_property -dict {PACKAGE_PIN D6} [get_ports tx_data_p[1]] ; ## A22 FMC_HPC_DP1_C2M_P
set_property -dict {PACKAGE_PIN D5} [get_ports tx_data_n[1]] ; ## A23 FMC_HPC_DP1_C2M_N
set_property -dict {PACKAGE_PIN C4} [get_ports tx_data_p[2]] ; ## A26 FMC_HPC_DP2_C2M_P
set_property -dict {PACKAGE_PIN C3} [get_ports tx_data_n[2]] ; ## A27 FMC_HPC_DP2_C2M_N
set_property -dict {PACKAGE_PIN B6} [get_ports tx_data_p[3]] ; ## A30 FMC_HPC_DP3_C2M_P
set_property -dict {PACKAGE_PIN B5} [get_ports tx_data_n[3]] ; ## A31 FMC_HPC_DP3_C2M_N
set_property -dict {PACKAGE_PIN B6} [get_ports tx_data_p[0]] ; ## A30 FMC_HPC_DP3_C2M_P
set_property -dict {PACKAGE_PIN B5} [get_ports tx_data_n[0]] ; ## A31 FMC_HPC_DP3_C2M_N
set_property -dict {PACKAGE_PIN C4} [get_ports tx_data_p[1]] ; ## A26 FMC_HPC_DP2_C2M_P
set_property -dict {PACKAGE_PIN C3} [get_ports tx_data_n[1]] ; ## A27 FMC_HPC_DP2_C2M_N
set_property -dict {PACKAGE_PIN D6} [get_ports tx_data_p[2]] ; ## A22 FMC_HPC_DP1_C2M_P
set_property -dict {PACKAGE_PIN D5} [get_ports tx_data_n[2]] ; ## A23 FMC_HPC_DP1_C2M_N
set_property -dict {PACKAGE_PIN F6} [get_ports tx_data_p[3]] ; ## C02 FMC_HPC_DP0_C2M_P
set_property -dict {PACKAGE_PIN F5} [get_ports tx_data_n[3]] ; ## C03 FMC_HPC_DP0_C2M_N
set_property -dict {PACKAGE_PIN K10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports tx_sync_p] ; ## H07 FMC_HPC_LA02_P
set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports tx_sync_n] ; ## H08 FMC_HPC_LA02_N
set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports tx_sysref_p] ; ## H10 FMC_HPC_LA04_P
@ -60,9 +61,3 @@ create_clock -name rx_div_clk -period 4.00 [get_nets i_system_wrapper/system_
set_clock_groups -asynchronous -group {tx_div_clk}
set_clock_groups -asynchronous -group {rx_div_clk}
set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_drp_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_gt_pll_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_gt_rx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_gt_tx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_rx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_tx_rst_reg/i_rst_reg/PRE]