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util_sigma_delta_spi: Fix syntax

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sergiu arpadi 2020-10-08 13:02:39 +03:00 committed by sarpadi
parent 1f6bba0aa1
commit b44df7a1e9
1 changed files with 7 additions and 7 deletions
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14
library/util_sigma_delta_spi/util_sigma_delta_spi.v
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@ -35,7 +35,12 @@
`timescale 1ns/100ps
module util_sigma_delta_spi (
module util_sigma_delta_spi #(
parameter NUM_OF_CS = 1,
parameter CS_PIN = 0,
parameter IDLE_TIMEOUT = 63 ) (
input clk,
input resetn,
@ -53,12 +58,7 @@ module util_sigma_delta_spi (
input m_sdi,
output [NUM_OF_CS-1:0] m_cs,
output reg data_ready
);
parameter NUM_OF_CS = 1;
parameter CS_PIN = 0;
parameter IDLE_TIMEOUT = 63;
output reg data_ready);
/*
* For converters from the ADI SigmaDelta family the data ready interrupt signal