From b44df7a1e94a044e37fb514e6ac74f92829ac877 Mon Sep 17 00:00:00 2001 From: sergiu arpadi Date: Thu, 8 Oct 2020 13:02:39 +0300 Subject: [PATCH] util_sigma_delta_spi: Fix syntax --- .../util_sigma_delta_spi/util_sigma_delta_spi.v | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/library/util_sigma_delta_spi/util_sigma_delta_spi.v b/library/util_sigma_delta_spi/util_sigma_delta_spi.v index 8244b30da..e4dac4886 100644 --- a/library/util_sigma_delta_spi/util_sigma_delta_spi.v +++ b/library/util_sigma_delta_spi/util_sigma_delta_spi.v @@ -35,7 +35,12 @@ `timescale 1ns/100ps -module util_sigma_delta_spi ( +module util_sigma_delta_spi #( + + parameter NUM_OF_CS = 1, + parameter CS_PIN = 0, + parameter IDLE_TIMEOUT = 63 ) ( + input clk, input resetn, @@ -53,12 +58,7 @@ module util_sigma_delta_spi ( input m_sdi, output [NUM_OF_CS-1:0] m_cs, - output reg data_ready -); - -parameter NUM_OF_CS = 1; -parameter CS_PIN = 0; -parameter IDLE_TIMEOUT = 63; + output reg data_ready); /* * For converters from the ADI SigmaDelta family the data ready interrupt signal