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change pl ddr clock to 1G

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Rejeesh Kutty 2017-05-01 09:34:45 -04:00
parent d29f420ffa
commit b3ce821311
2 changed files with 3 additions and 3 deletions
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2
projects/adrv9371x/a10soc/system_constr.sdc
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@ -5,7 +5,7 @@ create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}
create_clock -period "8.139 ns" -name ref_clk0_122mhz [get_ports {ref_clk0}]
create_clock -period "8.139 ns" -name ref_clk1_122mhz [get_ports {ref_clk1}]
create_clock -period "7.503 ns" -name hps_ddr_ref_clk_133mhz [get_ports {hps_ddr_ref_clk}]
create_clock -period "10.000 ns" -name sys_ddr_ref_clk_100mhz [get_ports {sys_ddr_ref_clk}]
create_clock -period "7.503 ns" -name sys_ddr_ref_clk_133mhz [get_ports {sys_ddr_ref_clk}]
derive_pll_clocks
derive_clock_uncertainty

4
projects/common/a10soc/a10soc_plddr4_dacfifo_qsys.tcl
View File

@ -3,9 +3,9 @@
add_instance sys_ddr4_cntrl altera_emif 16.0
set_instance_parameter_value sys_ddr4_cntrl {PROTOCOL_ENUM} {PROTOCOL_DDR4}
set_instance_parameter_value sys_ddr4_cntrl {PHY_DDR4_MEM_CLK_FREQ_MHZ} {800.0}
set_instance_parameter_value sys_ddr4_cntrl {PHY_DDR4_MEM_CLK_FREQ_MHZ} {1066.667}
set_instance_parameter_value sys_ddr4_cntrl {PHY_DDR4_DEFAULT_REF_CLK_FREQ} {0}
set_instance_parameter_value sys_ddr4_cntrl {PHY_DDR4_USER_REF_CLK_FREQ_MHZ} {100.0}
set_instance_parameter_value sys_ddr4_cntrl {PHY_DDR4_USER_REF_CLK_FREQ_MHZ} {133.333}
set_instance_parameter_value sys_ddr4_cntrl {PHY_DDR4_RATE_ENUM} {RATE_QUARTER}
set_instance_parameter_value sys_ddr4_cntrl {MEM_DDR4_FORMAT_ENUM} {MEM_FORMAT_UDIMM}
set_instance_parameter_value sys_ddr4_cntrl {MEM_DDR4_DQ_WIDTH} {64}