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util_sync_reset: Fix polarity of the sync_resetn signal 

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2014-03-25 13:02:36 +01:00
parent a230e6505a
commit b3657b77cb
1 changed files with 4 additions and 5 deletions
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9
library/util_sync_reset/util_sync_reset.v
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@ -1,5 +1,4 @@
module util_sync_reset (
input async_resetn,
input clk,
@ -7,15 +6,15 @@ module util_sync_reset (
);
// Keep it asserted for three clock cycles
reg [2:0] reset = 3'b111;
reg [2:0] resetn = 3'b000;
assign sync_resetn = reset[2];
assign sync_resetn = resetn[2];
always @(posedge clk or negedge async_resetn) begin
if (async_resetn == 1'b0) begin
reset <= 3'b111;
resetn <= 3'b000;
end else begin
reset <= {reset[1:0], 1'b0};
resetn <= {resetn[1:0], 1'b1};
end
end