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hdmi_rx: imageon updates

main
Rejeesh Kutty 2015-03-24 12:30:21 -04:00
parent ffe410b2dd
commit b29e97f985
1 changed files with 194 additions and 191 deletions
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385
library/common/up_hdmi_rx.v
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@ -34,8 +34,6 @@
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE PoosIBILITY OF SUCH DAMAGE. // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE PoosIBILITY OF SUCH DAMAGE.
// *************************************************************************** // ***************************************************************************
// *************************************************************************** // ***************************************************************************
// ***************************************************************************
// ***************************************************************************
module up_hdmi_rx ( module up_hdmi_rx (
@ -43,26 +41,23 @@ module up_hdmi_rx (
hdmi_clk, hdmi_clk,
hdmi_rst, hdmi_rst,
hdmi_edge_sel,
hdmi_up_edge_sel, hdmi_bgr,
hdmi_up_hs_count, hdmi_packed,
hdmi_up_vs_count, hdmi_csc_bypass,
hdmi_up_csc_bypass, hdmi_tpg_enable,
hdmi_up_tpg_enable, hdmi_vs_count,
hdmi_up_packed, hdmi_hs_count,
hdmi_up_bgr, hdmi_dma_ovf,
hdmi_dma_unf,
hdmi_tpm_oos, hdmi_tpm_oos,
hdmi_hs_mismatch, hdmi_vs_oos,
hdmi_hs, hdmi_hs_oos,
hdmi_vs_mismatch, hdmi_vs_mismatch,
hdmi_hs_mismatch,
hdmi_vs, hdmi_vs,
hdmi_oos_hs, hdmi_hs,
hdmi_oos_vs, hdmi_clk_ratio,
// dma fifo overflow
dma_ovf,
// bus interface // bus interface
@ -79,114 +74,118 @@ module up_hdmi_rx (
// parameters // parameters
localparam PCORE_VERSION = 32'h00040063; localparam PCORE_VERSION = 32'h00040063;
parameter PCORE_ID = 0; parameter PCORE_ID = 0;
// hdmi interface // hdmi interface
input hdmi_clk; input hdmi_clk;
output hdmi_rst; output hdmi_rst;
output hdmi_edge_sel;
output hdmi_up_edge_sel; output hdmi_bgr;
output [15:0] hdmi_up_hs_count; output hdmi_packed;
output [15:0] hdmi_up_vs_count; output hdmi_csc_bypass;
output hdmi_up_csc_bypass; output hdmi_tpg_enable;
output hdmi_up_tpg_enable; output [15:0] hdmi_vs_count;
output hdmi_up_packed; output [15:0] hdmi_hs_count;
output hdmi_up_bgr; input hdmi_dma_ovf;
input hdmi_dma_unf;
input hdmi_tpm_oos; input hdmi_tpm_oos;
input hdmi_vs_oos;
// vdma interface input hdmi_hs_oos;
input hdmi_vs_mismatch;
input dma_ovf; input hdmi_hs_mismatch;
input hdmi_hs_mismatch; input [15:0] hdmi_vs;
input [15:0] hdmi_hs; input [15:0] hdmi_hs;
input hdmi_vs_mismatch; input [31:0] hdmi_clk_ratio;
input [15:0] hdmi_vs;
input hdmi_oos_hs;
input hdmi_oos_vs;
// bus interface // bus interface
input up_rstn; input up_rstn;
input up_clk; input up_clk;
input up_wreq; input up_wreq;
input [13:0] up_waddr; input [13:0] up_waddr;
input [31:0] up_wdata; input [31:0] up_wdata;
output up_wack; output up_wack;
input up_rreq; input up_rreq;
input [13:0] up_raddr; input [13:0] up_raddr;
output [31:0] up_rdata; output [31:0] up_rdata;
output up_rack; output up_rack;
// internal registers // internal registers
reg up_wack = 'd0; reg up_wack = 'd0;
reg up_rack = 'd0; reg [31:0] up_scratch = 'd0;
reg [31:0] up_rdata = 'd0; reg up_resetn = 'd0;
reg up_packed = 'd0; reg up_edge_sel = 'd0;
reg [31:0] up_scratch = 'd0; reg up_bgr = 'd0;
reg up_bgr = 'd0; reg up_packed = 'd0;
reg up_tpg_enable = 'd0; reg up_csc_bypass = 'd0;
reg up_csc_bypass = 'd0; reg up_tpg_enable = 'd0;
reg up_edge_sel = 'd0; reg up_dma_ovf = 'd0;
reg up_resetn = 'd0; reg up_dma_unf = 'd0;
reg [15:0] up_vs_count = 'd0; reg up_tpm_oos = 'd0;
reg [15:0] up_hs_count = 'd0; reg up_vs_oos = 'd0;
reg [ 3:0] up_hdmi_status_hold = 'd0; reg up_hs_oos = 'd0;
reg up_status = 'd0; reg up_vs_mismatch = 'd0;
reg up_dma_ovf_hold = 'd0; reg up_hs_mismatch = 'd0;
reg up_hdmi_tpm_oos_hold = 'd0; reg [15:0] up_vs_count = 'd0;
reg [15:0] up_hs_count = 'd0;
reg up_rack = 'd0;
reg [31:0] up_rdata = 'd0;
// internal signals // internal signals
wire up_wreq_s; wire up_wreq_s;
wire up_rreq_s; wire up_rreq_s;
wire up_preset_s; wire up_preset_s;
wire up_hdmi_hs_mismatch; wire up_dma_ovf_s;
wire [15:0] up_hdmi_hs; wire up_dma_unf_s;
wire up_hdmi_vs_mismatch; wire up_vs_oos_s;
wire [15:0] up_hdmi_vs; wire up_hs_oos_s;
wire up_hdmi_oos_hs; wire up_vs_mismatch_s;
wire up_hdmi_oos_vs; wire up_hs_mismatch_s;
wire [15:0] up_vs_s;
wire [3:0] up_hdmi_status = {up_hdmi_oos_vs, up_hdmi_oos_hs, up_hdmi_vs_mismatch, up_hdmi_hs_mismatch}; wire [15:0] up_hs_s;
wire [31:0] up_clk_count_s;
wire up_dma_ovf;
// decode block select // decode block select
assign up_wreq_s = (up_waddr[13:12] == 2'd0) ? up_wreq : 1'b0; assign up_wreq_s = (up_waddr[13:12] == 2'd0) ? up_wreq : 1'b0;
assign up_rreq_s = (up_raddr[13:12] == 2'd0) ? up_rreq : 1'b0; assign up_rreq_s = (up_raddr[13:12] == 2'd0) ? up_rreq : 1'b0;
assign up_preset_s = ~up_resetn; assign up_preset_s = ~up_resetn;
// processor write interface (see regmap.txt for details) // processor write interface
always @(negedge up_rstn or posedge up_clk) begin always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin if (up_rstn == 0) begin
up_wack <= 'd0; up_wack <= 'd0;
up_scratch <= 'd0; up_scratch <= 'd0;
up_packed <= 'd0; up_resetn <= 'd0;
up_bgr <= 'd0; up_edge_sel <= 'd0;
up_tpg_enable <= 'd0; up_bgr <= 'd0;
up_packed <= 'd0;
up_csc_bypass <= 'd0; up_csc_bypass <= 'd0;
up_edge_sel <= 'd0; up_tpg_enable <= 'd0;
up_resetn <= 'd0; up_dma_ovf <= 'd0;
up_vs_count <= 'd0; up_dma_unf <= 'd0;
up_hs_count <= 'd0; up_tpm_oos <= 'd0;
up_hdmi_status_hold <= 'd0; up_vs_oos <= 'd0;
up_status <= 'd0; up_hs_oos <= 'd0;
up_vs_mismatch <= 'd0;
up_hs_mismatch <= 'd0;
up_vs_count <= 'd0;
up_hs_count <= 'd0;
end else begin end else begin
up_wack <= up_wreq_s; up_wack <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h002)) begin if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h002)) begin
up_scratch <= up_wdata; up_scratch <= up_wdata;
end end
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h010)) begin if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h010)) begin
up_resetn <= up_wdata[0]; up_resetn <= up_wdata[0];
end end
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h011)) begin if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h011)) begin
up_edge_sel = up_wdata[3]; up_edge_sel <= up_wdata[3];
up_bgr <= up_wdata[2]; up_bgr <= up_wdata[2];
up_packed <= up_wdata[1]; up_packed <= up_wdata[1];
up_csc_bypass <= up_wdata[0]; up_csc_bypass <= up_wdata[0];
@ -194,25 +193,45 @@ module up_hdmi_rx (
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h012)) begin if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h012)) begin
up_tpg_enable <= up_wdata[0]; up_tpg_enable <= up_wdata[0];
end end
if (up_dma_ovf_s == 1'b1) begin
up_dma_ovf <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h018)) begin
up_dma_ovf <= up_dma_ovf & ~up_wdata[1];
end
if (up_dma_unf_s == 1'b1) begin
up_dma_unf <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h018)) begin
up_dma_unf <= up_dma_unf & ~up_wdata[0];
end
if (up_tpm_oos_s == 1'b1) begin
up_tpm_oos <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h019)) begin
up_tpm_oos <= up_tpm_oos & ~up_wdata[0];
end
if (up_vs_oos_s == 1'b1) begin
up_vs_oos <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h020)) begin
up_vs_oos <= up_vs_oos & ~up_wdata[3];
end
if (up_hs_oos_s == 1'b1) begin
up_hs_oos <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h020)) begin
up_hs_oos <= up_hs_oos & ~up_wdata[2];
end
if (up_vs_mismatch_s == 1'b1) begin
up_vs_mismatch <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h020)) begin
up_vs_mismatch <= up_vs_mismatch & ~up_wdata[1];
end
if (up_hs_mismatch_s == 1'b1) begin
up_hs_mismatch <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h020)) begin
up_hs_mismatch <= up_hs_mismatch & ~up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h100)) begin if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h100)) begin
up_vs_count <= up_wdata[31:16]; up_vs_count <= up_wdata[31:16];
up_hs_count <= up_wdata[15:0]; up_hs_count <= up_wdata[15:0];
end end
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h018)) begin
up_dma_ovf_hold <= (up_dma_ovf_hold & ~up_wdata[0]) | up_dma_ovf;
end else begin
up_dma_ovf_hold <= up_dma_ovf_hold | up_dma_ovf;
end
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h019)) begin
up_hdmi_tpm_oos_hold <= (up_hdmi_tpm_oos_hold & ~up_wdata[0]) | up_hdmi_tpm_oos;
end else begin
up_hdmi_tpm_oos_hold <= up_hdmi_tpm_oos_hold | up_hdmi_tpm_oos;
end
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h020)) begin
up_hdmi_status_hold <= (up_hdmi_status_hold & ~up_wdata[3:0]) | up_hdmi_status;
end else begin
up_hdmi_status_hold <= up_hdmi_status_hold | up_hdmi_status;
end
end end
end end
@ -232,11 +251,14 @@ module up_hdmi_rx (
12'h010: up_rdata <= {31'h0, up_resetn}; 12'h010: up_rdata <= {31'h0, up_resetn};
12'h011: up_rdata <= {29'h0, up_bgr, up_packed, up_csc_bypass}; 12'h011: up_rdata <= {29'h0, up_bgr, up_packed, up_csc_bypass};
12'h012: up_rdata <= {31'h0, up_tpg_enable}; 12'h012: up_rdata <= {31'h0, up_tpg_enable};
12'h018: up_rdata <= {30'h0, up_dma_ovf_hold, 1'b0}; 12'h015: up_rdata <= up_clk_count_s;
12'h019: up_rdata <= {30'h0, up_hdmi_tpm_oos_hold, 1'b0}; 12'h016: up_rdata <= hdmi_clk_ratio;
12'h020: up_rdata <= {28'h0, up_hdmi_status_hold}; 12'h018: up_rdata <= {30'h0, up_dma_ovf, up_dma_unf};
12'h019: up_rdata <= {30'h0, up_tpm_oos, 1'b0};
12'h020: up_rdata <= {28'h0, up_vs_oos, up_hs_oos,
up_vs_mismatch, up_hs_mismatch};
12'h100: up_rdata <= {up_vs_count, up_hs_count}; 12'h100: up_rdata <= {up_vs_count, up_hs_count};
12'h101: up_rdata <= {up_hdmi_vs, up_hdmi_hs}; 12'h101: up_rdata <= {up_vs_s, up_hs_s};
default: up_rdata <= 0; default: up_rdata <= 0;
endcase endcase
end end
@ -244,86 +266,67 @@ module up_hdmi_rx (
end end
// resets // resets
ad_rst i_hdmi_rst_reg ( ad_rst i_hdmi_rst_reg (
.preset(up_preset_s), .preset (up_preset_s),
.clk(hdmi_clk), .clk (hdmi_clk),
.rst(hdmi_rst)); .rst (hdmi_rst));
// hdmi control & status // hdmi control & status
up_xfer_cntrl #( up_xfer_cntrl #(.DATA_WIDTH(37)) i_hdmi_xfer_cntrl (
.DATA_WIDTH(37) .up_rstn (up_rstn),
) i_hdmi_rx_xfer_cntrl ( .up_clk (up_clk),
.up_rstn(up_rstn), .up_data_cntrl ({ up_edge_sel,
.up_clk(up_clk), up_bgr,
.up_data_cntrl({ up_packed,
up_hs_count, up_csc_bypass,
up_vs_count, up_tpg_enable,
up_edge_sel, up_vs_count,
up_csc_bypass, up_hs_count}),
up_tpg_enable, .up_xfer_done (),
up_packed, .d_rst (hdmi_rst),
up_bgr .d_clk (hdmi_clk),
}), .d_data_cntrl ({ hdmi_edge_sel,
.up_xfer_done(), hdmi_bgr,
.d_rst(hdmi_rst), hdmi_packed,
.d_clk(hdmi_clk), hdmi_csc_bypass,
.d_data_cntrl({ hdmi_tpg_enable,
hdmi_up_hs_count, hdmi_vs_count,
hdmi_up_vs_count, hdmi_hs_count}));
hdmi_up_edge_sel,
hdmi_up_csc_bypass,
hdmi_up_tpg_enable,
hdmi_up_packed,
hdmi_up_bgr})
);
// Synchronize the detected horizontal/vertical resolution to the AXI clock domain. up_xfer_status #(.DATA_WIDTH(39)) i_hdmi_xfer_status (
// Synchronize status bits to the AXI clock domain .up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_status ({ up_dma_ovf_s,
up_dma_unf_s,
up_tpm_oos_s,
up_vs_oos_s,
up_hs_oos_s,
up_vs_mismatch_s,
up_hs_mismatch_s,
up_vs_s,
up_hs_s}),
.d_rst (hdmi_rst),
.d_clk (hdmi_clk),
.d_data_status ({ hdmi_dma_ovf,
hdmi_dma_unf,
hdmi_tpm_oos,
hdmi_vs_oos,
hdmi_hs_oos,
hdmi_vs_mismatch,
hdmi_hs_mismatch,
hdmi_vs,
hdmi_hs}));
up_xfer_status #( up_clock_mon i_hdmi_clock_mon (
.DATA_WIDTH(36) .up_rstn (up_rstn),
) i_hdmi_rx_xfer_status ( .up_clk (up_clk),
.up_rstn(up_rstn), .up_d_count (up_clk_count_s),
.up_clk(up_clk), .d_rst (hdmi_rst),
.up_data_status({ .d_clk (hdmi_clk));
up_hdmi_hs_mismatch,
up_hdmi_hs,
up_hdmi_vs_mismatch,
up_hdmi_vs,
up_hdmi_oos_hs,
up_hdmi_oos_vs}),
.d_rst(hdmi_rst),
.d_clk(hdmi_clk),
.d_data_status({
hdmi_hs_mismatch,
hdmi_hs,
hdmi_vs_mismatch,
hdmi_vs,
hdmi_oos_hs,
hdmi_oos_vs}));
up_xfer_status #(
.DATA_WIDTH(1)
) i_hdmi_tpm_xfer_status (
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_data_status(up_hdmi_tpm_oos),
.d_rst(hdmi_rst),
.d_clk(hdmi_clk),
.d_data_status(hdmi_tpm_oos));
// vdma status
up_xfer_status #(
.DATA_WIDTH(1)
) i_vdma_xfer_status (
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_data_status(up_dma_ovf),
.d_rst(hdmi_rst),
.d_clk(hdmi_clk),
.d_data_status(dma_ovf));
endmodule endmodule
// ***************************************************************************
// ***************************************************************************