axi_dacfifo: Update constraints
parent
b0b79013f7
commit
b2550b7aa0
|
@ -9,6 +9,7 @@ set_property ASYNC_REG TRUE \
|
||||||
[get_cells -hier *dac_bypass_m*]
|
[get_cells -hier *dac_bypass_m*]
|
||||||
|
|
||||||
set_false_path -to [get_cells -hier -filter {name =~ *_bypass_m1_reg && IS_SEQUENTIAL}]
|
set_false_path -to [get_cells -hier -filter {name =~ *_bypass_m1_reg && IS_SEQUENTIAL}]
|
||||||
|
set_false_path -to [get_cells -hier -filter {name =~ *dac_xfer_out_m1_reg && IS_SEQUENTIAL}]
|
||||||
set_false_path -to [get_cells -hier -filter {name =~ *_xfer_req_m_reg[0]* && IS_SEQUENTIAL}]
|
set_false_path -to [get_cells -hier -filter {name =~ *_xfer_req_m_reg[0]* && IS_SEQUENTIAL}]
|
||||||
|
|
||||||
set_false_path -from [get_cells -hier -filter {name =~ *dma_* && IS_SEQUENTIAL}] \
|
set_false_path -from [get_cells -hier -filter {name =~ *dma_* && IS_SEQUENTIAL}] \
|
||||||
|
|
Loading…
Reference in New Issue