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axi_dacfifo: Update constraints

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Istvan Csomortani 2017-08-18 10:39:22 +01:00
parent b0b79013f7
commit b2550b7aa0
1 changed files with 1 additions and 0 deletions
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library/xilinx/axi_dacfifo/axi_dacfifo_constr.xdc
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@ -9,6 +9,7 @@ set_property ASYNC_REG TRUE \
[get_cells -hier *dac_bypass_m*]
set_false_path -to [get_cells -hier -filter {name =~ *_bypass_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *dac_xfer_out_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *_xfer_req_m_reg[0]* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *dma_* && IS_SEQUENTIAL}] \