diff --git a/projects/ad9081_fmca_ebz/vcu118/Makefile b/projects/ad9081_fmca_ebz/vcu118/Makefile new file mode 100644 index 000000000..5e50771b1 --- /dev/null +++ b/projects/ad9081_fmca_ebz/vcu118/Makefile @@ -0,0 +1,34 @@ +#################################################################################### +## Copyright 2018(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := ad9081_fmca_ebz_vcu118 + +M_DEPS += timing_constr.xdc +M_DEPS += ../common/ad9081_fmca_ebz_bd.tcl +M_DEPS += ../../common/xilinx/dacfifo_bd.tcl +M_DEPS += ../../common/xilinx/adcfifo_bd.tcl +M_DEPS += ../../common/vcu118/vcu118_system_constr.xdc +M_DEPS += ../../common/vcu118/vcu118_system_bd.tcl +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v +M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl +M_DEPS += ../../../library/common/ad_3w_spi.v + +LIB_DEPS += axi_dmac +LIB_DEPS += axi_sysid +LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc +LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac +LIB_DEPS += jesd204/axi_jesd204_rx +LIB_DEPS += jesd204/axi_jesd204_tx +LIB_DEPS += jesd204/jesd204_rx +LIB_DEPS += jesd204/jesd204_tx +LIB_DEPS += sysid_rom +LIB_DEPS += util_adcfifo +LIB_DEPS += util_dacfifo +LIB_DEPS += util_pack/util_cpack2 +LIB_DEPS += util_pack/util_upack2 +LIB_DEPS += xilinx/axi_adxcvr +LIB_DEPS += xilinx/util_adxcvr + +include ../../scripts/project-xilinx.mk diff --git a/projects/ad9081_fmca_ebz/vcu118/system_bd.tcl b/projects/ad9081_fmca_ebz/vcu118/system_bd.tcl new file mode 100644 index 000000000..8ce2f58e7 --- /dev/null +++ b/projects/ad9081_fmca_ebz/vcu118/system_bd.tcl @@ -0,0 +1,62 @@ + +## ADC FIFO depth in samples per converter +set adc_fifo_samples_per_converter [expr 64*1024] +## DAC FIFO depth in samples per converter +set dac_fifo_samples_per_converter [expr 64*1024] + + +source $ad_hdl_dir/projects/common/vcu118/vcu118_system_bd.tcl +source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl +source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl +source ../common/ad9081_fmca_ebz_bd.tcl + +ad_ip_parameter axi_mxfe_rx_jesd/rx CONFIG.NUM_INPUT_PIPELINE 2 +ad_ip_parameter axi_mxfe_tx_jesd/tx CONFIG.NUM_OUTPUT_PIPELINE 1 + +#system ID +ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 +ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt" +ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 +set sys_cstring "sys rom custom string placeholder" +sysid_gen_sys_init_file $sys_cstring + +if {$ad_project_params(JESD_MODE) == "8B10B"} { +# Parameters for 15.5Gpbs lane rate + +ad_ip_parameter util_mxfe_xcvr CONFIG.RX_CLK25_DIV 31 +ad_ip_parameter util_mxfe_xcvr CONFIG.TX_CLK25_DIV 31 +ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_CFG0 0x1fa +ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_CFG1 0x2b +ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_CFG2 0x2 +ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_FBDIV 2 +ad_ip_parameter util_mxfe_xcvr CONFIG.CH_HSPMUX 0x4040 +ad_ip_parameter util_mxfe_xcvr CONFIG.PREIQ_FREQ_BST 1 +ad_ip_parameter util_mxfe_xcvr CONFIG.RTX_BUF_CML_CTRL 0x5 +ad_ip_parameter util_mxfe_xcvr CONFIG.RXPI_CFG0 0x3002 +ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG2 0x1E9 +ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3 0x23 +ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN2 0x23 +ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN3 0x23 +ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN4 0x23 +ad_ip_parameter util_mxfe_xcvr CONFIG.RX_WIDEMODE_CDR 0x1 +ad_ip_parameter util_mxfe_xcvr CONFIG.RX_XMODE_SEL 0x0 +ad_ip_parameter util_mxfe_xcvr CONFIG.TXDRV_FREQBAND 1 +ad_ip_parameter util_mxfe_xcvr CONFIG.TXFE_CFG1 0xAA00 +ad_ip_parameter util_mxfe_xcvr CONFIG.TXFE_CFG2 0xAA00 +ad_ip_parameter util_mxfe_xcvr CONFIG.TXFE_CFG3 0xAA00 +ad_ip_parameter util_mxfe_xcvr CONFIG.TXPI_CFG0 0x3100 +ad_ip_parameter util_mxfe_xcvr CONFIG.TXPI_CFG1 0x0 +ad_ip_parameter util_mxfe_xcvr CONFIG.TX_PI_BIASSET 1 + +ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_REFCLK_DIV 1 +ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CFG0 0x333c +ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CFG4 0x2 +ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_FBDIV 20 +ad_ip_parameter util_mxfe_xcvr CONFIG.PPF0_CFG 0xB00 +ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_LPF 0x2ff +} else { + set_property -dict [list CONFIG.ADDN_UI_CLKOUT4_FREQ_HZ {50}] [get_bd_cells axi_ddr_cntrl] + ad_connect /axi_ddr_cntrl/addn_ui_clkout4 jesd204_phy_121/drpclk + ad_connect /axi_ddr_cntrl/addn_ui_clkout4 jesd204_phy_126/drpclk +} + diff --git a/projects/ad9081_fmca_ebz/vcu118/system_constr.xdc b/projects/ad9081_fmca_ebz/vcu118/system_constr.xdc new file mode 100644 index 000000000..6435ea113 --- /dev/null +++ b/projects/ad9081_fmca_ebz/vcu118/system_constr.xdc @@ -0,0 +1,94 @@ +# +## mxfe +# + +set_property -dict {PACKAGE_PIN R34 IOSTANDARD LVCMOS18 } [get_ports agc0[0] ] ; ## IO_L13P_T2L_N0_GC_QBC_45 +set_property -dict {PACKAGE_PIN P34 IOSTANDARD LVCMOS18 } [get_ports agc0[1] ] ; ## IO_L13N_T2L_N1_GC_QBC_45 +set_property -dict {PACKAGE_PIN R31 IOSTANDARD LVCMOS18 } [get_ports agc1[0] ] ; ## IO_L10P_T1U_N6_QBC_AD4P_45 +set_property -dict {PACKAGE_PIN P31 IOSTANDARD LVCMOS18 } [get_ports agc1[1] ] ; ## IO_L10N_T1U_N7_QBC_AD4N_45 +set_property -dict {PACKAGE_PIN N32 IOSTANDARD LVCMOS18 } [get_ports agc2[0] ] ; ## IO_L23P_T3U_N8_45 +set_property -dict {PACKAGE_PIN M32 IOSTANDARD LVCMOS18 } [get_ports agc2[1] ] ; ## IO_L23N_T3U_N9_45 +set_property -dict {PACKAGE_PIN M35 IOSTANDARD LVCMOS18 } [get_ports agc3[0] ] ; ## IO_L24P_T3U_N10_45 +set_property -dict {PACKAGE_PIN L35 IOSTANDARD LVCMOS18 } [get_ports agc3[1] ] ; ## IO_L24N_T3U_N11_45 +set_property -dict {PACKAGE_PIN P36 IOSTANDARD LVDS } [get_ports clkin6_n ] ; ## IO_L14N_T2L_N3_GC_45 +set_property -dict {PACKAGE_PIN P35 IOSTANDARD LVDS } [get_ports clkin6_p ] ; ## IO_L14P_T2L_N2_GC_45 +set_property -dict {PACKAGE_PIN AM39 } [get_ports clkin8_n ] ; ## MGTREFCLK1N_120 +set_property -dict {PACKAGE_PIN AM38 } [get_ports clkin8_p ] ; ## MGTREFCLK1P_120 +set_property -dict {PACKAGE_PIN AK39 } [get_ports fpga_refclk_in_n ] ; ## MGTREFCLK0N_121 +set_property -dict {PACKAGE_PIN AK38 } [get_ports fpga_refclk_in_p ] ; ## MGTREFCLK0P_121 +set_property -dict {PACKAGE_PIN V39 } [get_ports fpga_refclk_in_replica_n ] ; ## MGTREFCLK0N_126 +set_property -dict {PACKAGE_PIN V38 } [get_ports fpga_refclk_in_replica_p ] ; ## MGTREFCLK0P_126 +set_property -quiet -dict {PACKAGE_PIN AL46 } [get_ports rx_data_n[2] ] ; ## MGTYRXN2_121 FPGA_SERDIN_0_N +set_property -quiet -dict {PACKAGE_PIN AL45 } [get_ports rx_data_p[2] ] ; ## MGTYRXP2_121 FPGA_SERDIN_0_P +set_property -quiet -dict {PACKAGE_PIN AR46 } [get_ports rx_data_n[0] ] ; ## MGTYRXN0_121 FPGA_SERDIN_1_N +set_property -quiet -dict {PACKAGE_PIN AR45 } [get_ports rx_data_p[0] ] ; ## MGTYRXP0_121 FPGA_SERDIN_1_P +set_property -quiet -dict {PACKAGE_PIN N46 } [get_ports rx_data_n[7] ] ; ## MGTYRXN3_126 FPGA_SERDIN_2_N +set_property -quiet -dict {PACKAGE_PIN N45 } [get_ports rx_data_p[7] ] ; ## MGTYRXP3_126 FPGA_SERDIN_2_P +set_property -quiet -dict {PACKAGE_PIN R46 } [get_ports rx_data_n[6] ] ; ## MGTYRXN2_126 FPGA_SERDIN_3_N +set_property -quiet -dict {PACKAGE_PIN R45 } [get_ports rx_data_p[6] ] ; ## MGTYRXP2_126 FPGA_SERDIN_3_P +set_property -quiet -dict {PACKAGE_PIN U46 } [get_ports rx_data_n[5] ] ; ## MGTYRXN1_126 FPGA_SERDIN_4_N +set_property -quiet -dict {PACKAGE_PIN U45 } [get_ports rx_data_p[5] ] ; ## MGTYRXP1_126 FPGA_SERDIN_4_P +set_property -quiet -dict {PACKAGE_PIN W46 } [get_ports rx_data_n[4] ] ; ## MGTYRXN0_126 FPGA_SERDIN_5_N +set_property -quiet -dict {PACKAGE_PIN W45 } [get_ports rx_data_p[4] ] ; ## MGTYRXP0_126 FPGA_SERDIN_5_P +set_property -quiet -dict {PACKAGE_PIN AJ46 } [get_ports rx_data_n[3] ] ; ## MGTYRXN3_121 FPGA_SERDIN_6_N +set_property -quiet -dict {PACKAGE_PIN AJ45 } [get_ports rx_data_p[3] ] ; ## MGTYRXP3_121 FPGA_SERDIN_6_P +set_property -quiet -dict {PACKAGE_PIN AN46 } [get_ports rx_data_n[1] ] ; ## MGTYRXN1_121 FPGA_SERDIN_7_N +set_property -quiet -dict {PACKAGE_PIN AN45 } [get_ports rx_data_p[1] ] ; ## MGTYRXP1_121 FPGA_SERDIN_7_P +set_property -quiet -dict {PACKAGE_PIN AT43 } [get_ports tx_data_n[0] ] ; ## MGTYTXN0_121 FPGA_SERDOUT_0_N +set_property -quiet -dict {PACKAGE_PIN AT42 } [get_ports tx_data_p[0] ] ; ## MGTYTXP0_121 FPGA_SERDOUT_0_P +set_property -quiet -dict {PACKAGE_PIN AM43 } [get_ports tx_data_n[2] ] ; ## MGTYTXN2_121 FPGA_SERDOUT_1_N +set_property -quiet -dict {PACKAGE_PIN AM42 } [get_ports tx_data_p[2] ] ; ## MGTYTXP2_121 FPGA_SERDOUT_1_P +set_property -quiet -dict {PACKAGE_PIN K43 } [get_ports tx_data_n[7] ] ; ## MGTYTXN3_126 FPGA_SERDOUT_2_N +set_property -quiet -dict {PACKAGE_PIN K42 } [get_ports tx_data_p[7] ] ; ## MGTYTXP3_126 FPGA_SERDOUT_2_P +set_property -quiet -dict {PACKAGE_PIN M43 } [get_ports tx_data_n[6] ] ; ## MGTYTXN2_126 FPGA_SERDOUT_3_N +set_property -quiet -dict {PACKAGE_PIN M42 } [get_ports tx_data_p[6] ] ; ## MGTYTXP2_126 FPGA_SERDOUT_3_P +set_property -quiet -dict {PACKAGE_PIN AP43 } [get_ports tx_data_n[1] ] ; ## MGTYTXN1_121 FPGA_SERDOUT_4_N +set_property -quiet -dict {PACKAGE_PIN AP42 } [get_ports tx_data_p[1] ] ; ## MGTYTXP1_121 FPGA_SERDOUT_4_P +set_property -quiet -dict {PACKAGE_PIN P43 } [get_ports tx_data_n[5] ] ; ## MGTYTXN1_126 FPGA_SERDOUT_5_N +set_property -quiet -dict {PACKAGE_PIN P42 } [get_ports tx_data_p[5] ] ; ## MGTYTXP1_126 FPGA_SERDOUT_5_P +set_property -quiet -dict {PACKAGE_PIN T43 } [get_ports tx_data_n[4] ] ; ## MGTYTXN0_126 FPGA_SERDOUT_6_N +set_property -quiet -dict {PACKAGE_PIN T42 } [get_ports tx_data_p[4] ] ; ## MGTYTXP0_126 FPGA_SERDOUT_6_P +set_property -quiet -dict {PACKAGE_PIN AL41 } [get_ports tx_data_n[3] ] ; ## MGTYTXN3_121 FPGA_SERDOUT_7_N +set_property -quiet -dict {PACKAGE_PIN AL40 } [get_ports tx_data_p[3] ] ; ## MGTYTXP3_121 FPGA_SERDOUT_7_P +set_property -quiet -dict {PACKAGE_PIN AK32 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports fpga_syncin_n[0] ] ; ## IO_L14N_T2L_N3_GC_43 +set_property -quiet -dict {PACKAGE_PIN AJ32 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports fpga_syncin_p[0] ] ; ## IO_L14P_T2L_N2_GC_43 +set_property -quiet -dict {PACKAGE_PIN AT40 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports fpga_syncin_n[1] ] ; ## IO_L4N_T0U_N7_DBC_AD7N_43 +set_property -quiet -dict {PACKAGE_PIN AT39 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports fpga_syncin_p[1] ] ; ## IO_L4P_T0U_N6_DBC_AD7P_43 +set_property -quiet -dict {PACKAGE_PIN AL31 IOSTANDARD LVDS } [get_ports fpga_syncout_n[0] ] ; ## IO_L16N_T2U_N7_QBC_AD3N_43 +set_property -quiet -dict {PACKAGE_PIN AL30 IOSTANDARD LVDS } [get_ports fpga_syncout_p[0] ] ; ## IO_L16P_T2U_N6_QBC_AD3P_43 +set_property -quiet -dict {PACKAGE_PIN AT36 IOSTANDARD LVDS } [get_ports fpga_syncout_n[1] ] ; ## IO_L2N_T0L_N3_43 +set_property -quiet -dict {PACKAGE_PIN AT35 IOSTANDARD LVDS } [get_ports fpga_syncout_p[1] ] ; ## IO_L2P_T0L_N2_43 +set_property -dict {PACKAGE_PIN AG32 IOSTANDARD LVCMOS18 } [get_ports gpio[0] ] ; ## IO_L24P_T3U_N10_43 +set_property -dict {PACKAGE_PIN AG33 IOSTANDARD LVCMOS18 } [get_ports gpio[1] ] ; ## IO_L24N_T3U_N11_43 +set_property -dict {PACKAGE_PIN N33 IOSTANDARD LVCMOS18 } [get_ports gpio[2] ] ; ## IO_L22P_T3U_N6_DBC_AD0P_45 +set_property -dict {PACKAGE_PIN M33 IOSTANDARD LVCMOS18 } [get_ports gpio[3] ] ; ## IO_L22N_T3U_N7_DBC_AD0N_45 +set_property -dict {PACKAGE_PIN AJ35 IOSTANDARD LVCMOS18 } [get_ports gpio[4] ] ; ## IO_L20P_T3L_N2_AD1P_43 +set_property -dict {PACKAGE_PIN AJ36 IOSTANDARD LVCMOS18 } [get_ports gpio[5] ] ; ## IO_L20N_T3L_N3_AD1N_43 +set_property -dict {PACKAGE_PIN AG31 IOSTANDARD LVCMOS18 } [get_ports gpio[6] ] ; ## IO_L23P_T3U_N8_43 +set_property -dict {PACKAGE_PIN AH31 IOSTANDARD LVCMOS18 } [get_ports gpio[7] ] ; ## IO_L23N_T3U_N9_43 +set_property -dict {PACKAGE_PIN AG34 IOSTANDARD LVCMOS18 } [get_ports gpio[8] ] ; ## IO_L22P_T3U_N6_DBC_AD0P_43 +set_property -dict {PACKAGE_PIN AH35 IOSTANDARD LVCMOS18 } [get_ports gpio[9] ] ; ## IO_L22N_T3U_N7_DBC_AD0N_43 +set_property -dict {PACKAGE_PIN N35 IOSTANDARD LVCMOS18 } [get_ports gpio[10] ] ; ## IO_L20N_T3L_N3_AD1N_45 +set_property -dict {PACKAGE_PIN AJ31 IOSTANDARD LVCMOS18 } [get_ports hmc_gpio1 ] ; ## IO_L17N_T2U_N9_AD10N_43 +set_property -dict {PACKAGE_PIN AP37 IOSTANDARD LVCMOS18 } [get_ports hmc_sync ] ; ## IO_L5N_T0U_N9_AD14N_43 +set_property -dict {PACKAGE_PIN AK29 IOSTANDARD LVCMOS18 } [get_ports irqb[0] ] ; ## IO_L18P_T2U_N10_AD2P_43 +set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVCMOS18 } [get_ports irqb[1] ] ; ## IO_L18N_T2U_N11_AD2N_43 +set_property -dict {PACKAGE_PIN AP36 IOSTANDARD LVCMOS18 } [get_ports rstb ] ; ## IO_L5P_T0U_N8_AD14P_43 +set_property -dict {PACKAGE_PIN AP35 IOSTANDARD LVCMOS18 } [get_ports rxen[0] ] ; ## IO_L3P_T0L_N4_AD15P_43 +set_property -dict {PACKAGE_PIN AR35 IOSTANDARD LVCMOS18 } [get_ports rxen[1] ] ; ## IO_L3N_T0L_N5_AD15N_43 +set_property -dict {PACKAGE_PIN AP38 IOSTANDARD LVCMOS18 } [get_ports spi0_csb ] ; ## IO_L1P_T0L_N0_DBC_43 +set_property -dict {PACKAGE_PIN AR38 IOSTANDARD LVCMOS18 } [get_ports spi0_miso ] ; ## IO_L1N_T0L_N1_DBC_43 +set_property -dict {PACKAGE_PIN AR37 IOSTANDARD LVCMOS18 } [get_ports spi0_mosi ] ; ## IO_L6P_T0U_N10_AD6P_43 +set_property -dict {PACKAGE_PIN AT37 IOSTANDARD LVCMOS18 } [get_ports spi0_sclk ] ; ## IO_L6N_T0U_N11_AD6N_43 +set_property -dict {PACKAGE_PIN AH33 IOSTANDARD LVCMOS18 } [get_ports spi1_csb ] ; ## IO_L21P_T3L_N4_AD8P_43 +set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD LVCMOS18 } [get_ports spi1_sclk ] ; ## IO_L17P_T2U_N8_AD10P_43 +set_property -dict {PACKAGE_PIN AH34 IOSTANDARD LVCMOS18 } [get_ports spi1_sdio ] ; ## IO_L21N_T3L_N5_AD8N_43 +set_property -dict {PACKAGE_PIN AM32 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports sysref2_n ] ; ## IO_L13N_T2L_N1_GC_QBC_43 +set_property -dict {PACKAGE_PIN AL32 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports sysref2_p ] ; ## IO_L13P_T2L_N0_GC_QBC_43 +set_property -dict {PACKAGE_PIN AJ33 IOSTANDARD LVCMOS18 } [get_ports txen[0] ] ; ## IO_L19P_T3L_N0_DBC_AD9P_43 +set_property -dict {PACKAGE_PIN AK33 IOSTANDARD LVCMOS18 } [get_ports txen[1] ] ; ## IO_L19N_T3L_N1_DBC_AD9N_43 + +set_property -dict {PACKAGE_PIN AK35 IOSTANDARD LVCMOS18 PULLTYPE PULLUP } [get_ports vadj_1v8_pgood ] ; ## IO_T1U_N12_43_AK35 + + + diff --git a/projects/ad9081_fmca_ebz/vcu118/system_project.tcl b/projects/ad9081_fmca_ebz/vcu118/system_project.tcl new file mode 100644 index 000000000..21610cf28 --- /dev/null +++ b/projects/ad9081_fmca_ebz/vcu118/system_project.tcl @@ -0,0 +1,45 @@ + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +# get_env_param retrieves parameter value from the environment if exists, +# other case use the default value +# +# Use over-writable parameters from the environment. +# +# e.g. +# make JESD_MODE=64B66B RX_RATE=24.75 TX_RATE=12.375 REF_CLK_RATE=375 RX_JESD_L=4 TX_JESD_L=4 +# make JESD_MODE=64B66B RX_RATE=16.22016 TX_RATE=16.22016 REF_CLK_RATE=245.76 RX_JESD_M=8 RX_JESD_L=2 TX_JESD_M=16 TX_JESD_L=4 +# make JESD_MODE=8B10B RX_JESD_L=4 RX_JESD_M=8 TX_JESD_L=4 TX_JESD_M=8 + +# RX_RATE,TX_RATE,REF_CLK_RATE used only in 64B66B mode + +adi_project ad9081_fmca_ebz_vcu118 0 [list \ + JESD_MODE [get_env_param JESD_MODE 8B10B ] \ + RX_RATE [get_env_param RX_RATE 10 ] \ + TX_RATE [get_env_param TX_RATE 10 ] \ + REF_CLK_RATE [get_env_param REF_CLK_RATE 250 ] \ + RX_JESD_M [get_env_param RX_JESD_M 8 ] \ + RX_JESD_L [get_env_param RX_JESD_L 4 ] \ + RX_JESD_S [get_env_param RX_JESD_S 1 ] \ + RX_JESD_NP [get_env_param RX_JESD_NP 16 ] \ + RX_NUM_LINKS [get_env_param RX_NUM_LINKS 1 ] \ + TX_JESD_M [get_env_param TX_JESD_M 8 ] \ + TX_JESD_L [get_env_param TX_JESD_L 4 ] \ + TX_JESD_S [get_env_param TX_JESD_S 1 ] \ + TX_JESD_NP [get_env_param TX_JESD_NP 16 ] \ + TX_NUM_LINKS [get_env_param TX_NUM_LINKS 1 ] \ +] + +adi_project_files ad9081_fmca_ebz_vcu118 [list \ + "system_top.v" \ + "system_constr.xdc"\ + "timing_constr.xdc"\ + "../../../library/common/ad_3w_spi.v"\ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ + "$ad_hdl_dir/projects/common/vcu118/vcu118_system_constr.xdc" ] + + +adi_project_run ad9081_fmca_ebz_vcu118 + diff --git a/projects/ad9081_fmca_ebz/vcu118/system_top.v b/projects/ad9081_fmca_ebz/vcu118/system_top.v new file mode 100644 index 000000000..245281bec --- /dev/null +++ b/projects/ad9081_fmca_ebz/vcu118/system_top.v @@ -0,0 +1,363 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + + +module system_top #( + parameter TX_JESD_L = 8, + parameter TX_NUM_LINKS = 1, + parameter RX_JESD_L = 8, + parameter RX_NUM_LINKS = 1 + ) ( + + input sys_rst, + input sys_clk_p, + input sys_clk_n, + + input uart_sin, + output uart_sout, + + output ddr4_act_n, + output [16:0] ddr4_addr, + output [ 1:0] ddr4_ba, + output [ 0:0] ddr4_bg, + output ddr4_ck_p, + output ddr4_ck_n, + output [ 0:0] ddr4_cke, + output [ 0:0] ddr4_cs_n, + inout [ 7:0] ddr4_dm_n, + inout [63:0] ddr4_dq, + inout [ 7:0] ddr4_dqs_p, + inout [ 7:0] ddr4_dqs_n, + output [ 0:0] ddr4_odt, + output ddr4_reset_n, + + output mdio_mdc, + inout mdio_mdio, + input phy_clk_p, + input phy_clk_n, + output phy_rst_n, + input phy_rx_p, + input phy_rx_n, + output phy_tx_p, + output phy_tx_n, + + inout [16:0] gpio_bd, + + output iic_rstn, + inout iic_scl, + inout iic_sda, + + input vadj_1v8_pgood, + + // FMC HPC IOs + input [1:0] agc0, + input [1:0] agc1, + input [1:0] agc2, + input [1:0] agc3, + input clkin8_n, + input clkin8_p, + input clkin6_n, + input clkin6_p, + input fpga_refclk_in_n, + input fpga_refclk_in_p, + input fpga_refclk_in_replica_n, + input fpga_refclk_in_replica_p, + input [RX_JESD_L*RX_NUM_LINKS-1:0] rx_data_n, + input [RX_JESD_L*RX_NUM_LINKS-1:0] rx_data_p, + output [TX_JESD_L*TX_NUM_LINKS-1:0] tx_data_n, + output [TX_JESD_L*TX_NUM_LINKS-1:0] tx_data_p, + input [TX_NUM_LINKS-1:0] fpga_syncin_n, + input [TX_NUM_LINKS-1:0] fpga_syncin_p, + output [RX_NUM_LINKS-1:0] fpga_syncout_n, + output [RX_NUM_LINKS-1:0] fpga_syncout_p, + inout [10:0] gpio, + inout hmc_gpio1, + output hmc_sync, + input [1:0] irqb, + output rstb, + output [1:0] rxen, + output spi0_csb, + input spi0_miso, + output spi0_mosi, + output spi0_sclk, + output spi1_csb, + output spi1_sclk, + inout spi1_sdio, + input sysref2_n, + input sysref2_p, + output [1:0] txen + +); + + // internal signals + + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + wire [ 7:0] spi_csn; + wire spi_mosi; + wire spi_miso; + wire spi1_miso; + + wire ref_clk; + wire ref_clk_replica; + wire sysref; + wire [TX_NUM_LINKS-1:0] tx_syncin; + wire [RX_NUM_LINKS-1:0] rx_syncout; + + wire [7:0] tx_data_p_loc; + wire [7:0] tx_data_n_loc; + + wire clkin6; + wire clkin8; + wire tx_device_clk; + wire rx_device_clk; + + assign iic_rstn = 1'b1; + + // instantiations + + IBUFDS_GTE4 i_ibufds_ref_clk ( + .CEB (1'd0), + .I (fpga_refclk_in_p), + .IB (fpga_refclk_in_n), + .O (ref_clk), + .ODIV2 ()); + + IBUFDS_GTE4 i_ibufds_ref_clk_replica ( + .CEB (1'd0), + .I (fpga_refclk_in_replica_p), + .IB (fpga_refclk_in_replica_n), + .O (ref_clk_replica), + .ODIV2 ()); + + IBUFDS i_ibufds_sysref ( + .I (sysref2_p), + .IB (sysref2_n), + .O (sysref)); + + IBUFDS i_ibufds_device_clk ( + .I (clkin6_p), + .IB (clkin6_n), + .O (clkin6)); + + IBUFDS_GTE4 i_ibufds_rx_device_clk ( + .I (clkin8_p), + .IB (clkin8_n), + .CEB(1'b0), + .ODIV2 (clkin8)); + + genvar i; + generate + for(i=0;i