From b17fec689e15fb9a2f3960c87c5b59186387ed46 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Wed, 11 Nov 2015 11:13:33 +0200
Subject: [PATCH] ad_tdd_control:  An active sync pulse can NOT be a reset for
 the control lines

By reset the control lines (RF, VCO and DP) on an active sync pulse, can cause glitches on the ENABLE/TXNRX lines. The sync pulse resets just the TDD counter.
---
 library/common/ad_tdd_control.v | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/library/common/ad_tdd_control.v b/library/common/ad_tdd_control.v
index 211e81e23..5d6beb385 100644
--- a/library/common/ad_tdd_control.v
+++ b/library/common/ad_tdd_control.v
@@ -273,7 +273,7 @@ module ad_tdd_control(
       end
 
       OFF : begin
-        if((tdd_enable == 1'b1) && (tdd_enable_d == 1'b0)) begin
+        if((tdd_enable_d1 == 1'b1) && (tdd_enable_d2 == 1'b0)) begin
           tdd_cstate_next <= ON;
         end
       end
@@ -772,7 +772,7 @@ module ad_tdd_control(
   assign tdd_txrx_only_en_s = tdd_tx_only ^ tdd_rx_only;
 
   always @(posedge clk) begin
-    if((rst == 1'b1) || (tdd_sync_pulse == 1'b1)) begin
+    if(rst == 1'b1) begin
       tdd_rx_vco_en <= 1'b0;
     end else if((tdd_cstate == OFF) || (counter_at_tdd_vco_rx_off_1 == 1'b1) || (counter_at_tdd_vco_rx_off_2 == 1'b1)) begin
       tdd_rx_vco_en <= 1'b0;
@@ -786,7 +786,7 @@ module ad_tdd_control(
   end
 
   always @(posedge clk) begin
-    if((rst == 1'b1) || (tdd_sync_pulse == 1'b1)) begin
+    if(rst == 1'b1) begin
       tdd_tx_vco_en <= 1'b0;
     end else if((tdd_cstate == OFF) || (counter_at_tdd_vco_tx_off_1 == 1'b1) || (counter_at_tdd_vco_tx_off_2 == 1'b1)) begin
       tdd_tx_vco_en <= 1'b0;
@@ -800,7 +800,7 @@ module ad_tdd_control(
   end
 
   always @(posedge clk) begin
-    if((rst == 1'b1) || (tdd_sync_pulse == 1'b1)) begin
+    if(rst == 1'b1) begin
       tdd_rx_rf_en <= 1'b0;
     end else if((tdd_cstate == OFF) || (counter_at_tdd_rx_off_1 == 1'b1) || (counter_at_tdd_rx_off_2 == 1'b1)) begin
       tdd_rx_rf_en <= 1'b0;
@@ -814,7 +814,7 @@ module ad_tdd_control(
   end
 
   always @(posedge clk) begin
-    if((rst == 1'b1) || (tdd_sync_pulse == 1'b1)) begin
+    if(rst == 1'b1) begin
       tdd_tx_rf_en <= 1'b0;
     end else if((tdd_cstate == OFF) || (counter_at_tdd_tx_off_1 == 1'b1) || (counter_at_tdd_tx_off_2 == 1'b1)) begin
       tdd_tx_rf_en <= 1'b0;
@@ -828,7 +828,7 @@ module ad_tdd_control(
   end
 
   always @(posedge clk) begin
-    if((rst == 1'b1) || (tdd_sync_pulse == 1'b1)) begin
+    if(rst == 1'b1) begin
       tdd_tx_dp_en <= 1'b0;
     end else if((tdd_cstate == OFF) || (counter_at_tdd_tx_dp_off_1 == 1'b1) || (counter_at_tdd_tx_dp_off_2 == 1'b1)) begin
       tdd_tx_dp_en <= 1'b0;