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adv7511_zc706: Interrupts and framework updates

main
Istvan Csomortani 2015-03-20 13:30:24 +02:00
parent 8f5551718e
commit b12187433d
4 changed files with 92 additions and 101 deletions
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12
projects/adv7511/common/adv7511_bd.tcl
View File

@ -19,11 +19,6 @@ create_bd_port -dir O -from 35 -to 0 hdmi_36_data
create_bd_port -dir O spdif
# interrupts
create_bd_port -dir O axi_hdmi_dma_intr
create_bd_port -dir O axi_spdif_tx_dma_intr
# hdmi peripherals
set axi_hdmi_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_hdmi_clkgen]
@ -76,7 +71,6 @@ ad_connect axi_hdmi_core/m_axis_mm2s_tlast axi_hdmi_dma/m_axis_mm2s_tlast
ad_connect axi_hdmi_core/m_axis_mm2s_tready axi_hdmi_dma/m_axis_mm2s_tready
ad_connect axi_hdmi_core/m_axis_mm2s_fsync axi_hdmi_dma/mm2s_fsync
ad_connect axi_hdmi_core/m_axis_mm2s_fsync axi_hdmi_core/m_axis_mm2s_fsync_ret
ad_connect axi_hdmi_dma/mm2s_introut axi_hdmi_dma_intr
# spdif audio
@ -89,7 +83,6 @@ ad_connect sys_audio_clkgen/clk_out1 axi_spdif_tx_core/spdif_data_clk
ad_connect sys_cpu_clk axi_spdif_tx_core/S_AXIS_ACLK
ad_connect sys_cpu_resetn axi_spdif_tx_core/S_AXIS_ARESETN
ad_connect spdif axi_spdif_tx_core/spdif_tx_o
ad_connect axi_spdif_tx_dma/mm2s_introut axi_spdif_tx_dma_intr
# processor interconnects
@ -105,3 +98,8 @@ ad_mem_hp0_interconnect sys_cpu_clk axi_hdmi_dma/M_AXI_MM2S
ad_mem_hp0_interconnect sys_cpu_clk axi_spdif_tx_dma/M_AXI_SG
ad_mem_hp0_interconnect sys_cpu_clk axi_spdif_tx_dma/M_AXI_MM2S
# interrupts
ad_cpu_interrupt ps-0 mb-8 axi_hdmi_dma/mm2s_introut
ad_cpu_interrupt ps-0 mb-7 axi_spdif_tx_dma/mm2s_introut

6
projects/adv7511/zc706/system_bd.tcl
View File

@ -1,9 +1,3 @@
source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {32}] $sys_ps7
set_property -dict [list CONFIG.NUM_MI {7}] $axi_cpu_interconnect
set_property LEFT 31 [get_bd_ports GPIO_I]
set_property LEFT 31 [get_bd_ports GPIO_O]
set_property LEFT 31 [get_bd_ports GPIO_T]

1
projects/adv7511/zc706/system_project.tcl
View File

@ -1,6 +1,7 @@
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project_create adv7511_zc706
adi_project_files adv7511_zc706 [list \

174
projects/adv7511/zc706/system_top.v
View File

@ -41,28 +41,28 @@
module system_top (
DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
ddr_addr,
ddr_ba,
ddr_cas_n,
ddr_ck_n,
ddr_ck_p,
ddr_cke,
ddr_cs_n,
ddr_dm,
ddr_dq,
ddr_dqs_n,
ddr_dqs_p,
ddr_odt,
ddr_ras_n,
ddr_reset_n,
ddr_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
fixed_io_ddr_vrn,
fixed_io_ddr_vrp,
fixed_io_mio,
fixed_io_ps_clk,
fixed_io_ps_porb,
fixed_io_ps_srstb,
gpio_bd,
@ -77,28 +77,28 @@ module system_top (
iic_scl,
iic_sda);
inout [14:0] DDR_addr;
inout [ 2:0] DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [ 3:0] DDR_dm;
inout [31:0] DDR_dq;
inout [ 3:0] DDR_dqs_n;
inout [ 3:0] DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout [14:0] ddr_addr;
inout [ 2:0] ddr_ba;
inout ddr_cas_n;
inout ddr_ck_n;
inout ddr_ck_p;
inout ddr_cke;
inout ddr_cs_n;
inout [ 3:0] ddr_dm;
inout [31:0] ddr_dq;
inout [ 3:0] ddr_dqs_n;
inout [ 3:0] ddr_dqs_p;
inout ddr_odt;
inout ddr_ras_n;
inout ddr_reset_n;
inout ddr_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0] FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
inout fixed_io_ddr_vrn;
inout fixed_io_ddr_vrp;
inout [53:0] fixed_io_mio;
inout fixed_io_ps_clk;
inout fixed_io_ps_porb;
inout fixed_io_ps_srstb;
inout [14:0] gpio_bd;
@ -115,47 +115,45 @@ module system_top (
// internal signals
wire [14:0] gpio_i;
wire [14:0] gpio_o;
wire [14:0] gpio_t;
wire [15:0] ps_intrs;
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
// instantiations
ad_iobuf #(
.DATA_WIDTH(15)
) i_gpio_bd (
.dt(gpio_t),
.di(gpio_o),
.do(gpio_i),
.dt(gpio_t[14:0]),
.di(gpio_o[14:0]),
.do(gpio_i[14:0]),
.dio(gpio_bd));
system_wrapper i_system_wrapper (
.DDR_addr (DDR_addr),
.DDR_ba (DDR_ba),
.DDR_cas_n (DDR_cas_n),
.DDR_ck_n (DDR_ck_n),
.DDR_ck_p (DDR_ck_p),
.DDR_cke (DDR_cke),
.DDR_cs_n (DDR_cs_n),
.DDR_dm (DDR_dm),
.DDR_dq (DDR_dq),
.DDR_dqs_n (DDR_dqs_n),
.DDR_dqs_p (DDR_dqs_p),
.DDR_odt (DDR_odt),
.DDR_ras_n (DDR_ras_n),
.DDR_reset_n (DDR_reset_n),
.DDR_we_n (DDR_we_n),
.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp),
.FIXED_IO_mio (FIXED_IO_mio),
.FIXED_IO_ps_clk (FIXED_IO_ps_clk),
.FIXED_IO_ps_porb (FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb),
.GPIO_I (gpio_i),
.GPIO_O (gpio_o),
.GPIO_T (gpio_t),
.ddr_addr (DDR_addr),
.ddr_ba (DDR_ba),
.ddr_cas_n (DDR_cas_n),
.ddr_ck_n (DDR_ck_n),
.ddr_ck_p (DDR_ck_p),
.ddr_cke (DDR_cke),
.ddr_cs_n (DDR_cs_n),
.ddr_dm (DDR_dm),
.ddr_dq (DDR_dq),
.ddr_dqs_n (DDR_dqs_n),
.ddr_dqs_p (DDR_dqs_p),
.ddr_odt (DDR_odt),
.ddr_ras_n (DDR_ras_n),
.ddr_reset_n (DDR_reset_n),
.ddr_we_n (DDR_we_n),
.fixed_io_ddr_vrn (FIXED_IO_ddr_vrn),
.fixed_io_ddr_vrp (FIXED_IO_ddr_vrp),
.fixed_io_mio (FIXED_IO_mio),
.fixed_io_ps_clk (FIXED_IO_ps_clk),
.fixed_io_ps_porb (FIXED_IO_ps_porb),
.fixed_io_ps_srstb (FIXED_IO_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
@ -163,20 +161,20 @@ module system_top (
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.ps_intr_0 (ps_intrs[0]),
.ps_intr_1 (ps_intrs[1]),
.ps_intr_2 (ps_intrs[2]),
.ps_intr_3 (ps_intrs[3]),
.ps_intr_4 (ps_intrs[4]),
.ps_intr_5 (ps_intrs[5]),
.ps_intr_6 (ps_intrs[6]),
.ps_intr_7 (ps_intrs[7]),
.ps_intr_8 (ps_intrs[8]),
.ps_intr_9 (ps_intrs[9]),
.ps_intr_10 (ps_intrs[10]),
.ps_intr_11 (ps_intrs[11]),
.ps_intr_12 (ps_intrs[12]),
.ps_intr_13 (ps_intrs[13]),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.ps_intr_10 (1'b0),
.ps_intr_11 (1'b0),
.ps_intr_12 (1'b0),
.ps_intr_13 (1'b0),
.spdif (spdif));
endmodule