diff --git a/projects/daq3/a10gx/Makefile b/projects/daq3/a10gx/Makefile
new file mode 100644
index 000000000..51c24bfef
--- /dev/null
+++ b/projects/daq3/a10gx/Makefile
@@ -0,0 +1,139 @@
+####################################################################################
+####################################################################################
+## Copyright 2011(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+M_DEPS += system_top.v
+M_DEPS += system_project.tcl
+M_DEPS += system_constr.sdc
+M_DEPS += system_bd.qsys
+M_DEPS += ../common/daq2_spi.v
+M_DEPS += ../common/daq2_bd.qsys
+M_DEPS += ../../scripts/adi_env.tcl
+M_DEPS += ../../common/a10gx/a10gx_system_bd.qsys
+M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl
+M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/axi_ad9144/axi_ad9144.v
+M_DEPS += ../../../library/axi_ad9144/axi_ad9144_channel.v
+M_DEPS += ../../../library/axi_ad9144/axi_ad9144_core.v
+M_DEPS += ../../../library/axi_ad9144/axi_ad9144_hw.tcl
+M_DEPS += ../../../library/axi_ad9144/axi_ad9144_if.v
+M_DEPS += ../../../library/axi_ad9680/axi_ad9680.v
+M_DEPS += ../../../library/axi_ad9680/axi_ad9680_channel.v
+M_DEPS += ../../../library/axi_ad9680/axi_ad9680_hw.tcl
+M_DEPS += ../../../library/axi_ad9680/axi_ad9680_if.v
+M_DEPS += ../../../library/axi_ad9680/axi_ad9680_pnmon.v
+M_DEPS += ../../../library/axi_dmac/2d_transfer.v
+M_DEPS += ../../../library/axi_dmac/address_generator.v
+M_DEPS += ../../../library/axi_dmac/axi_dmac.v
+M_DEPS += ../../../library/axi_dmac/axi_dmac_hw.tcl
+M_DEPS += ../../../library/axi_dmac/axi_register_slice.v
+M_DEPS += ../../../library/axi_dmac/data_mover.v
+M_DEPS += ../../../library/axi_dmac/dest_axi_mm.v
+M_DEPS += ../../../library/axi_dmac/dest_axi_stream.v
+M_DEPS += ../../../library/axi_dmac/dest_fifo_inf.v
+M_DEPS += ../../../library/axi_dmac/inc_id.h
+M_DEPS += ../../../library/axi_dmac/request_arb.v
+M_DEPS += ../../../library/axi_dmac/request_generator.v
+M_DEPS += ../../../library/axi_dmac/resp.h
+M_DEPS += ../../../library/axi_dmac/response_generator.v
+M_DEPS += ../../../library/axi_dmac/response_handler.v
+M_DEPS += ../../../library/axi_dmac/splitter.v
+M_DEPS += ../../../library/axi_dmac/src_axi_mm.v
+M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
+M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
+M_DEPS += ../../../library/axi_jesd_xcvr/axi_jesd_xcvr.v
+M_DEPS += ../../../library/axi_jesd_xcvr/axi_jesd_xcvr_hw.tcl
+M_DEPS += ../../../library/common/ad_datafmt.v
+M_DEPS += ../../../library/common/ad_dds.v
+M_DEPS += ../../../library/common/ad_dds_1.v
+M_DEPS += ../../../library/common/ad_dds_sine.v
+M_DEPS += ../../../library/common/ad_jesd_align.v
+M_DEPS += ../../../library/common/ad_mul.v
+M_DEPS += ../../../library/common/ad_pnmon.v
+M_DEPS += ../../../library/common/ad_rst.v
+M_DEPS += ../../../library/common/altera/MULT_MACRO.v
+M_DEPS += ../../../library/common/sync_bits.v
+M_DEPS += ../../../library/common/sync_gray.v
+M_DEPS += ../../../library/common/up_adc_channel.v
+M_DEPS += ../../../library/common/up_adc_common.v
+M_DEPS += ../../../library/common/up_axi.v
+M_DEPS += ../../../library/common/up_clock_mon.v
+M_DEPS += ../../../library/common/up_dac_channel.v
+M_DEPS += ../../../library/common/up_dac_common.v
+M_DEPS += ../../../library/common/up_delay_cntrl.v
+M_DEPS += ../../../library/common/up_xcvr.v
+M_DEPS += ../../../library/common/up_xfer_cntrl.v
+M_DEPS += ../../../library/common/up_xfer_status.v
+M_DEPS += ../../../library/util_adcfifo/../common/ad_axis_inf_rx.v
+M_DEPS += ../../../library/util_adcfifo/../common/ad_mem_asym.v
+M_DEPS += ../../../library/util_adcfifo/util_adcfifo.v
+M_DEPS += ../../../library/util_adcfifo/util_adcfifo_hw.tcl
+M_DEPS += ../../../library/util_axis_fifo/address_gray.v
+M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
+M_DEPS += ../../../library/util_axis_fifo/address_sync.v
+M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v
+M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v
+M_DEPS += ../../../library/util_cpack/util_cpack.v
+M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v
+M_DEPS += ../../../library/util_cpack/util_cpack_hw.tcl
+M_DEPS += ../../../library/util_cpack/util_cpack_mux.v
+M_DEPS += ../../../library/util_upack/util_upack.v
+M_DEPS += ../../../library/util_upack/util_upack_dmx.v
+M_DEPS += ../../../library/util_upack/util_upack_dsf.v
+M_DEPS += ../../../library/util_upack/util_upack_hw.tcl
+
+
+M_ALTERA := quartus_sh --64bit -t 
+
+
+M_FLIST += *.log
+M_FLIST += *_INFO.txt
+M_FLIST += *_dump.txt
+M_FLIST += db
+M_FLIST += *.asm.rpt
+M_FLIST += *.done
+M_FLIST += *.eda.rpt
+M_FLIST += *.fit.*
+M_FLIST += *.map.*
+M_FLIST += *.sta.*
+M_FLIST += *.qsf
+M_FLIST += *.qpf
+M_FLIST += *.qws
+M_FLIST += *.sof
+M_FLIST += *.cdf
+M_FLIST += *.sld
+M_FLIST += *.qdf
+M_FLIST += hc_output
+M_FLIST += system_bd
+M_FLIST += hps_isw_handoff
+M_FLIST += hps_sdram_*.csv
+M_FLIST += *ddr3_*.csv
+M_FLIST += incremental_db
+M_FLIST += reconfig_mif
+M_FLIST += *.sopcinfo
+M_FLIST +=  *.jdi
+M_FLIST += *.pin
+
+
+
+.PHONY: all clean clean-all
+all: daq2_a10gx.sof
+
+
+
+clean:clean-all
+
+
+clean-all:
+	rm -rf $(M_FLIST)
+
+
+daq2_a10gx.sof: $(M_DEPS)
+	rm -rf $(M_FLIST)
+	$(M_ALTERA) system_project.tcl  >> daq2_a10gx_quartus.log 2>&1
+
+####################################################################################
+####################################################################################
diff --git a/projects/daq3/a10gx/system_bd.qsys b/projects/daq3/a10gx/system_bd.qsys
new file mode 100755
index 000000000..1a8f91dd9
--- /dev/null
+++ b/projects/daq3/a10gx/system_bd.qsys
@@ -0,0 +1,586 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+   name="$${FILENAME}"
+   displayName="$${FILENAME}"
+   version="1.0"
+   description=""
+   tags=""
+   categories="System" />
+ <parameter name="bonusData"><![CDATA[bonusData 
+{
+   element $${FILENAME}
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element a10gx_base
+   {
+      datum _sortIndex
+      {
+         value = "1";
+         type = "int";
+      }
+   }
+   element a10gx_base.sys_mem_s_avl
+   {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "0";
+         type = "String";
+      }
+   }
+   element daq2
+   {
+      datum _sortIndex
+      {
+         value = "2";
+         type = "int";
+      }
+   }
+   element daq2.axi_ad9144_core_s_axi
+   {
+      datum baseAddress
+      {
+         value = "131072";
+         type = "String";
+      }
+   }
+   element daq2.axi_ad9144_dma_s_axi
+   {
+      datum baseAddress
+      {
+         value = "212992";
+         type = "String";
+      }
+   }
+   element daq2.axi_ad9680_core_s_axi
+   {
+      datum baseAddress
+      {
+         value = "65536";
+         type = "String";
+      }
+   }
+   element daq2.axi_ad9680_dma_s_axi
+   {
+      datum baseAddress
+      {
+         value = "196608";
+         type = "String";
+      }
+   }
+   element daq2.axi_jesd_xcvr_s_axi
+   {
+      datum baseAddress
+      {
+         value = "0";
+         type = "String";
+      }
+   }
+   element sys_clk
+   {
+      datum _sortIndex
+      {
+         value = "0";
+         type = "int";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="FIFO" />
+ <parameter name="device" value="10AX115S3F45I2SGE2" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="2" />
+ <parameter name="projectName" value="daq2_a10gx.qpf" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+   name="a10gx_base_sys_ddr3_cntrl_mem"
+   internal="a10gx_base.sys_ddr3_cntrl_mem"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="a10gx_base_sys_ddr3_cntrl_oct"
+   internal="a10gx_base.sys_ddr3_cntrl_oct"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="a10gx_base_sys_ddr3_cntrl_pll_ref_clk"
+   internal="a10gx_base.sys_ddr3_cntrl_pll_ref_clk"
+   type="clock"
+   dir="end" />
+ <interface
+   name="a10gx_base_sys_ethernet_mdio"
+   internal="a10gx_base.sys_ethernet_mdio"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="a10gx_base_sys_ethernet_ref_clk"
+   internal="a10gx_base.sys_ethernet_ref_clk"
+   type="clock"
+   dir="end" />
+ <interface
+   name="a10gx_base_sys_ethernet_reset"
+   internal="a10gx_base.sys_ethernet_reset"
+   type="reset"
+   dir="start" />
+ <interface
+   name="a10gx_base_sys_ethernet_sgmii"
+   internal="a10gx_base.sys_ethernet_sgmii"
+   type="conduit"
+   dir="end" />
+ <interface name="a10gx_base_sys_gpio" internal="a10gx_base.sys_gpio" />
+ <interface
+   name="a10gx_base_sys_gpio_bd"
+   internal="a10gx_base.sys_gpio_bd"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="a10gx_base_sys_gpio_in"
+   internal="a10gx_base.sys_gpio_in"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="a10gx_base_sys_gpio_out"
+   internal="a10gx_base.sys_gpio_out"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="a10gx_base_sys_spi"
+   internal="a10gx_base.sys_spi"
+   type="conduit"
+   dir="end" />
+ <interface name="daq2_rx_data" internal="daq2.rx_data" type="conduit" dir="end" />
+ <interface
+   name="daq2_rx_ref_clk"
+   internal="daq2.rx_ref_clk"
+   type="clock"
+   dir="end" />
+ <interface name="daq2_rx_sync" internal="daq2.rx_sync" type="conduit" dir="end" />
+ <interface
+   name="daq2_rx_sysref"
+   internal="daq2.rx_sysref"
+   type="conduit"
+   dir="end" />
+ <interface name="daq2_tx_data" internal="daq2.tx_data" type="conduit" dir="end" />
+ <interface
+   name="daq2_tx_ref_clk"
+   internal="daq2.tx_ref_clk"
+   type="clock"
+   dir="end" />
+ <interface name="daq2_tx_sync" internal="daq2.tx_sync" type="conduit" dir="end" />
+ <interface
+   name="daq2_tx_sysref"
+   internal="daq2.tx_sysref"
+   type="conduit"
+   dir="end" />
+ <interface name="sys_clk" internal="sys_clk.clk_in" type="clock" dir="end" />
+ <interface
+   name="sys_reset"
+   internal="sys_clk.clk_in_reset"
+   type="reset"
+   dir="end" />
+ <module name="a10gx_base" kind="a10gx_system_bd" version="1.0" enabled="1">
+  <parameter name="AUTO_DEVICE" value="10AX115S3F45I2SGE2" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
+  <parameter name="AUTO_GENERATION_ID" value="0" />
+  <parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="6" />
+  <parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="100000000" />
+  <parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="6" />
+  <parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_MAP"><![CDATA[<address-map><slave name='daq2_axi_jesd_xcvr.s_axi' start='0x0' end='0x10000' /><slave name='daq2_axi_ad9680_core.s_axi' start='0x10000' end='0x20000' /><slave name='daq2_axi_ad9144_core.s_axi' start='0x20000' end='0x30000' /><slave name='daq2_axi_ad9680_dma.s_axi' start='0x30000' end='0x34000' /><slave name='daq2_axi_ad9144_dma.s_axi' start='0x34000' end='0x38000' /></address-map>]]></parameter>
+  <parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_WIDTH" value="AddressWidth = 18" />
+  <parameter name="AUTO_SYS_DDR3_CNTRL_PLL_REF_CLK_CLOCK_DOMAIN" value="1" />
+  <parameter name="AUTO_SYS_DDR3_CNTRL_PLL_REF_CLK_CLOCK_RATE" value="0" />
+  <parameter name="AUTO_SYS_DDR3_CNTRL_PLL_REF_CLK_RESET_DOMAIN" value="1" />
+  <parameter name="AUTO_SYS_ETHERNET_REF_CLK_CLOCK_DOMAIN" value="2" />
+  <parameter name="AUTO_SYS_ETHERNET_REF_CLK_CLOCK_RATE" value="0" />
+  <parameter name="AUTO_SYS_ETHERNET_REF_CLK_RESET_DOMAIN" value="2" />
+  <parameter name="AUTO_SYS_INTR_INTERRUPTS_USED" value="3" />
+  <parameter name="AUTO_UNIQUE_ID">$${FILENAME}_a10gx_base</parameter>
+ </module>
+ <module name="daq2" kind="daq2_bd" version="1.0" enabled="1">
+  <parameter name="AUTO_AXI_AD9144_DMA_M_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10gx_base_sys_ddr3_cntrl.ctrl_amm_0' start='0x0' end='0x10000000' /></address-map>]]></parameter>
+  <parameter
+     name="AUTO_AXI_AD9144_DMA_M_AXI_ADDRESS_WIDTH"
+     value="AddressWidth = 29" />
+  <parameter name="AUTO_AXI_AD9680_DMA_M_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10gx_base_sys_ddr3_cntrl.ctrl_amm_0' start='0x0' end='0x10000000' /></address-map>]]></parameter>
+  <parameter
+     name="AUTO_AXI_AD9680_DMA_M_AXI_ADDRESS_WIDTH"
+     value="AddressWidth = 29" />
+  <parameter name="AUTO_DEVICE" value="10AX115S3F45I2SGE2" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
+  <parameter name="AUTO_GENERATION_ID" value="0" />
+  <parameter name="AUTO_MEM_CLK_CLOCK_DOMAIN" value="8" />
+  <parameter name="AUTO_MEM_CLK_CLOCK_RATE" value="133333250" />
+  <parameter name="AUTO_MEM_CLK_RESET_DOMAIN" value="8" />
+  <parameter name="AUTO_RX_REF_CLK_CLOCK_DOMAIN" value="4" />
+  <parameter name="AUTO_RX_REF_CLK_CLOCK_RATE" value="0" />
+  <parameter name="AUTO_RX_REF_CLK_RESET_DOMAIN" value="4" />
+  <parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="6" />
+  <parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="100000000" />
+  <parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="6" />
+  <parameter name="AUTO_TX_REF_CLK_CLOCK_DOMAIN" value="5" />
+  <parameter name="AUTO_TX_REF_CLK_CLOCK_RATE" value="0" />
+  <parameter name="AUTO_TX_REF_CLK_RESET_DOMAIN" value="5" />
+  <parameter name="AUTO_UNIQUE_ID" value="$${FILENAME}_daq2" />
+ </module>
+ <module name="sys_clk" kind="clock_source" version="15.0" enabled="1">
+  <parameter name="clockFrequency" value="100000000" />
+  <parameter name="clockFrequencyKnown" value="true" />
+  <parameter name="inputClockFrequency" value="0" />
+  <parameter name="resetSynchronousEdges" value="NONE" />
+ </module>
+ <connection
+   kind="avalon"
+   version="15.0"
+   start="daq2.axi_ad9144_dma_m_axi"
+   end="a10gx_base.sys_mem_s_avl">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.0"
+   start="daq2.axi_ad9680_dma_m_axi"
+   end="a10gx_base.sys_mem_s_avl">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.0"
+   start="a10gx_base.sys_cpu_m_avl"
+   end="daq2.axi_ad9144_core_s_axi">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00020000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.0"
+   start="a10gx_base.sys_cpu_m_avl"
+   end="daq2.axi_ad9144_dma_s_axi">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00034000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.0"
+   start="a10gx_base.sys_cpu_m_avl"
+   end="daq2.axi_ad9680_core_s_axi">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00010000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.0"
+   start="a10gx_base.sys_cpu_m_avl"
+   end="daq2.axi_ad9680_dma_s_axi">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00030000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.0"
+   start="a10gx_base.sys_cpu_m_avl"
+   end="daq2.axi_jesd_xcvr_s_axi">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="clock"
+   version="15.0"
+   start="sys_clk.clk"
+   end="a10gx_base.sys_clk" />
+ <connection kind="clock" version="15.0" start="sys_clk.clk" end="daq2.sys_clk" />
+ <connection
+   kind="clock"
+   version="15.0"
+   start="a10gx_base.mem_clk"
+   end="daq2.mem_clk" />
+ <connection
+   kind="interrupt"
+   version="15.0"
+   start="a10gx_base.sys_intr"
+   end="daq2.axi_ad9144_dma_intr">
+  <parameter name="irqNumber" value="1" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="15.0"
+   start="a10gx_base.sys_intr"
+   end="daq2.axi_ad9680_dma_intr">
+  <parameter name="irqNumber" value="0" />
+ </connection>
+ <connection
+   kind="reset"
+   version="15.0"
+   start="sys_clk.clk_reset"
+   end="a10gx_base.sys_rst" />
+ <connection
+   kind="reset"
+   version="15.0"
+   start="sys_clk.clk_reset"
+   end="daq2.sys_rst" />
+ <connection
+   kind="reset"
+   version="15.0"
+   start="a10gx_base.mem_rst"
+   end="daq2.mem_rst" />
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="false" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
+</system>
diff --git a/projects/daq3/a10gx/system_constr.sdc b/projects/daq3/a10gx/system_constr.sdc
new file mode 100644
index 000000000..86ef79f85
--- /dev/null
+++ b/projects/daq3/a10gx/system_constr.sdc
@@ -0,0 +1,16 @@
+
+create_clock -period "10.000 ns"  -name sys_clk_100mhz      [get_ports {sys_clk}]
+create_clock -period "2.000 ns"   -name rx_ref_clk_500mhz   [get_ports {rx_ref_clk}]
+create_clock -period "2.000 ns"   -name tx_ref_clk_500mhz   [get_ports {tx_ref_clk}]
+
+derive_pll_clocks
+derive_clock_uncertainty
+
+set_false_path -from [get_clocks {sys_clk_100mhz}] -to [get_clocks {\
+  i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_0 \
+  i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_1 \
+  i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_2 \
+  i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_l_0 \
+  i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_l_1 \
+  i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_l_2}]
+ 
diff --git a/projects/daq3/a10gx/system_project.tcl b/projects/daq3/a10gx/system_project.tcl
new file mode 100644
index 000000000..664f75637
--- /dev/null
+++ b/projects/daq3/a10gx/system_project.tcl
@@ -0,0 +1,92 @@
+
+load_package flow
+
+source ../../scripts/adi_env.tcl
+project_new daq2_a10gx -overwrite
+
+source "../../common/a10gx/a10gx_system_assign.tcl"
+set_user_option -name USER_IP_SEARCH_PATHS "../common/;../../common/a10gx/;../../../library/**/*"
+set_global_assignment -name IP_SEARCH_PATHS "../common/;../../common/a10gx;../../../library/**/*"
+set_global_assignment -name QSYS_FILE system_bd.qsys
+
+set_global_assignment -name VERILOG_FILE "../../../library/common/ad_iobuf.v"
+set_global_assignment -name VERILOG_FILE ../common/daq2_spi.v
+set_global_assignment -name VERILOG_FILE system_top.v
+
+set_global_assignment -name SDC_FILE system_constr.sdc
+set_global_assignment -name TOP_LEVEL_ENTITY system_top
+
+# lane interface
+
+set_location_assignment PIN_AJ8   -to rx_ref_clk            ; ## B20  FMCA_GBTCLK1_M2C_P
+set_location_assignment PIN_AJ7   -to "rx_ref_clk(n)"       ; ## B21  FMCA_GBTCLK1_M2C_N
+set_location_assignment PIN_AV5   -to rx_data[0]            ; ## A10  FMCA_DP3_M2C_P
+set_location_assignment PIN_AV6   -to "rx_data[0](n)"       ; ## A11  FMCA_DP3_M2C_N
+set_location_assignment PIN_AW7   -to rx_data[1]            ; ## C06  FMCA_DP0_M2C_P
+set_location_assignment PIN_AW8   -to "rx_data[1](n)"       ; ## C07  FMCA_DP0_M2C_N
+set_location_assignment PIN_AY5   -to rx_data[2]            ; ## A06  FMCA_DP2_M2C_P
+set_location_assignment PIN_AY6   -to "rx_data[2](n)"       ; ## A07  FMCA_DP2_M2C_N
+set_location_assignment PIN_BA7   -to rx_data[3]            ; ## A02  FMCA_DP1_M2C_P
+set_location_assignment PIN_BA8   -to "rx_data[3](n)"       ; ## A03  FMCA_DP1_M2C_N
+set_location_assignment PIN_AT10  -to rx_sync               ; ## D08  FMCA_LA01_CC_P
+set_location_assignment PIN_AR11  -to "rx_sync(n)"          ; ## D09  FMCA_LA01_CC_N
+set_location_assignment PIN_AR20  -to rx_sysref             ; ## G09  FMCA_LA03_P
+set_location_assignment PIN_AR19  -to "rx_sysref(n)"        ; ## G10  FMCA_LA03_N
+set_location_assignment PIN_AL8   -to tx_ref_clk            ; ## D04  FMCA_GBTCLK0_M2C_P
+set_location_assignment PIN_AL7   -to "tx_ref_clk(n)"       ; ## D05  FMCA_GBTCLK0_M2C_N
+set_location_assignment PIN_BC3   -to tx_data[0]            ; ## A30  FMCA_DP3_C2M_P (tx_data_p[0])
+set_location_assignment PIN_BC4   -to "tx_data[0](n)"       ; ## A31  FMCA_DP3_C2M_N (tx_data_n[0])
+set_location_assignment PIN_BC7   -to tx_data[1]            ; ## C02  FMCA_DP0_C2M_P (tx_data_p[3])
+set_location_assignment PIN_BC8   -to "tx_data[1](n)"       ; ## C03  FMCA_DP0_C2M_N (tx_data_n[3])
+set_location_assignment PIN_BB5   -to tx_data[2]            ; ## A26  FMCA_DP2_C2M_P (tx_data_p[1])
+set_location_assignment PIN_BB6   -to "tx_data[2](n)"       ; ## A27  FMCA_DP2_C2M_N (tx_data_n[1])
+set_location_assignment PIN_BD5   -to tx_data[3]            ; ## A22  FMCA_DP1_C2M_P (tx_data_p[2])
+set_location_assignment PIN_BD6   -to "tx_data[3](n)"       ; ## A23  FMCA_DP1_C2M_N (tx_data_n[2])
+set_location_assignment PIN_AR22  -to tx_sync               ; ## H07  FMCA_LA02_P
+set_location_assignment PIN_AT22  -to "tx_sync(n)"          ; ## H08  FMCA_LA02_N
+set_location_assignment PIN_AN20  -to tx_sysref             ; ## H10  FMCA_LA04_P
+set_location_assignment PIN_AP19  -to "tx_sysref(n)"        ; ## H11  FMCA_LA04_N
+
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[0]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[1]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[2]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[3]
+set_instance_assignment -name IO_STANDARD LVDS -to rx_sync
+set_instance_assignment -name IO_STANDARD LVDS -to rx_sysref
+set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_sysref
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[0]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[1]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[2]
+set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[3]
+set_instance_assignment -name IO_STANDARD LVDS -to tx_sync
+set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to tx_sync
+set_instance_assignment -name IO_STANDARD LVDS -to tx_sysref
+set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to tx_sysref
+
+# gpio
+
+set_location_assignment PIN_AT17  -to trig                  ; ## H13  FMCA_LA07_P
+set_location_assignment PIN_AU17  -to "trig(n)"             ; ## H14  FMCA_LA07_N
+set_location_assignment PIN_AR14  -to adc_fdb               ; ## H17  FMCA_LA11_N
+set_location_assignment PIN_AT14  -to adc_fda               ; ## H16  FMCA_LA11_P
+set_location_assignment PIN_AR16  -to dac_irq               ; ## G15  FMCA_LA12_P
+set_location_assignment PIN_AP17  -to clkd_status[1]        ; ## D18  FMCA_LA13_N
+set_location_assignment PIN_AR17  -to clkd_status[0]        ; ## D17  FMCA_LA13_P
+set_location_assignment PIN_AV14  -to adc_pd                ; ## C10  FMCA_LA06_P
+set_location_assignment PIN_AP16  -to dac_txen              ; ## G16  FMCA_LA12_N
+set_location_assignment PIN_AT15  -to dac_reset             ; ## C15  FMCA_LA10_N
+set_location_assignment PIN_AP18  -to clkd_sync             ; ## G12  FMCA_LA08_P
+
+set_instance_assignment -name IO_STANDARD LVDS -to trig
+
+# spi
+
+set_location_assignment PIN_AV11  -to spi_csn_clk           ; ## D11  FMCA_LA05_P
+set_location_assignment PIN_AR15  -to spi_csn_dac           ; ## C14  FMCA_LA10_P
+set_location_assignment PIN_AV13  -to spi_csn_adc           ; ## D15  FMCA_LA09_N
+set_location_assignment PIN_AW11  -to spi_clk               ; ## D12  FMCA_LA05_N
+set_location_assignment PIN_AW13  -to spi_sdio              ; ## D14  FMCA_LA09_P
+set_location_assignment PIN_AN19  -to spi_dir               ; ## G13  FMCA_LA08_N
+
+execute_flow -compile
+
diff --git a/projects/daq3/a10gx/system_top.v b/projects/daq3/a10gx/system_top.v
new file mode 100644
index 000000000..9b16e7693
--- /dev/null
+++ b/projects/daq3/a10gx/system_top.v
@@ -0,0 +1,274 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module system_top (
+
+  // clock and resets
+
+  sys_clk,
+  sys_resetn,
+
+  // ddr3
+
+  ddr3_clk_p,
+  ddr3_clk_n,
+  ddr3_a,
+  ddr3_ba,
+  ddr3_cke,
+  ddr3_cs_n,
+  ddr3_odt,
+  ddr3_reset_n,
+  ddr3_we_n,
+  ddr3_ras_n,
+  ddr3_cas_n,
+  ddr3_dqs_p,
+  ddr3_dqs_n,
+  ddr3_dq,
+  ddr3_dm,
+  ddr3_rzq,
+  ddr3_ref_clk,
+
+  // ethernet
+
+  eth_ref_clk,
+  eth_rxd,
+  eth_txd,
+  eth_mdc,
+  eth_mdio,
+  eth_resetn,
+  eth_intn,
+
+  // board gpio
+
+  gpio_bd,
+
+  // lane interface
+
+  rx_ref_clk,
+  rx_sysref,
+  rx_sync,
+  rx_data,
+  tx_ref_clk,
+  tx_sysref,
+  tx_sync,
+  tx_data,
+
+  // gpio
+
+  trig,
+  adc_fdb,
+  adc_fda,
+  dac_irq,
+  clkd_status,
+  adc_pd,
+  dac_txen,
+  dac_reset,
+  clkd_sync,
+
+  // spi
+
+  spi_csn_clk,
+  spi_csn_dac,
+  spi_csn_adc,
+  spi_clk,
+  spi_sdio,
+  spi_dir);
+
+  // clock and resets
+
+  input             sys_clk;
+  input             sys_resetn;
+
+  // ddr3
+
+  output            ddr3_clk_p;
+  output            ddr3_clk_n;
+  output  [ 14:0]   ddr3_a;
+  output  [  2:0]   ddr3_ba;
+  output            ddr3_cke;
+  output            ddr3_cs_n;
+  output            ddr3_odt;
+  output            ddr3_reset_n;
+  output            ddr3_we_n;
+  output            ddr3_ras_n;
+  output            ddr3_cas_n;
+  inout   [  7:0]   ddr3_dqs_p;
+  inout   [  7:0]   ddr3_dqs_n;
+  inout   [ 63:0]   ddr3_dq;
+  output  [  7:0]   ddr3_dm;
+  input             ddr3_rzq;
+  input             ddr3_ref_clk;
+
+  // ethernet
+
+  input             eth_ref_clk;
+  input             eth_rxd;
+  output            eth_txd;
+  output            eth_mdc;
+  inout             eth_mdio;
+  output            eth_resetn;
+  input             eth_intn;
+
+  // board gpio
+
+  inout   [ 26:0]   gpio_bd;
+
+  // lane interface
+
+  input             rx_ref_clk;
+  input             rx_sysref;
+  output            rx_sync;
+  input   [  3:0]   rx_data;
+  input             tx_ref_clk;
+  input             tx_sysref;
+  input             tx_sync;
+  output  [  3:0]   tx_data;
+
+  // gpio
+
+  input             trig;
+  input             adc_fdb;
+  input             adc_fda;
+  input             dac_irq;
+  input   [  1:0]   clkd_status;
+  output            adc_pd;
+  output            dac_txen;
+  output            dac_reset;
+  output            clkd_sync;
+
+  // spi
+
+  output            spi_csn_clk;
+  output            spi_csn_dac;
+  output            spi_csn_adc;
+  output            spi_clk;
+  inout             spi_sdio;
+  output            spi_dir;
+
+  // internal signals
+
+  wire              eth_reset;
+  wire              eth_mdio_i;
+  wire              eth_mdio_o;
+  wire              eth_mdio_t;
+  wire    [ 31:0]   gpio_i;
+  wire    [ 31:0]   gpio_o;
+  wire              spi_miso_s;
+  wire              spi_mosi_s;
+  wire    [  7:0]   spi_csn_s;
+
+  // daq2
+
+  assign spi_csn_adc = spi_csn_s[2];
+  assign spi_csn_dac = spi_csn_s[1];
+  assign spi_csn_clk = spi_csn_s[0];
+
+  daq2_spi i_daq2_spi (
+    .spi_csn (spi_csn_s[2:0]),
+    .spi_clk (spi_clk),
+    .spi_mosi (spi_mosi_s),
+    .spi_miso (spi_miso_s),
+    .spi_sdio (spi_sdio),
+    .spi_dir (spi_dir));
+
+  // board stuff
+
+  assign eth_resetn = ~eth_reset;
+  assign eth_mdio_i = eth_mdio;
+  assign eth_mdio = (eth_mdio_t == 1'b1) ? 1'bz : eth_mdio_o;
+
+  assign ddr3_a[14:12] = 3'd0;
+
+  assign gpio_i[31:27] = gpio_o[31:27];
+
+  ad_iobuf #(.DATA_WIDTH(27)) i_iobuf_bd (
+    .dio_t ({11'h7ff, 16'h0}),
+    .dio_i (gpio_o[26:0]),
+    .dio_o (gpio_i[26:0]),
+    .dio_p (gpio_bd));
+
+  system_bd i_system_bd (
+    .a10gx_base_sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p),
+    .a10gx_base_sys_ddr3_cntrl_mem_mem_ck_n (ddr3_clk_n),
+    .a10gx_base_sys_ddr3_cntrl_mem_mem_a (ddr3_a[11:0]),
+    .a10gx_base_sys_ddr3_cntrl_mem_mem_ba (ddr3_ba),
+    .a10gx_base_sys_ddr3_cntrl_mem_mem_cke (ddr3_cke),
+    .a10gx_base_sys_ddr3_cntrl_mem_mem_cs_n (ddr3_cs_n),
+    .a10gx_base_sys_ddr3_cntrl_mem_mem_odt (ddr3_odt),
+    .a10gx_base_sys_ddr3_cntrl_mem_mem_reset_n (ddr3_reset_n),
+    .a10gx_base_sys_ddr3_cntrl_mem_mem_we_n (ddr3_we_n),
+    .a10gx_base_sys_ddr3_cntrl_mem_mem_ras_n (ddr3_ras_n),
+    .a10gx_base_sys_ddr3_cntrl_mem_mem_cas_n (ddr3_cas_n),
+    .a10gx_base_sys_ddr3_cntrl_mem_mem_dqs (ddr3_dqs_p[7:0]),
+    .a10gx_base_sys_ddr3_cntrl_mem_mem_dqs_n (ddr3_dqs_n[7:0]),
+    .a10gx_base_sys_ddr3_cntrl_mem_mem_dq (ddr3_dq[63:0]),
+    .a10gx_base_sys_ddr3_cntrl_mem_mem_dm (ddr3_dm[7:0]),
+    .a10gx_base_sys_ddr3_cntrl_oct_oct_rzqin (ddr3_rzq),
+    .a10gx_base_sys_ddr3_cntrl_pll_ref_clk_clk (ddr3_ref_clk),
+    .a10gx_base_sys_ethernet_mdio_mdc (eth_mdc),
+    .a10gx_base_sys_ethernet_mdio_mdio_in (eth_mdio_i),
+    .a10gx_base_sys_ethernet_mdio_mdio_out (eth_mdio_o),
+    .a10gx_base_sys_ethernet_mdio_mdio_oen (eth_mdio_t),
+    .a10gx_base_sys_ethernet_ref_clk_clk (eth_ref_clk),
+    .a10gx_base_sys_ethernet_reset_reset (eth_reset),
+    .a10gx_base_sys_ethernet_sgmii_rxp_0 (eth_rxd),
+    .a10gx_base_sys_ethernet_sgmii_txp_0 (eth_txd),
+    .a10gx_base_sys_gpio_in_export ({trig, adc_fdb, adc_fda, dac_irq, clkd_status[1], clkd_status[0]}),
+    .a10gx_base_sys_gpio_out_export ({adc_pd, dac_txen, dac_reset, clkd_sync}),
+    .a10gx_base_sys_gpio_bd_in_port (gpio_i[31:0]),
+    .a10gx_base_sys_gpio_bd_out_port (gpio_o[31:0]),
+    .a10gx_base_sys_spi_MISO (spi_miso_s),
+    .a10gx_base_sys_spi_MOSI (spi_mosi_s),
+    .a10gx_base_sys_spi_SCLK (spi_clk),
+    .a10gx_base_sys_spi_SS_n (spi_csn_s),
+    .daq2_rx_data_rx_serial_data (rx_data),
+    .daq2_rx_ref_clk_clk (rx_ref_clk),
+    .daq2_rx_sync_rx_sync (rx_sync),
+    .daq2_rx_sysref_rx_ext_sysref_in (rx_sysref),
+    .daq2_tx_data_tx_serial_data (tx_data),
+    .daq2_tx_ref_clk_clk (tx_ref_clk),
+    .daq2_tx_sync_tx_sync (tx_sync),
+    .daq2_tx_sysref_tx_ext_sysref_in (tx_sysref),
+    .sys_clk_clk (sys_clk),
+    .sys_reset_reset_n (sys_resetn));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************