util_clkdiv: Seperate the IP source into an intel and xilinx version
parent
84bd50d437
commit
b0fbe1bb57
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@ -67,6 +67,7 @@ clean:
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$(MAKE) -C intel/common/alt_mem_asym clean
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$(MAKE) -C intel/common/alt_serdes clean
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$(MAKE) -C intel/jesd204_phy clean
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$(MAKE) -C intel/util_clkdiv clean
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$(MAKE) -C jesd204/ad_ip_jesd204_tpl_adc clean
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$(MAKE) -C jesd204/ad_ip_jesd204_tpl_dac clean
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$(MAKE) -C jesd204/axi_jesd204_common clean
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@ -90,7 +91,6 @@ clean:
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$(MAKE) -C util_bsplit clean
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$(MAKE) -C util_cdc clean
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$(MAKE) -C util_cic clean
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$(MAKE) -C util_clkdiv clean
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$(MAKE) -C util_dacfifo clean
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$(MAKE) -C util_dec256sinc24b clean
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$(MAKE) -C util_delay clean
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@ -113,6 +113,7 @@ clean:
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$(MAKE) -C xilinx/axi_dacfifo clean
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$(MAKE) -C xilinx/axi_xcvrlb clean
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$(MAKE) -C xilinx/util_adxcvr clean
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$(MAKE) -C xilinx/util_clkdiv clean
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$(MAKE) -C interfaces clean
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@ -176,6 +177,7 @@ lib:
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$(MAKE) -C intel/common/alt_mem_asym
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$(MAKE) -C intel/common/alt_serdes
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$(MAKE) -C intel/jesd204_phy
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$(MAKE) -C intel/util_clkdiv
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$(MAKE) -C jesd204/ad_ip_jesd204_tpl_adc
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$(MAKE) -C jesd204/ad_ip_jesd204_tpl_dac
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$(MAKE) -C jesd204/axi_jesd204_common
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@ -221,6 +223,7 @@ lib:
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$(MAKE) -C xilinx/axi_dacfifo
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$(MAKE) -C xilinx/axi_xcvrlb
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$(MAKE) -C xilinx/util_adxcvr
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$(MAKE) -C xilinx/util_clkdiv
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$(MAKE) -C interfaces
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@ -0,0 +1,11 @@
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####################################################################################
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## Copyright 2018(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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LIBRARY_NAME := util_clkdiv
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INTEL_DEPS += util_clkdiv.v
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INTEL_DEPS += util_clkdiv_hw.tcl
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include ../../scripts/library.mk
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@ -39,7 +39,7 @@
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// clk_sel is 1. Provides a glitch free output clock
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// IP uses BUFR/BUFGCE_DIV and BUFGMUX_CTRL primitives
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module util_clkdiv_alt #(
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module util_clkdiv #(
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parameter SIM_DEVICE = "CYCLONE5",
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parameter CLOCK_TYPE = "Global Clock") (
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@ -76,4 +76,4 @@ generate if (SIM_DEVICE == "CYCLONE5") begin
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end endgenerate
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endmodule // util_clkdiv_alt
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endmodule // util_clkdiv
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@ -1,7 +1,7 @@
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package require -exact qsys 13.0
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source ../scripts/adi_env.tcl
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source ../scripts/adi_ip_intel.tcl
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source ../../scripts/adi_env.tcl
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source ../../scripts/adi_ip_intel.tcl
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set_module_property NAME util_clkdiv
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@ -13,8 +13,8 @@ set_module_property DISPLAY_NAME util_clkdiv
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# files
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add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
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set_fileset_property quartus_synth TOP_LEVEL util_clkdiv_alt
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add_fileset_file util_clkdiv_alt.v VERILOG PATH util_clkdiv_alt.v TOP_LEVEL_FILE
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set_fileset_property quartus_synth TOP_LEVEL util_clkdiv
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add_fileset_file util_clkdiv.v VERILOG PATH util_clkdiv.v TOP_LEVEL_FILE
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# defaults
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@ -5,13 +5,9 @@
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LIBRARY_NAME := util_clkdiv
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XILINX_DEPS += util_clkdiv.v
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XILINX_DEPS += util_clkdiv_constr.xdc
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XILINX_DEPS += util_clkdiv_ooc.ttcl
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XILINX_DEPS += util_clkdiv_ip.tcl
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INTEL_DEPS += util_clkdiv_alt.v
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INTEL_DEPS += util_clkdiv_hw.tcl
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include ../scripts/library.mk
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include ../../scripts/library.mk
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@ -1,4 +1,4 @@
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source ../scripts/adi_env.tcl
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source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
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adi_ip_create util_clkdiv
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@ -16,12 +16,12 @@ M_DEPS += ../../../library/axi_ad9361/axi_ad9361_delay.tcl
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LIB_DEPS += axi_ad9361
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LIB_DEPS += axi_dmac
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LIB_DEPS += axi_gpreg
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LIB_DEPS += util_clkdiv
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LIB_DEPS += util_pack/util_cpack2
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LIB_DEPS += util_pack/util_upack2
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LIB_DEPS += util_rfifo
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LIB_DEPS += util_tdd_sync
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LIB_DEPS += util_wfifo
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LIB_DEPS += xilinx/axi_xcvrlb
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LIB_DEPS += xilinx/util_clkdiv
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include ../../scripts/project-xilinx.mk
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@ -16,12 +16,12 @@ M_DEPS += ../../../library/axi_ad9361/axi_ad9361_delay.tcl
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LIB_DEPS += axi_ad9361
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LIB_DEPS += axi_dmac
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LIB_DEPS += axi_gpreg
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LIB_DEPS += util_clkdiv
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LIB_DEPS += util_pack/util_cpack2
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LIB_DEPS += util_pack/util_upack2
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LIB_DEPS += util_rfifo
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LIB_DEPS += util_tdd_sync
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LIB_DEPS += util_wfifo
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LIB_DEPS += xilinx/axi_xcvrlb
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LIB_DEPS += xilinx/util_clkdiv
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include ../../scripts/project-xilinx.mk
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@ -17,11 +17,11 @@ M_DEPS += ../../../library/axi_ad9361/axi_ad9361_delay.tcl
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LIB_DEPS += axi_ad9361
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LIB_DEPS += axi_dmac
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LIB_DEPS += axi_i2s_adi
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LIB_DEPS += util_clkdiv
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LIB_DEPS += util_pack/util_cpack2
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LIB_DEPS += util_pack/util_upack2
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LIB_DEPS += util_rfifo
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LIB_DEPS += util_tdd_sync
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LIB_DEPS += util_wfifo
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LIB_DEPS += xilinx/util_clkdiv
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include ../../scripts/project-xilinx.mk
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@ -21,12 +21,12 @@ LIB_DEPS += axi_gpreg
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LIB_DEPS += axi_hdmi_tx
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LIB_DEPS += axi_i2s_adi
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LIB_DEPS += axi_spdif_tx
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LIB_DEPS += util_clkdiv
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LIB_DEPS += util_pack/util_cpack2
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LIB_DEPS += util_pack/util_upack2
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LIB_DEPS += util_rfifo
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LIB_DEPS += util_tdd_sync
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LIB_DEPS += util_wfifo
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LIB_DEPS += xilinx/axi_xcvrlb
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LIB_DEPS += xilinx/util_clkdiv
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include ../../scripts/project-xilinx.mk
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@ -16,11 +16,11 @@ M_DEPS += ../../../library/axi_ad9361/axi_ad9361_delay.tcl
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LIB_DEPS += axi_ad9361
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LIB_DEPS += axi_dmac
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LIB_DEPS += axi_gpreg
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LIB_DEPS += util_clkdiv
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LIB_DEPS += util_pack/util_cpack2
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LIB_DEPS += util_pack/util_upack2
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LIB_DEPS += util_rfifo
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LIB_DEPS += util_tdd_sync
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LIB_DEPS += util_wfifo
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LIB_DEPS += xilinx/util_clkdiv
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include ../../scripts/project-xilinx.mk
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@ -16,11 +16,11 @@ M_DEPS += ../../../library/axi_ad9361/axi_ad9361_delay.tcl
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LIB_DEPS += axi_ad9361
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LIB_DEPS += axi_dmac
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LIB_DEPS += axi_gpreg
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LIB_DEPS += util_clkdiv
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LIB_DEPS += util_pack/util_cpack2
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LIB_DEPS += util_pack/util_upack2
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LIB_DEPS += util_rfifo
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LIB_DEPS += util_tdd_sync
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LIB_DEPS += util_wfifo
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LIB_DEPS += xilinx/util_clkdiv
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include ../../scripts/project-xilinx.mk
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@ -17,11 +17,11 @@ M_DEPS += ../../../library/axi_ad9361/axi_ad9361_delay.tcl
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LIB_DEPS += axi_ad9361
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LIB_DEPS += axi_dmac
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LIB_DEPS += axi_i2s_adi
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LIB_DEPS += util_clkdiv
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LIB_DEPS += util_pack/util_cpack2
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LIB_DEPS += util_pack/util_upack2
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LIB_DEPS += util_rfifo
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LIB_DEPS += util_tdd_sync
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LIB_DEPS += util_wfifo
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LIB_DEPS += xilinx/util_clkdiv
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include ../../scripts/project-xilinx.mk
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@ -14,11 +14,11 @@ M_DEPS += ../../../library/axi_ad9361/axi_ad9361_delay.tcl
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LIB_DEPS += axi_ad9361
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LIB_DEPS += axi_dmac
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LIB_DEPS += util_clkdiv
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LIB_DEPS += util_pack/util_cpack2
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LIB_DEPS += util_pack/util_upack2
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LIB_DEPS += util_rfifo
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LIB_DEPS += util_tdd_sync
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LIB_DEPS += util_wfifo
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LIB_DEPS += xilinx/util_clkdiv
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include ../../scripts/project-xilinx.mk
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@ -15,11 +15,11 @@ M_DEPS += ../../../library/axi_ad9361/axi_ad9361_delay.tcl
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LIB_DEPS += axi_ad9361
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LIB_DEPS += axi_dmac
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LIB_DEPS += util_clkdiv
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LIB_DEPS += util_pack/util_cpack2
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LIB_DEPS += util_pack/util_upack2
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LIB_DEPS += util_rfifo
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LIB_DEPS += util_tdd_sync
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LIB_DEPS += util_wfifo
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LIB_DEPS += xilinx/util_clkdiv
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include ../../scripts/project-xilinx.mk
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@ -14,11 +14,11 @@ M_DEPS += ../../../library/axi_ad9361/axi_ad9361_delay.tcl
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LIB_DEPS += axi_ad9361
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LIB_DEPS += axi_dmac
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LIB_DEPS += util_clkdiv
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LIB_DEPS += util_pack/util_cpack2
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LIB_DEPS += util_pack/util_upack2
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LIB_DEPS += util_rfifo
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LIB_DEPS += util_tdd_sync
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LIB_DEPS += util_wfifo
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LIB_DEPS += xilinx/util_clkdiv
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include ../../scripts/project-xilinx.mk
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@ -16,11 +16,11 @@ LIB_DEPS += axi_clkgen
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LIB_DEPS += axi_dmac
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LIB_DEPS += axi_hdmi_tx
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LIB_DEPS += axi_spdif_tx
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LIB_DEPS += util_clkdiv
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LIB_DEPS += util_pack/util_cpack2
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LIB_DEPS += util_pack/util_upack2
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LIB_DEPS += util_rfifo
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LIB_DEPS += util_tdd_sync
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LIB_DEPS += util_wfifo
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LIB_DEPS += xilinx/util_clkdiv
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include ../../scripts/project-xilinx.mk
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LIB_DEPS += axi_dmac
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LIB_DEPS += axi_hdmi_tx
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LIB_DEPS += axi_spdif_tx
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LIB_DEPS += util_clkdiv
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LIB_DEPS += util_pack/util_cpack2
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LIB_DEPS += util_pack/util_upack2
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LIB_DEPS += util_rfifo
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LIB_DEPS += util_tdd_sync
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LIB_DEPS += util_wfifo
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LIB_DEPS += xilinx/util_clkdiv
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include ../../scripts/project-xilinx.mk
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@ -13,11 +13,11 @@ M_DEPS += ../../../library/axi_ad9361/axi_ad9361_delay.tcl
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LIB_DEPS += axi_ad9361
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LIB_DEPS += axi_dmac
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LIB_DEPS += util_clkdiv
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LIB_DEPS += util_pack/util_cpack2
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LIB_DEPS += util_pack/util_upack2
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LIB_DEPS += util_rfifo
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LIB_DEPS += util_tdd_sync
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LIB_DEPS += util_wfifo
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LIB_DEPS += xilinx/util_clkdiv
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include ../../scripts/project-xilinx.mk
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@ -17,12 +17,12 @@ LIB_DEPS += axi_dmac
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LIB_DEPS += axi_hdmi_tx
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LIB_DEPS += axi_i2s_adi
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LIB_DEPS += axi_spdif_tx
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LIB_DEPS += util_clkdiv
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LIB_DEPS += util_i2c_mixer
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LIB_DEPS += util_pack/util_cpack2
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LIB_DEPS += util_pack/util_upack2
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LIB_DEPS += util_rfifo
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LIB_DEPS += util_tdd_sync
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LIB_DEPS += util_wfifo
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LIB_DEPS += xilinx/util_clkdiv
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include ../../scripts/project-xilinx.mk
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@ -16,10 +16,10 @@ LIB_DEPS += axi_clkgen
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LIB_DEPS += axi_dmac
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LIB_DEPS += axi_hdmi_tx
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LIB_DEPS += axi_spdif_tx
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LIB_DEPS += util_clkdiv
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LIB_DEPS += util_pack/util_cpack2
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LIB_DEPS += util_pack/util_upack2
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LIB_DEPS += util_rfifo
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LIB_DEPS += util_wfifo
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LIB_DEPS += xilinx/util_clkdiv
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include ../../scripts/project-xilinx.mk
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@ -16,10 +16,10 @@ LIB_DEPS += axi_clkgen
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LIB_DEPS += axi_dmac
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LIB_DEPS += axi_hdmi_tx
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LIB_DEPS += axi_spdif_tx
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LIB_DEPS += util_clkdiv
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LIB_DEPS += util_pack/util_cpack2
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LIB_DEPS += util_pack/util_upack2
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LIB_DEPS += util_rfifo
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LIB_DEPS += util_wfifo
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LIB_DEPS += xilinx/util_clkdiv
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include ../../scripts/project-xilinx.mk
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@ -13,10 +13,10 @@ M_DEPS += ../../../library/axi_ad9361/axi_ad9361_delay.tcl
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LIB_DEPS += axi_ad9361
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LIB_DEPS += axi_dmac
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LIB_DEPS += util_clkdiv
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LIB_DEPS += util_pack/util_cpack2
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LIB_DEPS += util_pack/util_upack2
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LIB_DEPS += util_rfifo
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LIB_DEPS += util_wfifo
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LIB_DEPS += xilinx/util_clkdiv
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include ../../scripts/project-xilinx.mk
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