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util_clkdiv: Seperate the IP source into an intel and xilinx version

main
Istvan Csomortani 2019-04-01 10:41:00 +01:00 committed by István Csomortáni
parent 84bd50d437
commit b0fbe1bb57
26 changed files with 40 additions and 30 deletions
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5
library/Makefile
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@ -67,6 +67,7 @@ clean:
$(MAKE) -C intel/common/alt_mem_asym clean
$(MAKE) -C intel/common/alt_serdes clean
$(MAKE) -C intel/jesd204_phy clean
$(MAKE) -C intel/util_clkdiv clean
$(MAKE) -C jesd204/ad_ip_jesd204_tpl_adc clean
$(MAKE) -C jesd204/ad_ip_jesd204_tpl_dac clean
$(MAKE) -C jesd204/axi_jesd204_common clean
@ -90,7 +91,6 @@ clean:
$(MAKE) -C util_bsplit clean
$(MAKE) -C util_cdc clean
$(MAKE) -C util_cic clean
$(MAKE) -C util_clkdiv clean
$(MAKE) -C util_dacfifo clean
$(MAKE) -C util_dec256sinc24b clean
$(MAKE) -C util_delay clean
@ -113,6 +113,7 @@ clean:
$(MAKE) -C xilinx/axi_dacfifo clean
$(MAKE) -C xilinx/axi_xcvrlb clean
$(MAKE) -C xilinx/util_adxcvr clean
$(MAKE) -C xilinx/util_clkdiv clean
$(MAKE) -C interfaces clean
@ -176,6 +177,7 @@ lib:
$(MAKE) -C intel/common/alt_mem_asym
$(MAKE) -C intel/common/alt_serdes
$(MAKE) -C intel/jesd204_phy
$(MAKE) -C intel/util_clkdiv
$(MAKE) -C jesd204/ad_ip_jesd204_tpl_adc
$(MAKE) -C jesd204/ad_ip_jesd204_tpl_dac
$(MAKE) -C jesd204/axi_jesd204_common
@ -221,6 +223,7 @@ lib:
$(MAKE) -C xilinx/axi_dacfifo
$(MAKE) -C xilinx/axi_xcvrlb
$(MAKE) -C xilinx/util_adxcvr
$(MAKE) -C xilinx/util_clkdiv
$(MAKE) -C interfaces

11
library/intel/util_clkdiv/Makefile Normal file
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@ -0,0 +1,11 @@
####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := util_clkdiv
INTEL_DEPS += util_clkdiv.v
INTEL_DEPS += util_clkdiv_hw.tcl
include ../../scripts/library.mk

4
library/util_clkdiv/util_clkdiv_alt.v → library/intel/util_clkdiv/util_clkdiv.v
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@ -39,7 +39,7 @@
// clk_sel is 1. Provides a glitch free output clock
// IP uses BUFR/BUFGCE_DIV and BUFGMUX_CTRL primitives
module util_clkdiv_alt #(
module util_clkdiv #(
parameter SIM_DEVICE = "CYCLONE5",
parameter CLOCK_TYPE = "Global Clock") (
@ -76,4 +76,4 @@ generate if (SIM_DEVICE == "CYCLONE5") begin
end endgenerate
endmodule // util_clkdiv_alt
endmodule // util_clkdiv

8
library/util_clkdiv/util_clkdiv_hw.tcl → library/intel/util_clkdiv/util_clkdiv_hw.tcl
View File

@ -1,7 +1,7 @@
package require -exact qsys 13.0
source ../scripts/adi_env.tcl
source ../scripts/adi_ip_intel.tcl
source ../../scripts/adi_env.tcl
source ../../scripts/adi_ip_intel.tcl
set_module_property NAME util_clkdiv
@ -13,8 +13,8 @@ set_module_property DISPLAY_NAME util_clkdiv
# files
add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
set_fileset_property quartus_synth TOP_LEVEL util_clkdiv_alt
add_fileset_file util_clkdiv_alt.v VERILOG PATH util_clkdiv_alt.v TOP_LEVEL_FILE
set_fileset_property quartus_synth TOP_LEVEL util_clkdiv
add_fileset_file util_clkdiv.v VERILOG PATH util_clkdiv.v TOP_LEVEL_FILE
# defaults

6
library/util_clkdiv/Makefile → library/xilinx/util_clkdiv/Makefile
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@ -5,13 +5,9 @@
LIBRARY_NAME := util_clkdiv
XILINX_DEPS += util_clkdiv.v
XILINX_DEPS += util_clkdiv_constr.xdc
XILINX_DEPS += util_clkdiv_ooc.ttcl
XILINX_DEPS += util_clkdiv_ip.tcl
INTEL_DEPS += util_clkdiv_alt.v
INTEL_DEPS += util_clkdiv_hw.tcl
include ../scripts/library.mk
include ../../scripts/library.mk

0
library/util_clkdiv/util_clkdiv.v → library/xilinx/util_clkdiv/util_clkdiv.v
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0
library/util_clkdiv/util_clkdiv_constr.xdc → library/xilinx/util_clkdiv/util_clkdiv_constr.xdc
View File

2
library/util_clkdiv/util_clkdiv_ip.tcl → library/xilinx/util_clkdiv/util_clkdiv_ip.tcl
View File

@ -1,4 +1,4 @@
source ../scripts/adi_env.tcl
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
adi_ip_create util_clkdiv

0
library/util_clkdiv/util_clkdiv_ooc.ttcl → library/xilinx/util_clkdiv/util_clkdiv_ooc.ttcl
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2
projects/adrv9361z7035/ccbob_cmos/Makefile
View File

@ -16,12 +16,12 @@ M_DEPS += ../../../library/axi_ad9361/axi_ad9361_delay.tcl
LIB_DEPS += axi_ad9361
LIB_DEPS += axi_dmac
LIB_DEPS += axi_gpreg
LIB_DEPS += util_clkdiv
LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += util_pack/util_upack2
LIB_DEPS += util_rfifo
LIB_DEPS += util_tdd_sync
LIB_DEPS += util_wfifo
LIB_DEPS += xilinx/axi_xcvrlb
LIB_DEPS += xilinx/util_clkdiv
include ../../scripts/project-xilinx.mk

2
projects/adrv9361z7035/ccbob_lvds/Makefile
View File

@ -16,12 +16,12 @@ M_DEPS += ../../../library/axi_ad9361/axi_ad9361_delay.tcl
LIB_DEPS += axi_ad9361
LIB_DEPS += axi_dmac
LIB_DEPS += axi_gpreg
LIB_DEPS += util_clkdiv
LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += util_pack/util_upack2
LIB_DEPS += util_rfifo
LIB_DEPS += util_tdd_sync
LIB_DEPS += util_wfifo
LIB_DEPS += xilinx/axi_xcvrlb
LIB_DEPS += xilinx/util_clkdiv
include ../../scripts/project-xilinx.mk

2
projects/adrv9361z7035/ccbox_lvds/Makefile
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@ -17,11 +17,11 @@ M_DEPS += ../../../library/axi_ad9361/axi_ad9361_delay.tcl
LIB_DEPS += axi_ad9361
LIB_DEPS += axi_dmac
LIB_DEPS += axi_i2s_adi
LIB_DEPS += util_clkdiv
LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += util_pack/util_upack2
LIB_DEPS += util_rfifo
LIB_DEPS += util_tdd_sync
LIB_DEPS += util_wfifo
LIB_DEPS += xilinx/util_clkdiv
include ../../scripts/project-xilinx.mk

2
projects/adrv9361z7035/ccfmc_lvds/Makefile
View File

@ -21,12 +21,12 @@ LIB_DEPS += axi_gpreg
LIB_DEPS += axi_hdmi_tx
LIB_DEPS += axi_i2s_adi
LIB_DEPS += axi_spdif_tx
LIB_DEPS += util_clkdiv
LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += util_pack/util_upack2
LIB_DEPS += util_rfifo
LIB_DEPS += util_tdd_sync
LIB_DEPS += util_wfifo
LIB_DEPS += xilinx/axi_xcvrlb
LIB_DEPS += xilinx/util_clkdiv
include ../../scripts/project-xilinx.mk

2
projects/adrv9364z7020/ccbob_cmos/Makefile
View File

@ -16,11 +16,11 @@ M_DEPS += ../../../library/axi_ad9361/axi_ad9361_delay.tcl
LIB_DEPS += axi_ad9361
LIB_DEPS += axi_dmac
LIB_DEPS += axi_gpreg
LIB_DEPS += util_clkdiv
LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += util_pack/util_upack2
LIB_DEPS += util_rfifo
LIB_DEPS += util_tdd_sync
LIB_DEPS += util_wfifo
LIB_DEPS += xilinx/util_clkdiv
include ../../scripts/project-xilinx.mk

2
projects/adrv9364z7020/ccbob_lvds/Makefile
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@ -16,11 +16,11 @@ M_DEPS += ../../../library/axi_ad9361/axi_ad9361_delay.tcl
LIB_DEPS += axi_ad9361
LIB_DEPS += axi_dmac
LIB_DEPS += axi_gpreg
LIB_DEPS += util_clkdiv
LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += util_pack/util_upack2
LIB_DEPS += util_rfifo
LIB_DEPS += util_tdd_sync
LIB_DEPS += util_wfifo
LIB_DEPS += xilinx/util_clkdiv
include ../../scripts/project-xilinx.mk

2
projects/adrv9364z7020/ccbox_lvds/Makefile
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@ -17,11 +17,11 @@ M_DEPS += ../../../library/axi_ad9361/axi_ad9361_delay.tcl
LIB_DEPS += axi_ad9361
LIB_DEPS += axi_dmac
LIB_DEPS += axi_i2s_adi
LIB_DEPS += util_clkdiv
LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += util_pack/util_upack2
LIB_DEPS += util_rfifo
LIB_DEPS += util_tdd_sync
LIB_DEPS += util_wfifo
LIB_DEPS += xilinx/util_clkdiv
include ../../scripts/project-xilinx.mk

2
projects/fmcomms2/kc705/Makefile
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@ -14,11 +14,11 @@ M_DEPS += ../../../library/axi_ad9361/axi_ad9361_delay.tcl
LIB_DEPS += axi_ad9361
LIB_DEPS += axi_dmac
LIB_DEPS += util_clkdiv
LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += util_pack/util_upack2
LIB_DEPS += util_rfifo
LIB_DEPS += util_tdd_sync
LIB_DEPS += util_wfifo
LIB_DEPS += xilinx/util_clkdiv
include ../../scripts/project-xilinx.mk

2
projects/fmcomms2/kcu105/Makefile
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@ -15,11 +15,11 @@ M_DEPS += ../../../library/axi_ad9361/axi_ad9361_delay.tcl
LIB_DEPS += axi_ad9361
LIB_DEPS += axi_dmac
LIB_DEPS += util_clkdiv
LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += util_pack/util_upack2
LIB_DEPS += util_rfifo
LIB_DEPS += util_tdd_sync
LIB_DEPS += util_wfifo
LIB_DEPS += xilinx/util_clkdiv
include ../../scripts/project-xilinx.mk

2
projects/fmcomms2/vc707/Makefile
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@ -14,11 +14,11 @@ M_DEPS += ../../../library/axi_ad9361/axi_ad9361_delay.tcl
LIB_DEPS += axi_ad9361
LIB_DEPS += axi_dmac
LIB_DEPS += util_clkdiv
LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += util_pack/util_upack2
LIB_DEPS += util_rfifo
LIB_DEPS += util_tdd_sync
LIB_DEPS += util_wfifo
LIB_DEPS += xilinx/util_clkdiv
include ../../scripts/project-xilinx.mk

2
projects/fmcomms2/zc702/Makefile
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@ -16,11 +16,11 @@ LIB_DEPS += axi_clkgen
LIB_DEPS += axi_dmac
LIB_DEPS += axi_hdmi_tx
LIB_DEPS += axi_spdif_tx
LIB_DEPS += util_clkdiv
LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += util_pack/util_upack2
LIB_DEPS += util_rfifo
LIB_DEPS += util_tdd_sync
LIB_DEPS += util_wfifo
LIB_DEPS += xilinx/util_clkdiv
include ../../scripts/project-xilinx.mk

2
projects/fmcomms2/zc706/Makefile
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@ -16,11 +16,11 @@ LIB_DEPS += axi_clkgen
LIB_DEPS += axi_dmac
LIB_DEPS += axi_hdmi_tx
LIB_DEPS += axi_spdif_tx
LIB_DEPS += util_clkdiv
LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += util_pack/util_upack2
LIB_DEPS += util_rfifo
LIB_DEPS += util_tdd_sync
LIB_DEPS += util_wfifo
LIB_DEPS += xilinx/util_clkdiv
include ../../scripts/project-xilinx.mk

2
projects/fmcomms2/zcu102/Makefile
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@ -13,11 +13,11 @@ M_DEPS += ../../../library/axi_ad9361/axi_ad9361_delay.tcl
LIB_DEPS += axi_ad9361
LIB_DEPS += axi_dmac
LIB_DEPS += util_clkdiv
LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += util_pack/util_upack2
LIB_DEPS += util_rfifo
LIB_DEPS += util_tdd_sync
LIB_DEPS += util_wfifo
LIB_DEPS += xilinx/util_clkdiv
include ../../scripts/project-xilinx.mk

2
projects/fmcomms2/zed/Makefile
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@ -17,12 +17,12 @@ LIB_DEPS += axi_dmac
LIB_DEPS += axi_hdmi_tx
LIB_DEPS += axi_i2s_adi
LIB_DEPS += axi_spdif_tx
LIB_DEPS += util_clkdiv
LIB_DEPS += util_i2c_mixer
LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += util_pack/util_upack2
LIB_DEPS += util_rfifo
LIB_DEPS += util_tdd_sync
LIB_DEPS += util_wfifo
LIB_DEPS += xilinx/util_clkdiv
include ../../scripts/project-xilinx.mk

2
projects/fmcomms5/zc702/Makefile
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@ -16,10 +16,10 @@ LIB_DEPS += axi_clkgen
LIB_DEPS += axi_dmac
LIB_DEPS += axi_hdmi_tx
LIB_DEPS += axi_spdif_tx
LIB_DEPS += util_clkdiv
LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += util_pack/util_upack2
LIB_DEPS += util_rfifo
LIB_DEPS += util_wfifo
LIB_DEPS += xilinx/util_clkdiv
include ../../scripts/project-xilinx.mk

2
projects/fmcomms5/zc706/Makefile
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@ -16,10 +16,10 @@ LIB_DEPS += axi_clkgen
LIB_DEPS += axi_dmac
LIB_DEPS += axi_hdmi_tx
LIB_DEPS += axi_spdif_tx
LIB_DEPS += util_clkdiv
LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += util_pack/util_upack2
LIB_DEPS += util_rfifo
LIB_DEPS += util_wfifo
LIB_DEPS += xilinx/util_clkdiv
include ../../scripts/project-xilinx.mk

2
projects/fmcomms5/zcu102/Makefile
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@ -13,10 +13,10 @@ M_DEPS += ../../../library/axi_ad9361/axi_ad9361_delay.tcl
LIB_DEPS += axi_ad9361
LIB_DEPS += axi_dmac
LIB_DEPS += util_clkdiv
LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += util_pack/util_upack2
LIB_DEPS += util_rfifo
LIB_DEPS += util_wfifo
LIB_DEPS += xilinx/util_clkdiv
include ../../scripts/project-xilinx.mk