From b0f90bd0e8a37b80b80e3bacd869225e0aa69147 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Fri, 4 Mar 2016 18:56:21 +0200 Subject: [PATCH] daq1/cpld: Read interface fix --- projects/daq1/cpld/daq1_cpld.v | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/projects/daq1/cpld/daq1_cpld.v b/projects/daq1/cpld/daq1_cpld.v index 6306a9316..6671ae029 100644 --- a/projects/daq1/cpld/daq1_cpld.v +++ b/projects/daq1/cpld/daq1_cpld.v @@ -177,7 +177,7 @@ module daq1_cpld ( assign cpld_rdata_s = cpld_spicsn ? sdio : cpld_rdata_bit; assign rdnwr = fmc_cpld_addr[7]; - assign sclk = (~(fmc_spi_csn | fmc_spi_csn_enb)) ? fmc_spi_sclk : 1'b0; + assign sclk = (~(fmc_spi_csn | fmc_spi_csn_enb)) ? fmc_spi_sclk : 1'b0; always @(negedge fmc_spi_sclk or posedge fmc_spi_csn) begin if (fmc_spi_csn == 1'b1) begin @@ -222,8 +222,8 @@ module daq1_cpld ( always @(negedge fmc_spi_sclk or posedge fmc_spi_csn) begin if (fmc_spi_csn == 1'b1) begin - cpld_rdata_bit <= 1'b0; - cpld_rdata_index <= 3'h7; + cpld_rdata_bit <= cpld_rdata[7]; + cpld_rdata_index <= 3'h6; end else begin if (cpld_to_fpga == 1'b1) begin cpld_rdata_bit <= cpld_rdata[cpld_rdata_index];