cn0506_rgmii: base design initial commit
AndreiGrozav
AndreiGrozav
parent
7c3b4a5c73
commit
afd9420dab
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####################################################################################
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## Copyright 2018(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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include ../scripts/project-toplevel.mk
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create_bd_port -dir I ref_clk_125
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create_bd_port -dir O reset
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create_bd_port -dir O -from 1 -to 0 -type data speed_mode_a
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create_bd_port -dir O -from 1 -to 0 -type data speed_mode_b
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ad_ip_instance gmii_to_rgmii gmii_to_rgmii_0
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ad_ip_parameter gmii_to_rgmii_0 CONFIG.SupportLevel Include_Shared_Logic_in_Core
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# 200MHz for 7 series; 375 for ultrascale
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ad_ip_instance clk_wiz clk_wiz
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ad_ip_parameter clk_wiz CONFIG.PRIM_IN_FREQ 125
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ad_ip_parameter clk_wiz CONFIG.MMCM_CLKIN1_PERIOD 8.000
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ad_ip_parameter clk_wiz CONFIG.CLKOUT1_REQUESTED_OUT_FREQ 375
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ad_ip_parameter clk_wiz CONFIG.PRIM_SOURCE "No_buffer"
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make_bd_intf_pins_external [get_bd_intf_pins gmii_to_rgmii_0/MDIO_PHY]
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make_bd_intf_pins_external [get_bd_intf_pins gmii_to_rgmii_0/RGMII]
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ad_ip_instance proc_sys_reset proc_rgmii_reset
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ad_connect gmii_to_rgmii_0/clkin clk_wiz/clk_out1
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ad_connect ref_clk_125 clk_wiz/clk_in1
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ad_connect sys_rstgen/peripheral_reset clk_wiz/reset
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ad_connect proc_rgmii_reset/ext_reset_in sys_rstgen/peripheral_reset
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ad_connect reset proc_rgmii_reset/peripheral_reset
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ad_connect proc_rgmii_reset/dcm_locked clk_wiz/locked
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ad_connect proc_rgmii_reset/slowest_sync_clk clk_wiz/clk_out1
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ad_connect proc_rgmii_reset/peripheral_reset gmii_to_rgmii_0/tx_reset
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ad_connect gmii_to_rgmii_0/rx_reset proc_rgmii_reset/peripheral_reset
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make_bd_pins_external [get_bd_pins gmii_to_rgmii_0/clock_speed]
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ad_ip_instance gmii_to_rgmii gmii_to_rgmii_1
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ad_ip_parameter gmii_to_rgmii_1 CONFIG.SupportLevel {Include_Shared_Logic_in_Example_Design}
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make_bd_intf_pins_external [get_bd_intf_pins gmii_to_rgmii_1/MDIO_PHY]
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make_bd_intf_pins_external [get_bd_intf_pins gmii_to_rgmii_1/RGMII]
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ad_connect gmii_to_rgmii_1/ref_clk_in gmii_to_rgmii_0/ref_clk_out
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ad_connect gmii_to_rgmii_1/mmcm_locked_in gmii_to_rgmii_0/mmcm_locked_out
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ad_connect gmii_to_rgmii_1/gmii_clk_125m_in gmii_to_rgmii_0/gmii_clk_125m_out
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ad_connect gmii_to_rgmii_1/gmii_clk_25m_in gmii_to_rgmii_0/gmii_clk_25m_out
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ad_connect gmii_to_rgmii_1/gmii_clk_2_5m_in gmii_to_rgmii_0/gmii_clk_2_5m_out
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ad_connect proc_rgmii_reset/peripheral_reset gmii_to_rgmii_1/tx_reset
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ad_connect gmii_to_rgmii_1/rx_reset proc_rgmii_reset/peripheral_reset
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ad_connect gmii_to_rgmii_0/speed_mode speed_mode_a
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ad_connect gmii_to_rgmii_1/speed_mode speed_mode_b
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#system ID
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ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
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ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt"
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ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
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set sys_cstring "sys rom custom string placeholder"
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sysid_gen_sys_init_file $sys_cstring
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# Instances and instance parameters
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add_instance gmii_to_rgmii_adapter_0 altera_gmii_to_rgmii_adapter
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set_instance_parameter_value gmii_to_rgmii_adapter_0 {RX_PIPELINE_DEPTH} {1}
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set_instance_parameter_value gmii_to_rgmii_adapter_0 {TX_PIPELINE_DEPTH} {1}
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add_instance hps_emac_interface_splitter_0 altera_hps_emac_interface_splitter
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add_instance gmii_to_rgmii_adapter_1 altera_gmii_to_rgmii_adapter
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set_instance_parameter_value gmii_to_rgmii_adapter_1 {RX_PIPELINE_DEPTH} {1}
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set_instance_parameter_value gmii_to_rgmii_adapter_1 {TX_PIPELINE_DEPTH} {1}
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add_instance hps_emac_interface_splitter_1 altera_hps_emac_interface_splitter
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add_instance iopll_0 altera_iopll
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set_instance_parameter_value iopll_0 {gui_active_clk} {0}
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set_instance_parameter_value iopll_0 {gui_c_cnt_in_src0} {c_m_cnt_in_src_ph_mux_clk}
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set_instance_parameter_value iopll_0 {gui_c_cnt_in_src1} {c_m_cnt_in_src_ph_mux_clk}
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set_instance_parameter_value iopll_0 {gui_cal_error} {cal_clean}
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set_instance_parameter_value iopll_0 {gui_cascade_counter0} {0}
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set_instance_parameter_value iopll_0 {gui_cascade_counter1} {0}
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set_instance_parameter_value iopll_0 {gui_cascade_outclk_index} {0}
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set_instance_parameter_value iopll_0 {gui_clk_bad} {0}
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set_instance_parameter_value iopll_0 {gui_clock_name_global} {0}
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set_instance_parameter_value iopll_0 {gui_clock_name_string0} {outclk0}
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set_instance_parameter_value iopll_0 {gui_clock_name_string1} {outclk1}
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set_instance_parameter_value iopll_0 {gui_clock_name_string2} {outclk2}
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set_instance_parameter_value iopll_0 {gui_divide_factor_c0} {6}
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set_instance_parameter_value iopll_0 {gui_divide_factor_c1} {6}
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set_instance_parameter_value iopll_0 {gui_divide_factor_n} {1}
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set_instance_parameter_value iopll_0 {gui_dps_cntr} {C0}
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set_instance_parameter_value iopll_0 {gui_dps_dir} {Positive}
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set_instance_parameter_value iopll_0 {gui_dps_num} {1}
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set_instance_parameter_value iopll_0 {gui_dsm_out_sel} {1st_order}
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set_instance_parameter_value iopll_0 {gui_duty_cycle0} {50.0}
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set_instance_parameter_value iopll_0 {gui_duty_cycle1} {50.0}
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set_instance_parameter_value iopll_0 {gui_en_adv_params} {0}
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set_instance_parameter_value iopll_0 {gui_en_dps_ports} {0}
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set_instance_parameter_value iopll_0 {gui_en_extclkout_ports} {0}
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set_instance_parameter_value iopll_0 {gui_en_phout_ports} {0}
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set_instance_parameter_value iopll_0 {gui_extclkout_0_source} {C0}
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set_instance_parameter_value iopll_0 {gui_extclkout_1_source} {C0}
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set_instance_parameter_value iopll_0 {gui_feedback_clock} {Global Clock}
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set_instance_parameter_value iopll_0 {gui_fix_vco_frequency} {0}
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set_instance_parameter_value iopll_0 {gui_fixed_vco_frequency} {600.0}
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set_instance_parameter_value iopll_0 {gui_frac_multiply_factor} {1.0}
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set_instance_parameter_value iopll_0 {gui_fractional_cout} {32}
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set_instance_parameter_value iopll_0 {gui_multiply_factor} {6}
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set_instance_parameter_value iopll_0 {gui_number_of_clocks} {2}
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set_instance_parameter_value iopll_0 {gui_operation_mode} {direct}
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set_instance_parameter_value iopll_0 {gui_output_clock_frequency0} {2.5}
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set_instance_parameter_value iopll_0 {gui_output_clock_frequency1} {25.0}
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set_instance_parameter_value iopll_0 {gui_parameter_table_hex_file} {seq_params_sim.hex}
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set_instance_parameter_value iopll_0 {gui_phase_shift0} {0.0}
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set_instance_parameter_value iopll_0 {gui_phase_shift1} {0.0}
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set_instance_parameter_value iopll_0 {gui_phout_division} {1}
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set_instance_parameter_value iopll_0 {gui_pll_auto_reset} {0}
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set_instance_parameter_value iopll_0 {gui_pll_bandwidth_preset} {Low}
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set_instance_parameter_value iopll_0 {gui_pll_freqcal_en} {1}
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set_instance_parameter_value iopll_0 {gui_pll_m_cnt_in_src} {c_m_cnt_in_src_ph_mux_clk}
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set_instance_parameter_value iopll_0 {gui_pll_mode} {Integer-N PLL}
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set_instance_parameter_value iopll_0 {gui_pll_tclk_mux_en} {0}
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set_instance_parameter_value iopll_0 {gui_pll_tclk_sel} {pll_tclk_m_src}
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set_instance_parameter_value iopll_0 {gui_pll_type} {S10_Simple}
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set_instance_parameter_value iopll_0 {gui_pll_vco_freq_band_0} {pll_freq_clk0_disabled}
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set_instance_parameter_value iopll_0 {gui_pll_vco_freq_band_1} {pll_freq_clk1_disabled}
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set_instance_parameter_value iopll_0 {gui_ps_units0} {ps}
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set_instance_parameter_value iopll_0 {gui_ps_units1} {ps}
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set_instance_parameter_value iopll_0 {gui_refclk1_frequency} {100.0}
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set_instance_parameter_value iopll_0 {gui_refclk_switch} {0}
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set_instance_parameter_value iopll_0 {gui_reference_clock_frequency} {100.0}
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set_instance_parameter_value iopll_0 {gui_switchover_delay} {0}
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set_instance_parameter_value iopll_0 {gui_use_locked} {1}
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set_instance_parameter_value iopll_0 {gui_usr_device_speed_grade} {1}
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set_instance_parameter_value iopll_0 {gui_vco_frequency} {600.0}
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set_instance_parameter_value iopll_0 {hp_qsys_scripting_mode} {0}
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set_instance_parameter_value sys_hps {CLK_PERI_PLL_SOURCE2} {0}
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set_instance_parameter_value sys_hps {EMAC1_CLK} {250}
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set_instance_parameter_value sys_hps {EMAC1_Mode} {RGMII_with_MDIO}
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set_instance_parameter_value sys_hps {EMAC1_PTP} {0}
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set_instance_parameter_value sys_hps {EMAC1_PinMuxing} {FPGA}
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set_instance_parameter_value sys_hps {EMAC1_SWITCH_Enable} {0}
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set_instance_parameter_value sys_hps {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_GTX_CLK} {125}
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set_instance_parameter_value sys_hps {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_MD_CLK} {2.5}
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set_instance_parameter_value sys_hps {EMAC2_CLK} {250}
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set_instance_parameter_value sys_hps {EMAC2_Mode} {RGMII_with_MDIO}
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set_instance_parameter_value sys_hps {EMAC2_PTP} {0}
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set_instance_parameter_value sys_hps {EMAC2_PinMuxing} {FPGA}
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set_instance_parameter_value sys_hps {EMAC2_SWITCH_Enable} {0}
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set_instance_parameter_value sys_hps {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC2_GTX_CLK} {125}
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set_instance_parameter_value sys_hps {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC2_MD_CLK} {2.5}
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set_instance_parameter_value sys_hps {EMAC_PTP_REF_CLK} {100}
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set_instance_parameter_value sys_hps {EMIF_BYPASS_CHECK} {0}
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set_instance_parameter_value sys_hps {EMIF_CONDUIT_Enable} {1}
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# exported interfaces
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add_interface sys_hps_emac1_md_clk clock source
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set_interface_property sys_hps_emac1_md_clk EXPORT_OF sys_hps.emac1_md_clk
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add_interface sys_hps_emac2_md_clk clock source
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set_interface_property sys_hps_emac2_md_clk EXPORT_OF sys_hps.emac2_md_clk
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add_interface gmii_to_rgmii_adapter_0_phy_rgmii conduit end
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set_interface_property gmii_to_rgmii_adapter_0_phy_rgmii EXPORT_OF gmii_to_rgmii_adapter_0.phy_rgmii
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add_interface hps_emac_interface_splitter_0_mdio conduit end
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set_interface_property hps_emac_interface_splitter_0_mdio EXPORT_OF hps_emac_interface_splitter_0.mdio
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add_interface hps_emac_interface_splitter_0_ptp conduit end
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set_interface_property hps_emac_interface_splitter_0_ptp EXPORT_OF hps_emac_interface_splitter_0.ptp
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add_interface iopll_0_locked conduit end
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set_interface_property iopll_0_locked EXPORT_OF iopll_0.locked
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add_interface gmii_to_rgmii_adapter_0_hps_gmii conduit end
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set_interface_property gmii_to_rgmii_adapter_0_hps_gmii EXPORT_OF gmii_to_rgmii_adapter_0.hps_gmii
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add_interface hps_emac_interface_splitter_0_hps_gmii conduit end
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set_interface_property hps_emac_interface_splitter_0_hps_gmii EXPORT_OF hps_emac_interface_splitter_0.hps_gmii
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add_interface gmii_to_rgmii_adapter_1_hps_gmii conduit end
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set_interface_property gmii_to_rgmii_adapter_1_hps_gmii EXPORT_OF gmii_to_rgmii_adapter_1.hps_gmii
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add_interface hps_emac_interface_splitter_1_hps_gmii conduit end
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set_interface_property hps_emac_interface_splitter_1_hps_gmii EXPORT_OF hps_emac_interface_splitter_1.hps_gmii
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add_interface gmii_to_rgmii_adapter_1_phy_rgmii conduit end
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set_interface_property gmii_to_rgmii_adapter_1_phy_rgmii EXPORT_OF gmii_to_rgmii_adapter_1.phy_rgmii
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add_interface hps_emac_interface_splitter_1_mdio conduit end
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set_interface_property hps_emac_interface_splitter_1_mdio EXPORT_OF hps_emac_interface_splitter_1.mdio
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add_interface hps_emac_interface_splitter_1_ptp conduit end
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set_interface_property hps_emac_interface_splitter_1_ptp EXPORT_OF hps_emac_interface_splitter_1.ptp
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add_connection hps_emac_interface_splitter_0.emac sys_hps.emac1
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set_connection_parameter_value hps_emac_interface_splitter_0.emac/sys_hps.emac1 endPort {}
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set_connection_parameter_value hps_emac_interface_splitter_0.emac/sys_hps.emac1 endPortLSB {0}
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set_connection_parameter_value hps_emac_interface_splitter_0.emac/sys_hps.emac1 startPort {}
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set_connection_parameter_value hps_emac_interface_splitter_0.emac/sys_hps.emac1 startPortLSB {0}
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set_connection_parameter_value hps_emac_interface_splitter_0.emac/sys_hps.emac1 width {0}
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add_connection hps_emac_interface_splitter_0.emac_rx_clk_in sys_hps.emac1_rx_clk_in
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add_connection hps_emac_interface_splitter_0.emac_tx_clk_in sys_hps.emac1_tx_clk_in
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add_connection iopll_0.outclk0 gmii_to_rgmii_adapter_0.pll_2_5m_clock
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add_connection iopll_0.outclk1 gmii_to_rgmii_adapter_0.pll_25m_clock
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add_connection sys_clk.clk gmii_to_rgmii_adapter_0.peri_clock
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add_connection sys_clk.clk_reset gmii_to_rgmii_adapter_0.peri_reset
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add_connection sys_clk.clk iopll_0.refclk
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add_connection sys_clk.clk_reset iopll_0.reset
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add_connection sys_clk.clk sys_hps.emac_ptp_ref_clock
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add_connection sys_hps.emac1_gtx_clk hps_emac_interface_splitter_0.emac_gtx_clk
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add_connection sys_hps.emac1_rx_reset hps_emac_interface_splitter_0.emac_rx_reset
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add_connection sys_hps.emac1_tx_reset hps_emac_interface_splitter_0.emac_tx_reset
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add_connection hps_emac_interface_splitter_1.emac sys_hps.emac2
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set_connection_parameter_value hps_emac_interface_splitter_1.emac/sys_hps.emac2 endPort {}
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set_connection_parameter_value hps_emac_interface_splitter_1.emac/sys_hps.emac2 endPortLSB {0}
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set_connection_parameter_value hps_emac_interface_splitter_1.emac/sys_hps.emac2 startPort {}
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set_connection_parameter_value hps_emac_interface_splitter_1.emac/sys_hps.emac2 startPortLSB {0}
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set_connection_parameter_value hps_emac_interface_splitter_1.emac/sys_hps.emac2 width {0}
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add_connection hps_emac_interface_splitter_1.emac_rx_clk_in sys_hps.emac2_rx_clk_in
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add_connection hps_emac_interface_splitter_1.emac_tx_clk_in sys_hps.emac2_tx_clk_in
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add_connection iopll_0.outclk0 gmii_to_rgmii_adapter_1.pll_2_5m_clock
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add_connection iopll_0.outclk1 gmii_to_rgmii_adapter_1.pll_25m_clock
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add_connection sys_clk.clk gmii_to_rgmii_adapter_1.peri_clock
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add_connection sys_clk.clk_reset gmii_to_rgmii_adapter_1.peri_reset
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add_connection sys_hps.emac2_gtx_clk hps_emac_interface_splitter_1.emac_gtx_clk
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add_connection sys_hps.emac2_rx_reset hps_emac_interface_splitter_1.emac_rx_reset
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add_connection sys_hps.emac2_tx_reset hps_emac_interface_splitter_1.emac_tx_reset
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