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adxcvr- add parameters for xcvr config

main
Rejeesh Kutty 2017-01-19 12:40:26 -05:00
parent ecd152c90d
commit afcd11da87
2 changed files with 33 additions and 18 deletions
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28
library/xilinx/axi_adxcvr/axi_adxcvr.v
View File

@ -38,7 +38,19 @@
`timescale 1ns/1ps
module axi_adxcvr (
module axi_adxcvr #(
// parameters
parameter integer ID = 0,
parameter integer NUM_OF_LANES = 8,
parameter integer GTH_OR_GTX_N = 0,
parameter integer TX_OR_RX_N = 0,
parameter integer QPLL_ENABLE = 1,
parameter LPM_OR_DFE_N = 1,
parameter [ 2:0] RATE = 3'd0,
parameter [ 1:0] SYS_CLK_SEL = 2'd3,
parameter [ 2:0] OUT_CLK_SEL = 3'd4) (
output [ 7:0] up_cm_sel_0,
output up_cm_enb_0,
@ -501,14 +513,6 @@ module axi_adxcvr (
input [ 1:0] m_axi_rresp,
output m_axi_rready);
// parameters
parameter integer ID = 0;
parameter integer NUM_OF_LANES = 8;
parameter integer GTH_OR_GTX_N = 0;
parameter integer TX_OR_RX_N = 0;
parameter integer QPLL_ENABLE = 1;
// internal signals
wire [ 7:0] up_cm_sel;
@ -1788,7 +1792,11 @@ module axi_adxcvr (
axi_adxcvr_up #(
.ID (ID),
.TX_OR_RX_N (TX_OR_RX_N),
.QPLL_ENABLE (QPLL_ENABLE))
.QPLL_ENABLE (QPLL_ENABLE),
.LPM_OR_DFE_N (LPM_OR_DFE_N),
.RATE (RATE),
.SYS_CLK_SEL (SYS_CLK_SEL),
.OUT_CLK_SEL (OUT_CLK_SEL))
i_up (
.up_cm_sel (up_cm_sel),
.up_cm_enb (up_cm_enb),

23
library/xilinx/axi_adxcvr/axi_adxcvr_up.v
View File

@ -37,7 +37,17 @@
`timescale 1ns/100ps
module axi_adxcvr_up (
module axi_adxcvr_up #(
// parameters
parameter integer ID = 0,
parameter integer TX_OR_RX_N = 0,
parameter integer QPLL_ENABLE = 1,
parameter LPM_OR_DFE_N = 1,
parameter [ 2:0] RATE = 3'd0,
parameter [ 1:0] SYS_CLK_SEL = 2'd3,
parameter [ 2:0] OUT_CLK_SEL = 3'd4) (
// common
@ -104,9 +114,6 @@ module axi_adxcvr_up (
// parameters
localparam [31:0] VERSION = 32'h00100161;
parameter integer ID = 0;
parameter integer TX_OR_RX_N = 0;
parameter integer QPLL_ENABLE = 1;
// internal registers
@ -221,10 +228,10 @@ module axi_adxcvr_up (
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_lpm_dfe_n <= 'd0;
up_rate <= 'd0;
up_sys_clk_sel <= 'd0;
up_out_clk_sel <= 'd0;
up_lpm_dfe_n <= LPM_OR_DFE_N;
up_rate <= RATE;
up_sys_clk_sel <= SYS_CLK_SEL;
up_out_clk_sel <= OUT_CLK_SEL;
end else begin
if ((up_wreq == 1'b1) && (up_waddr == 10'h008)) begin
up_lpm_dfe_n <= up_wdata[12];