From afa3f11206f14f06689baef00da56ffa752b4496 Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Mon, 24 Aug 2020 11:34:48 +0100 Subject: [PATCH] axi_adrv9001: Add TDD support --- library/axi_adrv9001/axi_adrv9001.v | 29 +++ library/axi_adrv9001/axi_adrv9001_core.v | 121 ++++++++++- library/axi_adrv9001/axi_adrv9001_hw.tcl | 15 ++ library/axi_adrv9001/axi_adrv9001_ip.tcl | 4 + library/axi_adrv9001/axi_adrv9001_tdd.v | 258 +++++++++++++++++++++++ library/axi_adrv9001/axi_adrv9001_tx.v | 4 +- 6 files changed, 421 insertions(+), 10 deletions(-) create mode 100644 library/axi_adrv9001/axi_adrv9001_tdd.v diff --git a/library/axi_adrv9001/axi_adrv9001.v b/library/axi_adrv9001/axi_adrv9001.v index 2b8de2538..5e0cba5b8 100644 --- a/library/axi_adrv9001/axi_adrv9001.v +++ b/library/axi_adrv9001/axi_adrv9001.v @@ -38,6 +38,7 @@ module axi_adrv9001 #( parameter ID = 0, parameter CMOS_LVDS_N = 0, + parameter TDD_DISABLE = 0, parameter IO_DELAY_GROUP = "dev_if_delay_group", parameter FPGA_TECHNOLOGY = 0, parameter FPGA_FAMILY = 0, @@ -90,6 +91,11 @@ module axi_adrv9001 #( output tx2_strobe_out_n_NC, output tx2_strobe_out_p_strobe_out, + output rx1_enable, + output rx2_enable, + output tx1_enable, + output tx2_enable, + input delay_clk, // user interface @@ -147,6 +153,14 @@ module axi_adrv9001 #( input [15:0] dac_2_data_q0, input dac_2_dunf, + // TDD interface + input tdd_sync, + + input gpio_rx1_enable_in, + input gpio_rx2_enable_in, + input gpio_tx1_enable_in, + input gpio_tx2_enable_in, + // axi interface input s_axi_aclk, input s_axi_aresetn, @@ -360,6 +374,7 @@ module axi_adrv9001 #( .NUM_LANES (NUM_LANES), .CMOS_LVDS_N (CMOS_LVDS_N), .DRP_WIDTH (DRP_WIDTH), + .TDD_DISABLE (TDD_DISABLE), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .FPGA_FAMILY (FPGA_FAMILY), .SPEED_GRADE (SPEED_GRADE), @@ -456,6 +471,15 @@ module axi_adrv9001 #( .delay_rx2_rst (delay_rx2_rst), .delay_rx2_locked (delay_rx2_locked), + // TDD interface + .tdd_sync (tdd_sync), + .tdd_rx1_rf_en (tdd_rx1_rf_en), + .tdd_tx1_rf_en (tdd_tx1_rf_en), + .tdd_if1_mode (tdd_if1_mode), + .tdd_rx2_rf_en (tdd_rx2_rf_en), + .tdd_tx2_rf_en (tdd_tx2_rf_en), + .tdd_if2_mode (tdd_if2_mode), + .up_rstn (up_rstn), .up_clk (up_clk), .up_wreq (up_wreq_s), @@ -482,6 +506,11 @@ module axi_adrv9001 #( assign dac_2_valid_i0 = dac_2_valid; assign dac_2_valid_q0 = dac_2_valid; + assign rx1_enable = tdd_if1_mode ? tdd_rx1_rf_en : gpio_rx1_enable_in; + assign rx2_enable = tdd_if2_mode ? tdd_rx2_rf_en : gpio_rx2_enable_in; + assign tx1_enable = tdd_if1_mode ? tdd_tx1_rf_en : gpio_tx1_enable_in; + assign tx2_enable = tdd_if2_mode ? tdd_tx2_rf_en : gpio_tx2_enable_in; + // up bus interface up_axi #( .AXI_ADDRESS_WIDTH(15) diff --git a/library/axi_adrv9001/axi_adrv9001_core.v b/library/axi_adrv9001/axi_adrv9001_core.v index 67c4deb18..8f5d5615c 100644 --- a/library/axi_adrv9001/axi_adrv9001_core.v +++ b/library/axi_adrv9001/axi_adrv9001_core.v @@ -40,6 +40,7 @@ module axi_ad9001_core #( parameter CMOS_LVDS_N = 0, parameter NUM_LANES = 3, parameter DRP_WIDTH = 5, + parameter TDD_DISABLE = 0, parameter FPGA_TECHNOLOGY = 0, parameter FPGA_FAMILY = 0, parameter SPEED_GRADE = 0, @@ -140,6 +141,16 @@ module axi_ad9001_core #( output [DRP_WIDTH*NUM_LANES-1:0] up_rx2_dwdata, input [DRP_WIDTH*NUM_LANES-1:0] up_rx2_drdata, + // TDD interface + input tdd_sync, + + output tdd_rx1_rf_en, + output tdd_tx1_rf_en, + output tdd_if1_mode, + output tdd_rx2_rf_en, + output tdd_tx2_rf_en, + output tdd_if2_mode, + // processor interface input up_rstn, @@ -154,9 +165,9 @@ module axi_ad9001_core #( output reg up_rack ); - wire up_wack_s[0:5]; - wire [31:0] up_rdata_s[0:5]; - wire up_rack_s[0:5]; + wire [7:0] up_wack_s; + wire [31:0] up_rdata_s[0:7]; + wire [7:0] up_rack_s; wire tx1_data_valid_A; wire [15:0] tx1_data_i_A; @@ -235,9 +246,16 @@ module axi_ad9001_core #( up_rack <= 'd0; up_wack <= 'd0; end else begin - up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | up_rdata_s[3] | up_rdata_s[4] | up_rdata_s[5]; - up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2] | up_rack_s[3] | up_rack_s[4] | up_rack_s[5]; - up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2] | up_wack_s[3] | up_wack_s[4] | up_wack_s[5]; + up_rdata <= up_rdata_s[0] | + up_rdata_s[1] | + up_rdata_s[2] | + up_rdata_s[3] | + up_rdata_s[4] | + up_rdata_s[5] | + up_rdata_s[6] | + up_rdata_s[7]; + up_rack <= |up_rack_s; + up_wack <= |up_wack_s; end end @@ -257,11 +275,11 @@ module axi_ad9001_core #( i_rx1 ( .adc_rst (rx1_rst), .adc_clk (rx1_clk), - .adc_valid_A (rx1_data_valid), + .adc_valid_A (rx1_data_valid & tdd_rx1_valid), .adc_data_i_A (rx1_data_i), .adc_data_q_A (rx1_data_q), - .adc_valid_B (rx2_data_valid), + .adc_valid_B (rx2_data_valid & tdd_rx1_valid), .adc_data_i_B (rx2_data_i), .adc_data_q_B (rx2_data_q), @@ -316,7 +334,7 @@ module axi_ad9001_core #( i_rx2 ( .adc_rst (rx2_rst_loc), .adc_clk (rx2_clk), - .adc_valid_A (rx2_data_valid), + .adc_valid_A (rx2_data_valid & tdd_rx2_valid), .adc_data_i_A (rx2_data_i), .adc_data_q_A (rx2_data_q), @@ -380,6 +398,7 @@ module axi_ad9001_core #( .dac_single_lane (tx1_single_lane), .dac_sdr_ddr_n (tx1_sdr_ddr_n), .dac_r1_mode (tx1_r1_mode), + .tdd_tx_valid (tdd_tx1_valid), .dac_sync_in (1'b0), .dac_sync_out (), .dac_enable_i0 (dac_1_enable_i0), @@ -441,6 +460,7 @@ module axi_ad9001_core #( .dac_enable_q1 (), .dac_data_q1 (16'b0), .dac_dunf (dac_2_dunf), + .tdd_tx_valid (tdd_tx2_valid), .up_rstn (up_rstn), .up_clk (up_clk), .up_wreq (up_wreq), @@ -497,5 +517,88 @@ module axi_ad9001_core #( .up_rdata (up_rdata_s[5]), .up_rack (up_rack_s[5])); + generate + if (TDD_DISABLE == 0) begin + + wire tdd_rx2_rf_en_loc; + wire tdd_tx2_rf_en_loc; + wire tdd_if2_mode_loc; + + axi_adrv9001_tdd #( + .BASE_ADDRESS (6'h12) + ) i_tdd_1 ( + .clk (rx1_clk), + .rst (rx1_rst), + .tdd_rx_vco_en (), + .tdd_tx_vco_en (), + .tdd_rx_rf_en (tdd_rx1_rf_en), + .tdd_tx_rf_en (tdd_tx1_rf_en), + .tdd_enabled (tdd_if1_mode), + .tdd_status (8'h0), + .tdd_sync (tdd_sync), + .tdd_sync_cntr (), + .tdd_tx_valid (tdd_tx1_valid), + .tdd_rx_valid (tdd_rx1_valid), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[6]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[6]), + .up_rack (up_rack_s[6])); + + axi_adrv9001_tdd #( + .BASE_ADDRESS (6'h13) + ) i_tdd_2 ( + .clk (rx2_clk), + .rst (rx2_rst), + .tdd_rx_vco_en (), + .tdd_tx_vco_en (), + .tdd_rx_rf_en (tdd_rx2_rf_en_loc), + .tdd_tx_rf_en (tdd_tx2_rf_en_loc), + .tdd_enabled (tdd_if2_mode_loc), + .tdd_status (8'h0), + .tdd_sync (tdd_sync), + .tdd_sync_cntr (), + .tdd_tx_valid (tdd_tx2_valid), + .tdd_rx_valid (tdd_rx2_valid), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[7]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[7]), + .up_rack (up_rack_s[7])); + + assign tdd_rx2_rf_en = tx1_r1_mode&rx1_r1_mode ? tdd_rx2_rf_en_loc : tdd_rx1_rf_en; + assign tdd_tx2_rf_en = tx1_r1_mode&rx1_r1_mode ? tdd_tx2_rf_en_loc : tdd_tx1_rf_en; + assign tdd_if2_mode = tx1_r1_mode&rx1_r1_mode ? tdd_if2_mode_loc : tdd_if1_mode; + + end else begin + assign up_wack_s[6] = 1'b0; + assign up_rack_s[6] = 1'b0; + assign up_rdata_s[6] = 32'h0; + assign up_wack_s[7] = 1'b0; + assign up_rack_s[7] = 1'b0; + assign up_rdata_s[7] = 32'h0; + assign tdd_rx1_rf_en = 1'b1; + assign tdd_tx1_rf_en = 1'b1; + assign tdd_if1_mode = 1'b0; + assign tdd_tx1_valid = 1'b1; + assign tdd_rx1_valid = 1'b1; + assign tdd_rx2_rf_en = 1'b1; + assign tdd_tx2_rf_en = 1'b1; + assign tdd_if2_mode = 1'b0; + assign tdd_tx2_valid = 1'b1; + assign tdd_rx2_valid = 1'b1; + end + endgenerate + endmodule diff --git a/library/axi_adrv9001/axi_adrv9001_hw.tcl b/library/axi_adrv9001/axi_adrv9001_hw.tcl index 3df858a03..66b7f80d1 100644 --- a/library/axi_adrv9001/axi_adrv9001_hw.tcl +++ b/library/axi_adrv9001/axi_adrv9001_hw.tcl @@ -17,6 +17,9 @@ ad_ip_files axi_adrv9001 [list\ "$ad_hdl_dir/library/common/ad_dds.v" \ "$ad_hdl_dir/library/common/ad_datafmt.v" \ "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/common/up_tdd_cntrl.v" \ + "$ad_hdl_dir/library/common/ad_tdd_control.v" \ + "$ad_hdl_dir/library/common/ad_addsub.v" \ "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ "$ad_hdl_dir/library/common/up_xfer_status.v" \ "$ad_hdl_dir/library/common/up_clock_mon.v" \ @@ -46,6 +49,7 @@ ad_ip_files axi_adrv9001 [list\ "axi_adrv9001_tx_channel.v" \ "axi_adrv9001_core.v" \ "axi_adrv9001_constr.sdc" \ + "axi_adrv9001_tdd.v" \ "axi_adrv9001.v" ] # parameters @@ -163,6 +167,13 @@ add_interface_port dac_2_ch_1 dac_2_data_q0 data Input 16 ad_interface signal dac_2_dunf input 1 unf +add_interface tdd_if conduit end +add_interface_port tdd_if gpio_rx1_enable_in rx1_enable_in Input 1 +add_interface_port tdd_if gpio_rx2_enable_in rx2_enable_in Input 1 +add_interface_port tdd_if gpio_tx1_enable_in tx1_enable_in Input 1 +add_interface_port tdd_if gpio_tx2_enable_in tx2_enable_in Input 1 +add_interface_port tdd_if tdd_sync tdd_sync_in Input 1 + # updates proc axi_adrv9001_elab {} { @@ -197,6 +208,7 @@ proc axi_adrv9001_elab {} { add_interface_port device_if rx1_qdata_in_n_qdata2 rx1_qdata_in_n_qdata2 Input 1 add_interface_port device_if rx1_qdata_in_p_qdata3 rx1_qdata_in_p_qdata3 Input 1 add_interface_port device_if rx1_strobe_in_p_strobe_in rx1_strobe_in_p_strobe_in Input 1 + add_interface_port device_if rx1_enable rx1_enable Output 1 add_interface_port device_if rx2_dclk_in_p_dclk_in rx2_dclk_in_p_dclk_in Input 1 add_interface_port device_if rx2_idata_in_n_idata0 rx2_idata_in_n_idata0 Input 1 @@ -204,6 +216,7 @@ proc axi_adrv9001_elab {} { add_interface_port device_if rx2_qdata_in_n_qdata2 rx2_qdata_in_n_qdata2 Input 1 add_interface_port device_if rx2_qdata_in_p_qdata3 rx2_qdata_in_p_qdata3 Input 1 add_interface_port device_if rx2_strobe_in_p_strobe_in rx2_strobe_in_p_strobe_in Input 1 + add_interface_port device_if rx2_enable rx2_enable Output 1 add_interface_port device_if tx1_dclk_out_p_dclk_out tx1_dclk_out_p_dclk_out Output 1 add_interface_port device_if tx1_dclk_in_p_dclk_in tx1_dclk_in_p_dclk_in Input 1 @@ -212,6 +225,7 @@ proc axi_adrv9001_elab {} { add_interface_port device_if tx1_qdata_out_n_qdata2 tx1_qdata_out_n_qdata2 Output 1 add_interface_port device_if tx1_qdata_out_p_qdata3 tx1_qdata_out_p_qdata3 Output 1 add_interface_port device_if tx1_strobe_out_p_strobe_out tx1_strobe_out_p_strobe_out Output 1 + add_interface_port device_if tx1_enable tx1_enable Output 1 add_interface_port device_if tx2_dclk_out_p_dclk_out tx2_dclk_out_p_dclk_out Output 1 add_interface_port device_if tx2_dclk_in_p_dclk_in tx2_dclk_in_p_dclk_in Input 1 @@ -220,6 +234,7 @@ proc axi_adrv9001_elab {} { add_interface_port device_if tx2_qdata_out_n_qdata2 tx2_qdata_out_n_qdata2 Output 1 add_interface_port device_if tx2_qdata_out_p_qdata3 tx2_qdata_out_p_qdata3 Output 1 add_interface_port device_if tx2_strobe_out_p_strobe_out tx2_strobe_out_p_strobe_out Output 1 + add_interface_port device_if tx2_enable tx2_enable Output 1 } } diff --git a/library/axi_adrv9001/axi_adrv9001_ip.tcl b/library/axi_adrv9001/axi_adrv9001_ip.tcl index f16e80c12..fd8cc5c07 100644 --- a/library/axi_adrv9001/axi_adrv9001_ip.tcl +++ b/library/axi_adrv9001/axi_adrv9001_ip.tcl @@ -17,6 +17,9 @@ adi_ip_files axi_adrv9001 [list \ "$ad_hdl_dir/library/common/ad_dds_2.v" \ "$ad_hdl_dir/library/common/ad_dds.v" \ "$ad_hdl_dir/library/common/ad_datafmt.v" \ + "$ad_hdl_dir/library/common/up_tdd_cntrl.v" \ + "$ad_hdl_dir/library/common/ad_tdd_control.v" \ + "$ad_hdl_dir/library/common/ad_addsub.v" \ "$ad_hdl_dir/library/common/ad_rst.v" \ "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ "$ad_hdl_dir/library/common/up_xfer_status.v" \ @@ -47,6 +50,7 @@ adi_ip_files axi_adrv9001 [list \ "axi_adrv9001_tx_channel.v" \ "axi_adrv9001_core.v" \ "axi_adrv9001_constr.xdc" \ + "axi_adrv9001_tdd.v" \ "axi_adrv9001.v" ] adi_ip_properties axi_adrv9001 diff --git a/library/axi_adrv9001/axi_adrv9001_tdd.v b/library/axi_adrv9001/axi_adrv9001_tdd.v new file mode 100644 index 000000000..fe5f5d905 --- /dev/null +++ b/library/axi_adrv9001/axi_adrv9001_tdd.v @@ -0,0 +1,258 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/1ps + +module axi_adrv9001_tdd #( + parameter ID = 0, + parameter BASE_ADDRESS = 6'h20 +) ( + + // clock + + input clk, + input rst, + + // control signals from the tdd control + + output tdd_rx_vco_en, + output tdd_tx_vco_en, + output tdd_rx_rf_en, + output tdd_tx_rf_en, + + // status signal + + output tdd_enabled, + input [ 7:0] tdd_status, + + // sync signal + + input tdd_sync, + output reg tdd_sync_cntr, + + // tx/rx data flow control + + output reg tdd_tx_valid, + output reg tdd_rx_valid, + + // bus interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack); + + // internal signals + + wire tdd_enable_s; + wire tdd_secondary_s; + wire [ 7:0] tdd_burst_count_s; + wire tdd_rx_only_s; + wire tdd_tx_only_s; + wire tdd_gated_rx_dmapath_s; + wire tdd_gated_tx_dmapath_s; + wire [23:0] tdd_counter_init_s; + wire [23:0] tdd_frame_length_s; + wire tdd_terminal_type_s; + wire tdd_sync_enable_s; + wire [23:0] tdd_vco_rx_on_1_s; + wire [23:0] tdd_vco_rx_off_1_s; + wire [23:0] tdd_vco_tx_on_1_s; + wire [23:0] tdd_vco_tx_off_1_s; + wire [23:0] tdd_rx_on_1_s; + wire [23:0] tdd_rx_off_1_s; + wire [23:0] tdd_rx_dp_on_1_s; + wire [23:0] tdd_rx_dp_off_1_s; + wire [23:0] tdd_tx_on_1_s; + wire [23:0] tdd_tx_off_1_s; + wire [23:0] tdd_tx_dp_on_1_s; + wire [23:0] tdd_tx_dp_off_1_s; + wire [23:0] tdd_vco_rx_on_2_s; + wire [23:0] tdd_vco_rx_off_2_s; + wire [23:0] tdd_vco_tx_on_2_s; + wire [23:0] tdd_vco_tx_off_2_s; + wire [23:0] tdd_rx_on_2_s; + wire [23:0] tdd_rx_off_2_s; + wire [23:0] tdd_rx_dp_on_2_s; + wire [23:0] tdd_rx_dp_off_2_s; + wire [23:0] tdd_tx_on_2_s; + wire [23:0] tdd_tx_off_2_s; + wire [23:0] tdd_tx_dp_on_2_s; + wire [23:0] tdd_tx_dp_off_2_s; + + wire [23:0] tdd_counter_status; + + wire tdd_rx_dp_en_s; + wire tdd_tx_dp_en_s; + + assign tdd_enabled = tdd_enable_s; + + // syncronization control signal + + always @(posedge clk) begin + if (tdd_enable_s == 1'b1) begin + tdd_sync_cntr <= ~tdd_terminal_type_s; + end else begin + tdd_sync_cntr <= 1'b0; + end + end + + // tx/rx data flow control + + always @(posedge clk) begin + if((tdd_enable_s == 1) && (tdd_gated_tx_dmapath_s == 1)) begin + tdd_tx_valid <= tdd_tx_dp_en_s; + end else begin + tdd_tx_valid <= 1'b1; + end + end + + always @(posedge clk) begin + if((tdd_enable_s == 1) && (tdd_gated_tx_dmapath_s == 1)) begin + tdd_rx_valid <= tdd_rx_dp_en_s; + end else begin + tdd_rx_valid <= 1'b1; + end + end + + // instantiations + + up_tdd_cntrl #( + .BASE_ADDRESS (BASE_ADDRESS) + ) i_up_tdd_cntrl( + .clk(clk), + .rst(rst), + .tdd_enable(tdd_enable_s), + .tdd_secondary(tdd_secondary_s), + .tdd_burst_count(tdd_burst_count_s), + .tdd_tx_only(tdd_tx_only_s), + .tdd_rx_only(tdd_rx_only_s), + .tdd_gated_rx_dmapath(tdd_gated_rx_dmapath_s), + .tdd_gated_tx_dmapath(tdd_gated_tx_dmapath_s), + .tdd_counter_init(tdd_counter_init_s), + .tdd_frame_length(tdd_frame_length_s), + .tdd_terminal_type(tdd_terminal_type_s), + .tdd_vco_rx_on_1(tdd_vco_rx_on_1_s), + .tdd_vco_rx_off_1(tdd_vco_rx_off_1_s), + .tdd_vco_tx_on_1(tdd_vco_tx_on_1_s), + .tdd_vco_tx_off_1(tdd_vco_tx_off_1_s), + .tdd_rx_on_1(tdd_rx_on_1_s), + .tdd_rx_off_1(tdd_rx_off_1_s), + .tdd_rx_dp_on_1(tdd_rx_dp_on_1_s), + .tdd_rx_dp_off_1(tdd_rx_dp_off_1_s), + .tdd_tx_on_1(tdd_tx_on_1_s), + .tdd_tx_off_1(tdd_tx_off_1_s), + .tdd_tx_dp_on_1(tdd_tx_dp_on_1_s), + .tdd_tx_dp_off_1(tdd_tx_dp_off_1_s), + .tdd_vco_rx_on_2(tdd_vco_rx_on_2_s), + .tdd_vco_rx_off_2(tdd_vco_rx_off_2_s), + .tdd_vco_tx_on_2(tdd_vco_tx_on_2_s), + .tdd_vco_tx_off_2(tdd_vco_tx_off_2_s), + .tdd_rx_on_2(tdd_rx_on_2_s), + .tdd_rx_off_2(tdd_rx_off_2_s), + .tdd_rx_dp_on_2(tdd_rx_dp_on_2_s), + .tdd_rx_dp_off_2(tdd_rx_dp_off_2_s), + .tdd_tx_on_2(tdd_tx_on_2_s), + .tdd_tx_off_2(tdd_tx_off_2_s), + .tdd_tx_dp_on_2(tdd_tx_dp_on_2_s), + .tdd_tx_dp_off_2(tdd_tx_dp_off_2_s), + .tdd_status(tdd_status), + .up_rstn(up_rstn), + .up_clk(up_clk), + .up_wreq(up_wreq), + .up_waddr(up_waddr), + .up_wdata(up_wdata), + .up_wack(up_wack), + .up_rreq(up_rreq), + .up_raddr(up_raddr), + .up_rdata(up_rdata), + .up_rack(up_rack)); + + // the TX_DATA_PATH_DELAY and CONTROL_PATH_DELAY are specificly defined + // for the axi_adrv9001 core + + ad_tdd_control #( + .TX_DATA_PATH_DELAY(), + .CONTROL_PATH_DELAY()) + i_tdd_control( + .clk(clk), + .rst(rst), + .tdd_enable(tdd_enable_s), + .tdd_secondary(tdd_secondary_s), + .tdd_counter_init(tdd_counter_init_s), + .tdd_frame_length(tdd_frame_length_s), + .tdd_burst_count(tdd_burst_count_s), + .tdd_rx_only(tdd_rx_only_s), + .tdd_tx_only(tdd_tx_only_s), + .tdd_sync (tdd_sync), + .tdd_vco_rx_on_1(tdd_vco_rx_on_1_s), + .tdd_vco_rx_off_1(tdd_vco_rx_off_1_s), + .tdd_vco_tx_on_1(tdd_vco_tx_on_1_s), + .tdd_vco_tx_off_1(tdd_vco_tx_off_1_s), + .tdd_rx_on_1(tdd_rx_on_1_s), + .tdd_rx_off_1(tdd_rx_off_1_s), + .tdd_rx_dp_on_1(tdd_rx_dp_on_1_s), + .tdd_rx_dp_off_1(tdd_rx_dp_off_1_s), + .tdd_tx_on_1(tdd_tx_on_1_s), + .tdd_tx_off_1(tdd_tx_off_1_s), + .tdd_tx_dp_on_1(tdd_tx_dp_on_1_s), + .tdd_tx_dp_off_1(tdd_tx_dp_off_1_s), + .tdd_vco_rx_on_2(tdd_vco_rx_on_2_s), + .tdd_vco_rx_off_2(tdd_vco_rx_off_2_s), + .tdd_vco_tx_on_2(tdd_vco_tx_on_2_s), + .tdd_vco_tx_off_2(tdd_vco_tx_off_2_s), + .tdd_rx_on_2(tdd_rx_on_2_s), + .tdd_rx_off_2(tdd_rx_off_2_s), + .tdd_rx_dp_on_2(tdd_rx_dp_on_2_s), + .tdd_rx_dp_off_2(tdd_rx_dp_off_2_s), + .tdd_tx_on_2(tdd_tx_on_2_s), + .tdd_tx_off_2(tdd_tx_off_2_s), + .tdd_tx_dp_on_2(tdd_tx_dp_on_2_s), + .tdd_tx_dp_off_2(tdd_tx_dp_off_2_s), + .tdd_rx_dp_en(tdd_rx_dp_en_s), + .tdd_tx_dp_en(tdd_tx_dp_en_s), + .tdd_rx_vco_en(tdd_rx_vco_en), + .tdd_tx_vco_en(tdd_tx_vco_en), + .tdd_rx_rf_en(tdd_rx_rf_en), + .tdd_tx_rf_en(tdd_tx_rf_en), + .tdd_counter_status(tdd_counter_status)); + +endmodule diff --git a/library/axi_adrv9001/axi_adrv9001_tx.v b/library/axi_adrv9001/axi_adrv9001_tx.v index c23f65e16..989b1016b 100644 --- a/library/axi_adrv9001/axi_adrv9001_tx.v +++ b/library/axi_adrv9001/axi_adrv9001_tx.v @@ -67,6 +67,8 @@ module axi_adrv9001_tx #( output dac_sdr_ddr_n, output dac_r1_mode, + input tdd_tx_valid, + // master/slave input dac_sync_in, output dac_sync_out, @@ -157,7 +159,7 @@ module axi_adrv9001_tx #( if (dac_rst == 1'b1) begin dac_valid_int <= 1'b0; end else begin - dac_valid_int <= (dac_rate_cnt == 16'd0) ? 1'b1 : 1'b0; + dac_valid_int <= (dac_rate_cnt == 16'd0) ? tdd_tx_valid : 1'b0; end end