axi_dmac: Comment out unused src_response interface
Currently the read side of the src_response interface is not used. This leads to warnings about signals that have a value assigned but are never read. To avoid this just comment out all signals that are related to the src_response interface for now. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>main
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16bd0c3894
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aeabe91144
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@ -245,10 +245,12 @@ wire [DMA_ADDRESS_WIDTH_SRC-1:0] src_req_address;
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wire [BEATS_PER_BURST_WIDTH_SRC-1:0] src_req_last_burst_length;
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wire src_req_sync_transfer_start;
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/* TODO
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wire src_response_valid;
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wire src_response_ready;
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wire src_response_empty;
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wire [1:0] src_response_resp;
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*/
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wire [ID_WIDTH-1:0] src_request_id;
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wire [ID_WIDTH-1:0] src_response_id;
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@ -632,9 +634,11 @@ dmac_src_mm_axi #(
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.req_address(src_req_address),
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.req_last_burst_length(src_req_last_burst_length),
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/* TODO
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.response_valid(src_response_valid),
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.response_ready(src_response_ready),
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.response_resp(src_response_resp),
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*/
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.request_id(src_request_id),
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.response_id(src_response_id),
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@ -685,9 +689,10 @@ wire src_eot = eot_mem[src_response_id];
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assign dbg_src_address_id = 'h00;
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assign dbg_src_data_id = 'h00;
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/* TODO */
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/* TODO
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assign src_response_valid = 1'b0;
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assign src_response_resp = 2'b0;
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*/
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dmac_src_axi_stream #(
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.ID_WIDTH(ID_WIDTH),
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@ -739,9 +744,10 @@ wire src_eot = eot_mem[src_response_id];
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assign dbg_src_address_id = 'h00;
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assign dbg_src_data_id = 'h00;
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/* TODO */
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/* TODO
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assign src_response_valid = 1'b0;
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assign src_response_resp = 2'b0;
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*/
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dmac_src_fifo_inf #(
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.ID_WIDTH(ID_WIDTH),
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@ -1048,9 +1054,10 @@ util_axis_fifo #(
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.m_axis_valid(response_src_valid),
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.m_axis_ready(response_src_ready),
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.m_axis_data(response_src_resp)
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);*/
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);
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assign src_response_empty = 1'b1;
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assign src_response_ready = 1'b1;
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*/
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dmac_request_generator #(
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.ID_WIDTH(ID_WIDTH),
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@ -1108,7 +1115,7 @@ sync_bits #(
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) i_sync_status_src (
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.out_clk(req_aclk),
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.out_resetn(req_aresetn),
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.in({src_enabled | ~src_response_empty, src_sync_id_ret, src_fifo_empty}),
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.in({src_enabled /* | ~src_response_empty*/, src_sync_id_ret, src_fifo_empty}),
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.out({enabled_src, sync_id_ret_src, fifo_empty})
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);
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@ -56,9 +56,11 @@ module dmac_src_mm_axi #(
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input sync_id,
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output sync_id_ret,
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/*
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output response_valid,
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input response_ready,
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output [1:0] response_resp,
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*/
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input [ID_WIDTH-1:0] request_id,
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output [ID_WIDTH-1:0] response_id,
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@ -89,8 +91,6 @@ module dmac_src_mm_axi #(
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input [ 1:0] m_axi_rresp
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);
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`include "resp.h"
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wire address_enabled;
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wire address_req_valid;
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@ -101,9 +101,6 @@ wire data_req_ready;
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assign sync_id_ret = sync_id;
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assign response_id = data_id;
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assign response_valid = 1'b0;
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assign response_resp = RESP_OKAY;
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splitter #(
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.NUM_M(2)
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) i_req_splitter (
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@ -188,6 +185,12 @@ dmac_data_mover # (
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.m_axi_last()
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);
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/* TODO
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`include "resp.h"
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assign response_valid = 1'b0;
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assign response_resp = RESP_OKAY;
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reg [1:0] rresp;
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always @(posedge m_axi_aclk)
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@ -197,5 +200,6 @@ begin
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rresp <= m_axi_rresp;
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end
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end
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*/
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endmodule
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