From aeabe911443e6bb9fcaa4a1222abfec3636cbb51 Mon Sep 17 00:00:00 2001
From: Lars-Peter Clausen <lars@metafoo.de>
Date: Mon, 31 Jul 2017 09:06:54 +0200
Subject: [PATCH] axi_dmac: Comment out unused src_response interface

Currently the read side of the src_response interface is not used. This
leads to warnings about signals that have a value assigned but are never
read.

To avoid this just comment out all signals that are related to the
src_response interface for now.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
---
 library/axi_dmac/request_arb.v | 15 +++++++++++----
 library/axi_dmac/src_axi_mm.v  | 14 +++++++++-----
 2 files changed, 20 insertions(+), 9 deletions(-)

diff --git a/library/axi_dmac/request_arb.v b/library/axi_dmac/request_arb.v
index c8cba6e39..bcd650bc3 100644
--- a/library/axi_dmac/request_arb.v
+++ b/library/axi_dmac/request_arb.v
@@ -245,10 +245,12 @@ wire [DMA_ADDRESS_WIDTH_SRC-1:0] src_req_address;
 wire [BEATS_PER_BURST_WIDTH_SRC-1:0] src_req_last_burst_length;
 wire src_req_sync_transfer_start;
 
+/* TODO
 wire src_response_valid;
 wire src_response_ready;
 wire src_response_empty;
 wire [1:0] src_response_resp;
+*/
 
 wire [ID_WIDTH-1:0] src_request_id;
 wire [ID_WIDTH-1:0] src_response_id;
@@ -632,9 +634,11 @@ dmac_src_mm_axi #(
   .req_address(src_req_address),
   .req_last_burst_length(src_req_last_burst_length),
 
+/* TODO
   .response_valid(src_response_valid),
   .response_ready(src_response_ready),
   .response_resp(src_response_resp),
+*/
 
   .request_id(src_request_id),
   .response_id(src_response_id),
@@ -685,9 +689,10 @@ wire src_eot = eot_mem[src_response_id];
 assign dbg_src_address_id = 'h00;
 assign dbg_src_data_id = 'h00;
 
-/* TODO */
+/* TODO
 assign src_response_valid = 1'b0;
 assign src_response_resp = 2'b0;
+*/
 
 dmac_src_axi_stream #(
   .ID_WIDTH(ID_WIDTH),
@@ -739,9 +744,10 @@ wire src_eot = eot_mem[src_response_id];
 assign dbg_src_address_id = 'h00;
 assign dbg_src_data_id = 'h00;
 
-/* TODO */
+/* TODO
 assign src_response_valid = 1'b0;
 assign src_response_resp = 2'b0;
+*/
 
 dmac_src_fifo_inf #(
   .ID_WIDTH(ID_WIDTH),
@@ -1048,9 +1054,10 @@ util_axis_fifo #(
   .m_axis_valid(response_src_valid),
   .m_axis_ready(response_src_ready),
   .m_axis_data(response_src_resp)
-);*/
+);
 assign src_response_empty = 1'b1;
 assign src_response_ready = 1'b1;
+*/
 
 dmac_request_generator #(
   .ID_WIDTH(ID_WIDTH),
@@ -1108,7 +1115,7 @@ sync_bits #(
 ) i_sync_status_src (
   .out_clk(req_aclk),
   .out_resetn(req_aresetn),
-  .in({src_enabled | ~src_response_empty, src_sync_id_ret, src_fifo_empty}),
+  .in({src_enabled /* | ~src_response_empty*/, src_sync_id_ret, src_fifo_empty}),
   .out({enabled_src, sync_id_ret_src, fifo_empty})
 );
 
diff --git a/library/axi_dmac/src_axi_mm.v b/library/axi_dmac/src_axi_mm.v
index 5a2ed5205..4370297df 100644
--- a/library/axi_dmac/src_axi_mm.v
+++ b/library/axi_dmac/src_axi_mm.v
@@ -56,9 +56,11 @@ module dmac_src_mm_axi #(
   input                           sync_id,
   output                          sync_id_ret,
 
+/*
   output                          response_valid,
   input                           response_ready,
   output [1:0]                    response_resp,
+*/
 
   input  [ID_WIDTH-1:0]         request_id,
   output [ID_WIDTH-1:0]         response_id,
@@ -89,8 +91,6 @@ module dmac_src_mm_axi #(
   input  [ 1:0]                    m_axi_rresp
 );
 
-`include "resp.h"
-
 wire address_enabled;
 
 wire address_req_valid;
@@ -101,9 +101,6 @@ wire data_req_ready;
 assign sync_id_ret = sync_id;
 assign response_id = data_id;
 
-assign response_valid = 1'b0;
-assign response_resp = RESP_OKAY;
-
 splitter #(
   .NUM_M(2)
 ) i_req_splitter (
@@ -188,6 +185,12 @@ dmac_data_mover # (
   .m_axi_last()
 );
 
+/* TODO
+`include "resp.h"
+
+assign response_valid = 1'b0;
+assign response_resp = RESP_OKAY;
+
 reg [1:0] rresp;
 
 always @(posedge m_axi_aclk)
@@ -197,5 +200,6 @@ begin
       rresp <= m_axi_rresp;
   end
 end
+*/
 
 endmodule