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ad_ip_jesd204_tpl_dac: Fix pattern output correctly when DATA_PATH_WIDTH=1 

Some modes produce only one sample per channel per beat, e.g. when M=2*L.

In this case the pattern output needs to alternate between the two patterns
from beat to beat.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
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Lars-Peter Clausen 2018-08-08 16:12:07 +02:00 committed by Lars-Peter Clausen
parent 5d044b9fd3
commit ae8ce1ccd8
1 changed files with 21 additions and 1 deletions
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22
library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_channel.v
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@ -65,6 +65,26 @@ module ad_ip_jesd204_tpl_dac_channel #(
// internal signals
wire [DATA_PATH_WIDTH*16-1:0] dac_dds_data_s;
wire [DATA_PATH_WIDTH*16-1:0] dac_pat_data_s;
generate
if (DATA_PATH_WIDTH > 1) begin
assign dac_pat_data_s = {DATA_PATH_WIDTH/2{dac_pat_data_1,dac_pat_data_0}};
end else begin
reg dac_pat_data_sel = 1'b0;
always @(posedge clk) begin
if (dac_data_sync == 1'b1) begin
dac_pat_data_sel <= 1'b0;
end else begin
dac_pat_data_sel <= ~dac_pat_data_sel;
end
end
assign dac_pat_data_s = dac_pat_data_sel == 1'b0 ?
dac_pat_data_0 : dac_pat_data_1;
end
endgenerate
// dac data select
@ -77,7 +97,7 @@ module ad_ip_jesd204_tpl_dac_channel #(
4'h4: dac_data <= ~pn7_data;
4'h3: dac_data <= 'h00;
4'h2: dac_data <= dma_data;
4'h1: dac_data <= {DATA_PATH_WIDTH/2{dac_pat_data_1, dac_pat_data_0}};
4'h1: dac_data <= dac_pat_data_s;
default: dac_data <= dac_dds_data_s;
endcase
end