util_axis_fifo: Add option to disable registered output
Add a option to specify whether the FIFO should have a registered output stage or not. This is useful if the user wants to implement that stage itself. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>main
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f6594e276e
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ae4e7a0c37
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@ -54,6 +54,7 @@ module util_axis_fifo (
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parameter C_DATA_WIDTH = 64;
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parameter C_CLKS_ASYNC = 1;
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parameter C_ADDRESS_WIDTH = 4;
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parameter C_S_AXIS_REGISTERED = 1;
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generate if (C_ADDRESS_WIDTH == 0) begin
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@ -168,6 +169,8 @@ always @(posedge s_axis_aclk) begin
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ram[s_axis_waddr] <= s_axis_data;
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end
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if (C_S_AXIS_REGISTERED == 1) begin
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reg [C_DATA_WIDTH-1:0] data;
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reg valid;
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@ -191,6 +194,14 @@ assign _m_axis_ready = ~valid || m_axis_ready;
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assign m_axis_data = data;
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assign m_axis_valid = valid;
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end else begin
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assign _m_axis_ready = m_axis_ready;
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assign m_axis_valid = _m_axis_valid;
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assign m_axis_data = ram[m_axis_raddr];
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end
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end endgenerate
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endmodule
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