diff --git a/projects/common/a10gx/a10gx_system_bd.qsys b/projects/common/a10gx/a10gx_system_bd.qsys
index b3a3a70b5..c49ad0640 100644
--- a/projects/common/a10gx/a10gx_system_bd.qsys
+++ b/projects/common/a10gx/a10gx_system_bd.qsys
@@ -9,14 +9,6 @@
    categories="System" />
  <parameter name="bonusData"><![CDATA[bonusData 
 {
-   element $${FILENAME}
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
    element a10gx_system_bd
    {
       datum _originalDeviceFamily
@@ -103,7 +95,7 @@
       }
       datum sopceditor_expanded
       {
-         value = "1";
+         value = "0";
          type = "boolean";
       }
    }
@@ -620,7 +612,7 @@
  <parameter name="hideFromIPCatalog" value="false" />
  <parameter name="lockedInterfaceDefinition" value="" />
  <parameter name="maxAdditionalLatency" value="2" />
- <parameter name="projectName" value="daq2_a10gx.qpf" />
+ <parameter name="projectName" value="" />
  <parameter name="sopcBorderPoints" value="false" />
  <parameter name="systemHash" value="0" />
  <parameter name="testBenchDutName" value="" />
@@ -721,24 +713,24 @@
    dir="end" />
  <interface name="sys_rst" internal="sys_rst.in_reset" type="reset" dir="end" />
  <interface name="sys_spi" internal="sys_spi.external" type="conduit" dir="end" />
- <module name="mem_clk" kind="altera_clock_bridge" version="15.0" enabled="1">
+ <module name="mem_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
   <parameter name="DERIVED_CLOCK_RATE" value="133333250" />
   <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
   <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
  </module>
- <module name="mem_rst" kind="altera_reset_bridge" version="15.0" enabled="1">
+ <module name="mem_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
   <parameter name="ACTIVE_LOW_RESET" value="0" />
   <parameter name="AUTO_CLK_CLOCK_RATE" value="133333250" />
   <parameter name="NUM_RESET_OUTPUTS" value="1" />
   <parameter name="SYNCHRONOUS_EDGES" value="deassert" />
   <parameter name="USE_RESET_REQUEST" value="0" />
  </module>
- <module name="sys_clk" kind="altera_clock_bridge" version="15.0" enabled="1">
+ <module name="sys_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
   <parameter name="DERIVED_CLOCK_RATE" value="0" />
   <parameter name="EXPLICIT_CLOCK_RATE" value="100000000" />
   <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
  </module>
- <module name="sys_cpu" kind="altera_nios2_gen2" version="15.0" enabled="1">
+ <module name="sys_cpu" kind="altera_nios2_gen2" version="15.1" enabled="1">
   <parameter name="AUTO_CLK_CLOCK_DOMAIN" value="3" />
   <parameter name="AUTO_CLK_RESET_DOMAIN" value="3" />
   <parameter name="AUTO_DEVICE" value="10AX115S3F45I2SGE2" />
@@ -758,7 +750,7 @@
   <parameter name="dataAddrWidth" value="29" />
   <parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
   <parameter name="dataMasterHighPerformanceMapParam" value="" />
-  <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='sys_ddr3_cntrl.ctrl_amm_0' start='0x0' end='0x10000000' /><slave name='sys_cpu_interconnect.s0' start='0x10000000' end='0x10100000' /><slave name='sys_int_mem.s1' start='0x10140000' end='0x10168000' /><slave name='sys_cpu.debug_mem_slave' start='0x10180800' end='0x10181000' /><slave name='sys_ethernet.control_port' start='0x10181000' end='0x10181400' /><slave name='sys_spi.spi_control_port' start='0x10181400' end='0x10181420' /><slave name='sys_timer.s1' start='0x10181420' end='0x10181440' /><slave name='sys_ethernet_dma_rx.descriptor_slave' start='0x10181440' end='0x10181460' /><slave name='sys_ethernet_dma_tx.descriptor_slave' start='0x10181460' end='0x10181480' /><slave name='sys_ethernet_dma_tx.csr' start='0x10181480' end='0x101814A0' /><slave name='sys_ethernet_dma_rx.csr' start='0x101814A0' end='0x101814C0' /><slave name='sys_gpio_in.s1' start='0x101814C0' end='0x101814D0' /><slave name='sys_gpio_bd.s1' start='0x101814D0' end='0x101814E0' /><slave name='sys_ethernet_dma_rx.response' start='0x101814E0' end='0x101814E8' /><slave name='sys_id.control_slave' start='0x101814E8' end='0x101814F0' /><slave name='sys_uart.avalon_jtag_slave' start='0x101814F0' end='0x101814F8' /><slave name='sys_gpio_out.s1' start='0x10181500' end='0x10181510' /><slave name='sys_timer_2nd.s1' start='0x10181520' end='0x10181540' /></address-map>]]></parameter>
+  <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='sys_ddr3_cntrl_arch.ctrl_amm_0' start='0x0' end='0x10000000' type='altera_emif_arch_nf.ctrl_amm_0' /><slave name='sys_cpu_interconnect.s0' start='0x10000000' end='0x10100000' type='altera_avalon_mm_bridge.s0' /><slave name='sys_int_mem.s1' start='0x10140000' end='0x10168000' type='altera_avalon_onchip_memory2.s1' /><slave name='sys_cpu.debug_mem_slave' start='0x10180800' end='0x10181000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sys_ethernet.control_port' start='0x10181000' end='0x10181400' type='altera_eth_tse.control_port' /><slave name='sys_spi.spi_control_port' start='0x10181400' end='0x10181420' type='altera_avalon_spi.spi_control_port' /><slave name='sys_timer.s1' start='0x10181420' end='0x10181440' type='altera_avalon_timer.s1' /><slave name='sys_ethernet_dma_rx.descriptor_slave' start='0x10181440' end='0x10181460' type='altera_msgdma.descriptor_slave' /><slave name='sys_ethernet_dma_tx.descriptor_slave' start='0x10181460' end='0x10181480' type='altera_msgdma.descriptor_slave' /><slave name='sys_ethernet_dma_tx.csr' start='0x10181480' end='0x101814A0' type='altera_msgdma.csr' /><slave name='sys_ethernet_dma_rx.csr' start='0x101814A0' end='0x101814C0' type='altera_msgdma.csr' /><slave name='sys_gpio_in.s1' start='0x101814C0' end='0x101814D0' type='altera_avalon_pio.s1' /><slave name='sys_gpio_bd.s1' start='0x101814D0' end='0x101814E0' type='altera_avalon_pio.s1' /><slave name='sys_ethernet_dma_rx.response' start='0x101814E0' end='0x101814E8' type='altera_msgdma.response' /><slave name='sys_id.control_slave' start='0x101814E8' end='0x101814F0' type='altera_avalon_sysid_qsys.control_slave' /><slave name='sys_uart.avalon_jtag_slave' start='0x101814F0' end='0x101814F8' type='altera_avalon_jtag_uart.avalon_jtag_slave' /><slave name='sys_gpio_out.s1' start='0x10181500' end='0x10181510' type='altera_avalon_pio.s1' /><slave name='sys_timer_2nd.s1' start='0x10181520' end='0x10181540' type='altera_avalon_timer.s1' /></address-map>]]></parameter>
   <parameter name="data_master_high_performance_paddr_base" value="0" />
   <parameter name="data_master_high_performance_paddr_size" value="0" />
   <parameter name="data_master_paddr_base" value="0" />
@@ -780,10 +772,10 @@
   <parameter name="debug_traceType" value="none" />
   <parameter name="debug_triggerArming" value="true" />
   <parameter name="deviceFamilyName" value="Arria 10" />
-  <parameter name="deviceFeaturesSystemInfo">ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 1 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</parameter>
+  <parameter name="deviceFeaturesSystemInfo">ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 1 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</parameter>
   <parameter name="dividerType" value="no_div" />
   <parameter name="exceptionOffset" value="32" />
-  <parameter name="exceptionSlave">sys_ddr3_cntrl.ctrl_amm_0</parameter>
+  <parameter name="exceptionSlave">sys_ddr3_cntrl_arch.ctrl_amm_0</parameter>
   <parameter name="faAddrWidth" value="1" />
   <parameter name="faSlaveMapParam" value="" />
   <parameter name="fa_cache_line" value="2" />
@@ -797,7 +789,7 @@
   <parameter name="icache_tagramBlockType" value="Automatic" />
   <parameter name="impl" value="Fast" />
   <parameter name="instAddrWidth" value="29" />
-  <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='sys_ddr3_cntrl.ctrl_amm_0' start='0x0' end='0x10000000' /><slave name='sys_int_mem.s1' start='0x10140000' end='0x10168000' /><slave name='sys_cpu.debug_mem_slave' start='0x10180800' end='0x10181000' /></address-map>]]></parameter>
+  <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='sys_ddr3_cntrl_arch.ctrl_amm_0' start='0x0' end='0x10000000' type='altera_emif_arch_nf.ctrl_amm_0' /><slave name='sys_int_mem.s1' start='0x10140000' end='0x10168000' type='altera_avalon_onchip_memory2.s1' /><slave name='sys_cpu.debug_mem_slave' start='0x10180800' end='0x10181000' type='altera_nios2_gen2.debug_mem_slave' /></address-map>]]></parameter>
   <parameter name="instructionMasterHighPerformanceAddrWidth" value="1" />
   <parameter name="instructionMasterHighPerformanceMapParam" value="" />
   <parameter name="instruction_master_high_performance_paddr_base" value="0" />
@@ -832,7 +824,7 @@
   <parameter name="ocimem_ramInit" value="false" />
   <parameter name="regfile_ramBlockType" value="Automatic" />
   <parameter name="resetOffset" value="0" />
-  <parameter name="resetSlave">sys_ddr3_cntrl.ctrl_amm_0</parameter>
+  <parameter name="resetSlave">sys_ddr3_cntrl_arch.ctrl_amm_0</parameter>
   <parameter name="resetrequest_enabled" value="true" />
   <parameter name="setting_HBreakTest" value="false" />
   <parameter name="setting_HDLSimCachesCleared" value="true" />
@@ -879,7 +871,7 @@
   <parameter name="setting_usedesignware" value="false" />
   <parameter name="shift_rot_impl" value="0" />
   <parameter name="tightlyCoupledDataMaster0AddrWidth" value="29" />
-  <parameter name="tightlyCoupledDataMaster0MapParam"><![CDATA[<address-map><slave name='sys_tlb_mem.s1' start='0x10200000' end='0x10228000' /></address-map>]]></parameter>
+  <parameter name="tightlyCoupledDataMaster0MapParam"><![CDATA[<address-map><slave name='sys_tlb_mem.s1' start='0x10200000' end='0x10228000' type='altera_avalon_onchip_memory2.s1' /></address-map>]]></parameter>
   <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
   <parameter name="tightlyCoupledDataMaster1MapParam" value="" />
   <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
@@ -887,7 +879,7 @@
   <parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
   <parameter name="tightlyCoupledDataMaster3MapParam" value="" />
   <parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="29" />
-  <parameter name="tightlyCoupledInstructionMaster0MapParam"><![CDATA[<address-map><slave name='sys_tlb_mem.s2' start='0x10200000' end='0x10228000' /></address-map>]]></parameter>
+  <parameter name="tightlyCoupledInstructionMaster0MapParam"><![CDATA[<address-map><slave name='sys_tlb_mem.s2' start='0x10200000' end='0x10228000' type='altera_avalon_onchip_memory2.s2' /></address-map>]]></parameter>
   <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
   <parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
   <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
@@ -917,7 +909,7 @@
  <module
    name="sys_cpu_interconnect"
    kind="altera_avalon_mm_bridge"
-   version="15.0"
+   version="15.1"
    enabled="1">
   <parameter name="ADDRESS_UNITS" value="SYMBOLS" />
   <parameter name="ADDRESS_WIDTH" value="20" />
@@ -934,7 +926,7 @@
   <parameter name="USE_AUTO_ADDRESS_WIDTH" value="0" />
   <parameter name="USE_RESPONSE" value="0" />
  </module>
- <module name="sys_ddr3_cntrl" kind="altera_emif" version="15.0" enabled="1">
+ <module name="sys_ddr3_cntrl" kind="altera_emif" version="15.1" enabled="1">
   <parameter name="BOARD_DDR3_AC_TO_CK_SKEW_NS" value="0.0" />
   <parameter name="BOARD_DDR3_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
   <parameter name="BOARD_DDR3_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
@@ -943,8 +935,8 @@
   <parameter name="BOARD_DDR3_IS_SKEW_WITHIN_DQS_DESKEWED" value="false" />
   <parameter name="BOARD_DDR3_MAX_CK_DELAY_NS" value="0.6" />
   <parameter name="BOARD_DDR3_MAX_DQS_DELAY_NS" value="0.6" />
-  <parameter name="BOARD_DDR3_PKG+BRD_SKEW_WITHIN_AC_NS" value="0.02" />
-  <parameter name="BOARD_DDR3_PKG+BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
+  <parameter name="BOARD_DDR3_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+  <parameter name="BOARD_DDR3_PKG_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
   <parameter name="BOARD_DDR3_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
   <parameter name="BOARD_DDR3_SKEW_BETWEEN_DQS_NS" value="0.02" />
   <parameter name="BOARD_DDR3_USER_AC_ISI_NS" value="0.0" />
@@ -968,8 +960,8 @@
   <parameter name="BOARD_DDR4_IS_SKEW_WITHIN_DQS_DESKEWED" value="true" />
   <parameter name="BOARD_DDR4_MAX_CK_DELAY_NS" value="0.6" />
   <parameter name="BOARD_DDR4_MAX_DQS_DELAY_NS" value="0.6" />
-  <parameter name="BOARD_DDR4_PKG+BRD_SKEW_WITHIN_AC_NS" value="0.02" />
-  <parameter name="BOARD_DDR4_PKG+BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
+  <parameter name="BOARD_DDR4_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+  <parameter name="BOARD_DDR4_PKG_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
   <parameter name="BOARD_DDR4_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
   <parameter name="BOARD_DDR4_SKEW_BETWEEN_DQS_NS" value="0.02" />
   <parameter name="BOARD_DDR4_USER_AC_ISI_NS" value="0.0" />
@@ -985,6 +977,31 @@
   <parameter name="BOARD_DDR4_USER_WDATA_SLEW_RATE" value="2.0" />
   <parameter name="BOARD_DDR4_USE_DEFAULT_ISI_VALUES" value="true" />
   <parameter name="BOARD_DDR4_USE_DEFAULT_SLEW_RATES" value="true" />
+  <parameter name="BOARD_LPDDR3_AC_TO_CK_SKEW_NS" value="0.0" />
+  <parameter name="BOARD_LPDDR3_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+  <parameter name="BOARD_LPDDR3_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
+  <parameter name="BOARD_LPDDR3_DQS_TO_CK_SKEW_NS" value="0.02" />
+  <parameter name="BOARD_LPDDR3_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
+  <parameter name="BOARD_LPDDR3_IS_SKEW_WITHIN_DQS_DESKEWED" value="false" />
+  <parameter name="BOARD_LPDDR3_MAX_CK_DELAY_NS" value="0.6" />
+  <parameter name="BOARD_LPDDR3_MAX_DQS_DELAY_NS" value="0.6" />
+  <parameter name="BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+  <parameter name="BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
+  <parameter name="BOARD_LPDDR3_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
+  <parameter name="BOARD_LPDDR3_SKEW_BETWEEN_DQS_NS" value="0.02" />
+  <parameter name="BOARD_LPDDR3_USER_AC_ISI_NS" value="0.0" />
+  <parameter name="BOARD_LPDDR3_USER_AC_SLEW_RATE" value="2.0" />
+  <parameter name="BOARD_LPDDR3_USER_CK_SLEW_RATE" value="4.0" />
+  <parameter name="BOARD_LPDDR3_USER_RCLK_ISI_NS" value="0.0" />
+  <parameter name="BOARD_LPDDR3_USER_RCLK_SLEW_RATE" value="4.0" />
+  <parameter name="BOARD_LPDDR3_USER_RDATA_ISI_NS" value="0.0" />
+  <parameter name="BOARD_LPDDR3_USER_RDATA_SLEW_RATE" value="2.0" />
+  <parameter name="BOARD_LPDDR3_USER_WCLK_ISI_NS" value="0.0" />
+  <parameter name="BOARD_LPDDR3_USER_WCLK_SLEW_RATE" value="4.0" />
+  <parameter name="BOARD_LPDDR3_USER_WDATA_ISI_NS" value="0.0" />
+  <parameter name="BOARD_LPDDR3_USER_WDATA_SLEW_RATE" value="2.0" />
+  <parameter name="BOARD_LPDDR3_USE_DEFAULT_ISI_VALUES" value="true" />
+  <parameter name="BOARD_LPDDR3_USE_DEFAULT_SLEW_RATES" value="true" />
   <parameter name="BOARD_QDR2_AC_TO_K_SKEW_NS" value="0.0" />
   <parameter name="BOARD_QDR2_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
   <parameter name="BOARD_QDR2_BRD_SKEW_WITHIN_D_NS" value="0.02" />
@@ -993,10 +1010,9 @@
   <parameter name="BOARD_QDR2_IS_SKEW_WITHIN_D_DESKEWED" value="false" />
   <parameter name="BOARD_QDR2_IS_SKEW_WITHIN_Q_DESKEWED" value="false" />
   <parameter name="BOARD_QDR2_MAX_K_DELAY_NS" value="0.6" />
-  <parameter name="BOARD_QDR2_PKG+BRD_SKEW_WITHIN_AC_NS" value="0.02" />
-  <parameter name="BOARD_QDR2_PKG+BRD_SKEW_WITHIN_D_NS" value="0.02" />
-  <parameter name="BOARD_QDR2_PKG+BRD_SKEW_WITHIN_Q_NS" value="0.02" />
-  <parameter name="BOARD_QDR2_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
+  <parameter name="BOARD_QDR2_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+  <parameter name="BOARD_QDR2_PKG_BRD_SKEW_WITHIN_D_NS" value="0.02" />
+  <parameter name="BOARD_QDR2_PKG_BRD_SKEW_WITHIN_Q_NS" value="0.02" />
   <parameter name="BOARD_QDR2_USER_AC_ISI_NS" value="0.0" />
   <parameter name="BOARD_QDR2_USER_AC_SLEW_RATE" value="2.0" />
   <parameter name="BOARD_QDR2_USER_K_SLEW_RATE" value="4.0" />
@@ -1017,8 +1033,8 @@
   <parameter name="BOARD_QDR4_IS_SKEW_WITHIN_QK_DESKEWED" value="false" />
   <parameter name="BOARD_QDR4_MAX_CK_DELAY_NS" value="0.6" />
   <parameter name="BOARD_QDR4_MAX_DK_DELAY_NS" value="0.6" />
-  <parameter name="BOARD_QDR4_PKG+BRD_SKEW_WITHIN_AC_NS" value="0.02" />
-  <parameter name="BOARD_QDR4_PKG+BRD_SKEW_WITHIN_QK_NS" value="0.02" />
+  <parameter name="BOARD_QDR4_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+  <parameter name="BOARD_QDR4_PKG_BRD_SKEW_WITHIN_QK_NS" value="0.02" />
   <parameter name="BOARD_QDR4_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
   <parameter name="BOARD_QDR4_SKEW_BETWEEN_DK_NS" value="0.02" />
   <parameter name="BOARD_QDR4_USER_AC_ISI_NS" value="0.0" />
@@ -1042,8 +1058,8 @@
   <parameter name="BOARD_RLD3_IS_SKEW_WITHIN_QK_DESKEWED" value="false" />
   <parameter name="BOARD_RLD3_MAX_CK_DELAY_NS" value="0.6" />
   <parameter name="BOARD_RLD3_MAX_DK_DELAY_NS" value="0.6" />
-  <parameter name="BOARD_RLD3_PKG+BRD_SKEW_WITHIN_AC_NS" value="0.02" />
-  <parameter name="BOARD_RLD3_PKG+BRD_SKEW_WITHIN_QK_NS" value="0.02" />
+  <parameter name="BOARD_RLD3_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+  <parameter name="BOARD_RLD3_PKG_BRD_SKEW_WITHIN_QK_NS" value="0.02" />
   <parameter name="BOARD_RLD3_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
   <parameter name="BOARD_RLD3_SKEW_BETWEEN_DK_NS" value="0.02" />
   <parameter name="BOARD_RLD3_USER_AC_ISI_NS" value="0.0" />
@@ -1098,32 +1114,65 @@
   <parameter name="CTRL_DDR4_WR_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
   <parameter name="CTRL_DDR4_WR_TO_RD_SAME_CHIP_DELTA_CYCS" value="0" />
   <parameter name="CTRL_DDR4_WR_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+  <parameter name="CTRL_LPDDR3_ADDR_ORDER_ENUM">LPDDR3_CTRL_ADDR_ORDER_CS_R_B_C</parameter>
+  <parameter name="CTRL_LPDDR3_AUTO_POWER_DOWN_CYCS" value="32" />
+  <parameter name="CTRL_LPDDR3_AUTO_POWER_DOWN_EN" value="false" />
+  <parameter name="CTRL_LPDDR3_AUTO_PRECHARGE_EN" value="false" />
+  <parameter name="CTRL_LPDDR3_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+  <parameter name="CTRL_LPDDR3_MMR_EN" value="false" />
+  <parameter name="CTRL_LPDDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+  <parameter name="CTRL_LPDDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+  <parameter name="CTRL_LPDDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS" value="0" />
+  <parameter name="CTRL_LPDDR3_REORDER_EN" value="true" />
+  <parameter name="CTRL_LPDDR3_SELF_REFRESH_EN" value="false" />
+  <parameter name="CTRL_LPDDR3_STARVE_LIMIT" value="10" />
+  <parameter name="CTRL_LPDDR3_USER_PRIORITY_EN" value="false" />
+  <parameter name="CTRL_LPDDR3_USER_REFRESH_EN" value="false" />
+  <parameter name="CTRL_LPDDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+  <parameter name="CTRL_LPDDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS" value="0" />
+  <parameter name="CTRL_LPDDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
   <parameter name="CTRL_QDR2_AVL_ENABLE_POWER_OF_TWO_BUS" value="false" />
   <parameter name="CTRL_QDR2_AVL_MAX_BURST_COUNT" value="4" />
   <parameter name="CTRL_QDR2_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+  <parameter name="CTRL_QDR4_ADD_RAW_TURNAROUND_DELAY_CYC" value="0" />
+  <parameter name="CTRL_QDR4_ADD_WAR_TURNAROUND_DELAY_CYC" value="0" />
   <parameter name="CTRL_QDR4_AVL_ENABLE_POWER_OF_TWO_BUS" value="false" />
   <parameter name="CTRL_QDR4_AVL_MAX_BURST_COUNT" value="4" />
   <parameter name="CTRL_QDR4_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
-  <parameter name="CTRL_QDR4_RAW_TURNAROUND_DELAY_CYC" value="3" />
-  <parameter name="CTRL_QDR4_WAR_TURNAROUND_DELAY_CYC" value="10" />
   <parameter name="CTRL_RLD2_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
   <parameter name="CTRL_RLD3_ADDR_ORDER_ENUM">RLD3_CTRL_ADDR_ORDER_CS_R_B_C</parameter>
   <parameter name="CTRL_RLD3_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
   <parameter name="DIAG_BOARD_DELAY_CONFIG_STR" value="" />
+  <parameter name="DIAG_DDR3_ABSTRACT_PHY" value="false" />
+  <parameter name="DIAG_DDR3_BYPASS_DEFAULT_PATTERN" value="false" />
+  <parameter name="DIAG_DDR3_BYPASS_USER_STAGE" value="true" />
+  <parameter name="DIAG_DDR3_CAL_ADDR0" value="0" />
+  <parameter name="DIAG_DDR3_CAL_ADDR1" value="8" />
+  <parameter name="DIAG_DDR3_CAL_ENABLE_NON_DES" value="false" />
+  <parameter name="DIAG_DDR3_CAL_FULL_CAL_ON_RESET" value="true" />
   <parameter name="DIAG_DDR3_CA_LEVEL_EN" value="false" />
   <parameter name="DIAG_DDR3_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
   <parameter name="DIAG_DDR3_EXPORT_SEQ_AVALON_MASTER" value="true" />
   <parameter name="DIAG_DDR3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
   <parameter name="DIAG_DDR3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+  <parameter name="DIAG_DDR3_EX_DESIGN_SEPARATE_RZQS" value="false" />
   <parameter name="DIAG_DDR3_INTERFACE_ID" value="0" />
   <parameter name="DIAG_DDR3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
   <parameter name="DIAG_DDR3_TG_BE_PATTERN_LENGTH" value="8" />
   <parameter name="DIAG_DDR3_TG_DATA_PATTERN_LENGTH" value="8" />
   <parameter name="DIAG_DDR3_USE_TG_AVL_2" value="false" />
+  <parameter name="DIAG_DDR4_ABSTRACT_PHY" value="false" />
+  <parameter name="DIAG_DDR4_BYPASS_DEFAULT_PATTERN" value="false" />
+  <parameter name="DIAG_DDR4_BYPASS_USER_STAGE" value="true" />
+  <parameter name="DIAG_DDR4_CAL_ADDR0" value="0" />
+  <parameter name="DIAG_DDR4_CAL_ADDR1" value="8" />
+  <parameter name="DIAG_DDR4_CAL_ENABLE_NON_DES" value="false" />
+  <parameter name="DIAG_DDR4_CAL_FULL_CAL_ON_RESET" value="true" />
   <parameter name="DIAG_DDR4_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
   <parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_MASTER" value="true" />
   <parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
   <parameter name="DIAG_DDR4_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+  <parameter name="DIAG_DDR4_EX_DESIGN_SEPARATE_RZQS" value="false" />
   <parameter name="DIAG_DDR4_INTERFACE_ID" value="0" />
   <parameter name="DIAG_DDR4_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
   <parameter name="DIAG_DDR4_SKIP_CA_DESKEW" value="false" />
@@ -1141,47 +1190,128 @@
   <parameter name="DIAG_EXTRA_CONFIGS" value="" />
   <parameter name="DIAG_EX_DESIGN_ADD_TEST_EMIFS" value="" />
   <parameter name="DIAG_FAST_SIM_OVERRIDE">FAST_SIM_OVERRIDE_DEFAULT</parameter>
+  <parameter name="DIAG_LPDDR3_ABSTRACT_PHY" value="false" />
+  <parameter name="DIAG_LPDDR3_BYPASS_DEFAULT_PATTERN" value="false" />
+  <parameter name="DIAG_LPDDR3_BYPASS_USER_STAGE" value="true" />
+  <parameter name="DIAG_LPDDR3_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+  <parameter name="DIAG_LPDDR3_EXPORT_SEQ_AVALON_MASTER" value="false" />
+  <parameter name="DIAG_LPDDR3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+  <parameter name="DIAG_LPDDR3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+  <parameter name="DIAG_LPDDR3_EX_DESIGN_SEPARATE_RZQS" value="false" />
+  <parameter name="DIAG_LPDDR3_INTERFACE_ID" value="0" />
+  <parameter name="DIAG_LPDDR3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+  <parameter name="DIAG_LPDDR3_SKIP_CA_DESKEW" value="false" />
+  <parameter name="DIAG_LPDDR3_SKIP_CA_LEVEL" value="false" />
+  <parameter name="DIAG_LPDDR3_TG_BE_PATTERN_LENGTH" value="8" />
+  <parameter name="DIAG_LPDDR3_TG_DATA_PATTERN_LENGTH" value="8" />
+  <parameter name="DIAG_LPDDR3_USE_TG_AVL_2" value="false" />
+  <parameter name="DIAG_QDR2_ABSTRACT_PHY" value="false" />
+  <parameter name="DIAG_QDR2_BYPASS_DEFAULT_PATTERN" value="false" />
+  <parameter name="DIAG_QDR2_BYPASS_USER_STAGE" value="true" />
   <parameter name="DIAG_QDR2_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
   <parameter name="DIAG_QDR2_EXPORT_SEQ_AVALON_MASTER" value="true" />
   <parameter name="DIAG_QDR2_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
   <parameter name="DIAG_QDR2_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+  <parameter name="DIAG_QDR2_EX_DESIGN_SEPARATE_RZQS" value="false" />
   <parameter name="DIAG_QDR2_INTERFACE_ID" value="0" />
   <parameter name="DIAG_QDR2_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
   <parameter name="DIAG_QDR2_TG_BE_PATTERN_LENGTH" value="8" />
   <parameter name="DIAG_QDR2_TG_DATA_PATTERN_LENGTH" value="8" />
   <parameter name="DIAG_QDR2_USE_TG_AVL_2" value="false" />
+  <parameter name="DIAG_QDR4_ABSTRACT_PHY" value="false" />
+  <parameter name="DIAG_QDR4_BYPASS_DEFAULT_PATTERN" value="false" />
+  <parameter name="DIAG_QDR4_BYPASS_USER_STAGE" value="true" />
   <parameter name="DIAG_QDR4_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
   <parameter name="DIAG_QDR4_EXPORT_SEQ_AVALON_MASTER" value="true" />
   <parameter name="DIAG_QDR4_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
   <parameter name="DIAG_QDR4_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+  <parameter name="DIAG_QDR4_EX_DESIGN_SEPARATE_RZQS" value="false" />
   <parameter name="DIAG_QDR4_INTERFACE_ID" value="0" />
   <parameter name="DIAG_QDR4_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+  <parameter name="DIAG_QDR4_SKIP_VREF_CAL" value="false" />
   <parameter name="DIAG_QDR4_TG_BE_PATTERN_LENGTH" value="8" />
   <parameter name="DIAG_QDR4_TG_DATA_PATTERN_LENGTH" value="8" />
   <parameter name="DIAG_QDR4_USE_TG_AVL_2" value="false" />
+  <parameter name="DIAG_RLD2_ABSTRACT_PHY" value="false" />
+  <parameter name="DIAG_RLD2_BYPASS_DEFAULT_PATTERN" value="false" />
+  <parameter name="DIAG_RLD2_BYPASS_USER_STAGE" value="true" />
   <parameter name="DIAG_RLD2_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
   <parameter name="DIAG_RLD2_EXPORT_SEQ_AVALON_MASTER" value="true" />
   <parameter name="DIAG_RLD2_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
   <parameter name="DIAG_RLD2_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+  <parameter name="DIAG_RLD2_EX_DESIGN_SEPARATE_RZQS" value="false" />
   <parameter name="DIAG_RLD2_INTERFACE_ID" value="0" />
   <parameter name="DIAG_RLD2_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
   <parameter name="DIAG_RLD2_TG_BE_PATTERN_LENGTH" value="8" />
   <parameter name="DIAG_RLD2_TG_DATA_PATTERN_LENGTH" value="8" />
   <parameter name="DIAG_RLD2_USE_TG_AVL_2" value="false" />
+  <parameter name="DIAG_RLD3_ABSTRACT_PHY" value="false" />
+  <parameter name="DIAG_RLD3_BYPASS_DEFAULT_PATTERN" value="false" />
+  <parameter name="DIAG_RLD3_BYPASS_USER_STAGE" value="true" />
   <parameter name="DIAG_RLD3_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
   <parameter name="DIAG_RLD3_EXPORT_SEQ_AVALON_MASTER" value="true" />
   <parameter name="DIAG_RLD3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
   <parameter name="DIAG_RLD3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+  <parameter name="DIAG_RLD3_EX_DESIGN_SEPARATE_RZQS" value="false" />
   <parameter name="DIAG_RLD3_INTERFACE_ID" value="0" />
   <parameter name="DIAG_RLD3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
   <parameter name="DIAG_RLD3_TG_BE_PATTERN_LENGTH" value="8" />
   <parameter name="DIAG_RLD3_TG_DATA_PATTERN_LENGTH" value="8" />
   <parameter name="DIAG_RLD3_USE_TG_AVL_2" value="false" />
+  <parameter name="DIAG_RS232_UART_BAUDRATE" value="57600" />
   <parameter name="DIAG_SIM_REGTEST_MODE" value="false" />
+  <parameter name="DIAG_SOFT_NIOS_CLOCK_FREQUENCY" value="100" />
+  <parameter name="DIAG_SOFT_NIOS_MODE">SOFT_NIOS_MODE_DISABLED</parameter>
   <parameter name="DIAG_SYNTH_FOR_SIM" value="false" />
+  <parameter name="DIAG_TG_AVL_2_NUM_CFG_INTERFACES" value="0" />
   <parameter name="DIAG_TIMING_REGTEST_MODE" value="false" />
   <parameter name="DIAG_USE_BOARD_DELAY_MODEL" value="false" />
+  <parameter name="DIAG_USE_RS232_UART" value="false" />
   <parameter name="DIAG_VERBOSE_IOAUX" value="false" />
+  <parameter name="EX_DESIGN_GUI_DDR3_GEN_SIM" value="true" />
+  <parameter name="EX_DESIGN_GUI_DDR3_GEN_SYNTH" value="true" />
+  <parameter name="EX_DESIGN_GUI_DDR3_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+  <parameter name="EX_DESIGN_GUI_DDR3_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+  <parameter name="EX_DESIGN_GUI_DDR3_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+  <parameter name="EX_DESIGN_GUI_DDR3_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
+  <parameter name="EX_DESIGN_GUI_DDR4_GEN_SIM" value="true" />
+  <parameter name="EX_DESIGN_GUI_DDR4_GEN_SYNTH" value="true" />
+  <parameter name="EX_DESIGN_GUI_DDR4_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+  <parameter name="EX_DESIGN_GUI_DDR4_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+  <parameter name="EX_DESIGN_GUI_DDR4_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+  <parameter name="EX_DESIGN_GUI_DDR4_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
+  <parameter name="EX_DESIGN_GUI_LPDDR3_GEN_SIM" value="true" />
+  <parameter name="EX_DESIGN_GUI_LPDDR3_GEN_SYNTH" value="true" />
+  <parameter name="EX_DESIGN_GUI_LPDDR3_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+  <parameter name="EX_DESIGN_GUI_LPDDR3_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+  <parameter name="EX_DESIGN_GUI_LPDDR3_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+  <parameter
+     name="EX_DESIGN_GUI_LPDDR3_TARGET_DEV_KIT"
+     value="TARGET_DEV_KIT_NONE" />
+  <parameter name="EX_DESIGN_GUI_QDR2_GEN_SIM" value="true" />
+  <parameter name="EX_DESIGN_GUI_QDR2_GEN_SYNTH" value="true" />
+  <parameter name="EX_DESIGN_GUI_QDR2_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+  <parameter name="EX_DESIGN_GUI_QDR2_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+  <parameter name="EX_DESIGN_GUI_QDR2_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+  <parameter name="EX_DESIGN_GUI_QDR2_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
+  <parameter name="EX_DESIGN_GUI_QDR4_GEN_SIM" value="true" />
+  <parameter name="EX_DESIGN_GUI_QDR4_GEN_SYNTH" value="true" />
+  <parameter name="EX_DESIGN_GUI_QDR4_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+  <parameter name="EX_DESIGN_GUI_QDR4_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+  <parameter name="EX_DESIGN_GUI_QDR4_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+  <parameter name="EX_DESIGN_GUI_QDR4_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
+  <parameter name="EX_DESIGN_GUI_RLD2_GEN_SIM" value="true" />
+  <parameter name="EX_DESIGN_GUI_RLD2_GEN_SYNTH" value="true" />
+  <parameter name="EX_DESIGN_GUI_RLD2_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+  <parameter name="EX_DESIGN_GUI_RLD2_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+  <parameter name="EX_DESIGN_GUI_RLD2_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+  <parameter name="EX_DESIGN_GUI_RLD2_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
+  <parameter name="EX_DESIGN_GUI_RLD3_GEN_SIM" value="true" />
+  <parameter name="EX_DESIGN_GUI_RLD3_GEN_SYNTH" value="true" />
+  <parameter name="EX_DESIGN_GUI_RLD3_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+  <parameter name="EX_DESIGN_GUI_RLD3_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+  <parameter name="EX_DESIGN_GUI_RLD3_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+  <parameter name="EX_DESIGN_GUI_RLD3_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
   <parameter name="INTERNAL_TESTING_MODE" value="false" />
   <parameter name="IS_ED_SLAVE" value="false" />
   <parameter name="MEM_DDR3_ALERT_N_DQS_GROUP" value="0" />
@@ -1300,6 +1430,7 @@
   <parameter name="MEM_DDR4_GEARDOWN" value="DDR4_GEARDOWN_HR" />
   <parameter name="MEM_DDR4_INTERNAL_VREFDQ_MONITOR" value="false" />
   <parameter name="MEM_DDR4_LRDIMM_EXTENDED_CONFIG" value="0000000000000000" />
+  <parameter name="MEM_DDR4_LRDIMM_VREFDQ_VALUE" value="1D" />
   <parameter name="MEM_DDR4_MAX_POWERDOWN" value="false" />
   <parameter name="MEM_DDR4_MIRROR_ADDRESSING_EN" value="true" />
   <parameter name="MEM_DDR4_MPR_READ_FORMAT">DDR4_MPR_READ_FORMAT_SERIAL</parameter>
@@ -1334,8 +1465,10 @@
   <parameter name="MEM_DDR4_TCCD_S_CYC" value="4" />
   <parameter name="MEM_DDR4_TCL" value="18" />
   <parameter name="MEM_DDR4_TDIVW_DJ_CYC" value="0.1" />
+  <parameter name="MEM_DDR4_TDIVW_TOTAL_UI" value="0.2" />
   <parameter name="MEM_DDR4_TDQSCK_PS" value="165" />
   <parameter name="MEM_DDR4_TDQSQ_PS" value="66" />
+  <parameter name="MEM_DDR4_TDQSQ_UI" value="0.16" />
   <parameter name="MEM_DDR4_TDQSS_CYC" value="0.27" />
   <parameter name="MEM_DDR4_TDSH_CYC" value="0.18" />
   <parameter name="MEM_DDR4_TDSS_CYC" value="0.18" />
@@ -1350,6 +1483,7 @@
   <parameter name="MEM_DDR4_TIS_PS" value="60" />
   <parameter name="MEM_DDR4_TMRD_CK_CYC" value="8" />
   <parameter name="MEM_DDR4_TQH_CYC" value="0.38" />
+  <parameter name="MEM_DDR4_TQH_UI" value="0.76" />
   <parameter name="MEM_DDR4_TQSH_CYC" value="0.38" />
   <parameter name="MEM_DDR4_TRAS_NS" value="32.0" />
   <parameter name="MEM_DDR4_TRCD_NS" value="15.0" />
@@ -1384,6 +1518,70 @@
   <parameter name="MEM_DDR4_W_ODTN_2X2" value="Rank 0,Rank 1" />
   <parameter name="MEM_DDR4_W_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
   <parameter name="MEM_DDR4_W_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+  <parameter name="MEM_LPDDR3_BANK_ADDR_WIDTH" value="3" />
+  <parameter name="MEM_LPDDR3_BL" value="LPDDR3_BL_BL8" />
+  <parameter name="MEM_LPDDR3_COL_ADDR_WIDTH" value="10" />
+  <parameter name="MEM_LPDDR3_DATA_LATENCY" value="LPDDR3_DL_RL12_WL6" />
+  <parameter name="MEM_LPDDR3_DISCRETE_CS_WIDTH" value="1" />
+  <parameter name="MEM_LPDDR3_DM_EN" value="true" />
+  <parameter name="MEM_LPDDR3_DQODT">LPDDR3_DQODT_DISABLE</parameter>
+  <parameter name="MEM_LPDDR3_DQ_WIDTH" value="32" />
+  <parameter name="MEM_LPDDR3_DRV_STR">LPDDR3_DRV_STR_40D_40U</parameter>
+  <parameter name="MEM_LPDDR3_NWR" value="LPDDR3_NWR_NWR10" />
+  <parameter name="MEM_LPDDR3_PDODT">LPDDR3_PDODT_DISABLED</parameter>
+  <parameter name="MEM_LPDDR3_ROW_ADDR_WIDTH" value="15" />
+  <parameter name="MEM_LPDDR3_R_ODT0_1X1" value="off" />
+  <parameter name="MEM_LPDDR3_R_ODT0_2X2" value="off,off" />
+  <parameter name="MEM_LPDDR3_R_ODT0_4X4" value="off,off,on,on" />
+  <parameter name="MEM_LPDDR3_R_ODT1_2X2" value="off,off" />
+  <parameter name="MEM_LPDDR3_R_ODT1_4X4" value="off,off,off,off" />
+  <parameter name="MEM_LPDDR3_R_ODT2_4X4" value="on,on,off,off" />
+  <parameter name="MEM_LPDDR3_R_ODT3_4X4" value="off,off,off,off" />
+  <parameter name="MEM_LPDDR3_R_ODTN_1X1" value="Rank 0" />
+  <parameter name="MEM_LPDDR3_R_ODTN_2X2" value="Rank 0,Rank 1" />
+  <parameter name="MEM_LPDDR3_R_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+  <parameter name="MEM_LPDDR3_SPEEDBIN_ENUM">LPDDR3_SPEEDBIN_1600</parameter>
+  <parameter name="MEM_LPDDR3_TDH_DC_MV" value="100" />
+  <parameter name="MEM_LPDDR3_TDH_PS" value="100" />
+  <parameter name="MEM_LPDDR3_TDQSCK_PS" value="614" />
+  <parameter name="MEM_LPDDR3_TDQSQ_PS" value="135" />
+  <parameter name="MEM_LPDDR3_TDQSS_CYC" value="1.25" />
+  <parameter name="MEM_LPDDR3_TDSH_CYC" value="0.2" />
+  <parameter name="MEM_LPDDR3_TDSS_CYC" value="0.2" />
+  <parameter name="MEM_LPDDR3_TDS_AC_MV" value="150" />
+  <parameter name="MEM_LPDDR3_TDS_PS" value="75" />
+  <parameter name="MEM_LPDDR3_TFAW_NS" value="50.0" />
+  <parameter name="MEM_LPDDR3_TIH_DC_MV" value="100" />
+  <parameter name="MEM_LPDDR3_TIH_PS" value="100" />
+  <parameter name="MEM_LPDDR3_TINIT_US" value="500" />
+  <parameter name="MEM_LPDDR3_TIS_AC_MV" value="150" />
+  <parameter name="MEM_LPDDR3_TIS_PS" value="75" />
+  <parameter name="MEM_LPDDR3_TMRR_CK_CYC" value="4" />
+  <parameter name="MEM_LPDDR3_TMRW_CK_CYC" value="10" />
+  <parameter name="MEM_LPDDR3_TQH_CYC" value="0.38" />
+  <parameter name="MEM_LPDDR3_TQSH_CYC" value="0.38" />
+  <parameter name="MEM_LPDDR3_TRAS_NS" value="42.5" />
+  <parameter name="MEM_LPDDR3_TRCD_NS" value="18.75" />
+  <parameter name="MEM_LPDDR3_TREFI_US" value="3.9" />
+  <parameter name="MEM_LPDDR3_TRFC_NS" value="210.0" />
+  <parameter name="MEM_LPDDR3_TRP_NS" value="18.75" />
+  <parameter name="MEM_LPDDR3_TRRD_CYC" value="2" />
+  <parameter name="MEM_LPDDR3_TRTP_CYC" value="4" />
+  <parameter name="MEM_LPDDR3_TWLH_PS" value="175.0" />
+  <parameter name="MEM_LPDDR3_TWLS_PS" value="175.0" />
+  <parameter name="MEM_LPDDR3_TWR_NS" value="15.0" />
+  <parameter name="MEM_LPDDR3_TWTR_CYC" value="4" />
+  <parameter name="MEM_LPDDR3_USE_DEFAULT_ODT" value="true" />
+  <parameter name="MEM_LPDDR3_W_ODT0_1X1" value="on" />
+  <parameter name="MEM_LPDDR3_W_ODT0_2X2" value="on,off" />
+  <parameter name="MEM_LPDDR3_W_ODT0_4X4" value="on,on,on,on" />
+  <parameter name="MEM_LPDDR3_W_ODT1_2X2" value="off,on" />
+  <parameter name="MEM_LPDDR3_W_ODT1_4X4" value="off,off,off,off" />
+  <parameter name="MEM_LPDDR3_W_ODT2_4X4" value="on,on,on,on" />
+  <parameter name="MEM_LPDDR3_W_ODT3_4X4" value="off,off,off,off" />
+  <parameter name="MEM_LPDDR3_W_ODTN_1X1" value="Rank 0" />
+  <parameter name="MEM_LPDDR3_W_ODTN_2X2" value="Rank 0,Rank 1" />
+  <parameter name="MEM_LPDDR3_W_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
   <parameter name="MEM_QDR2_ADDR_WIDTH" value="19" />
   <parameter name="MEM_QDR2_BL" value="4" />
   <parameter name="MEM_QDR2_BWS_EN" value="true" />
@@ -1458,9 +1656,13 @@
   <parameter name="MEM_RLD3_TCKDK_MAX_CYC" value="0.27" />
   <parameter name="MEM_RLD3_TCKDK_MIN_CYC" value="-0.27" />
   <parameter name="MEM_RLD3_TCKQK_MAX_PS" value="135" />
+  <parameter name="MEM_RLD3_TDH_DC_MV" value="100" />
   <parameter name="MEM_RLD3_TDH_PS" value="5" />
+  <parameter name="MEM_RLD3_TDS_AC_MV" value="150" />
   <parameter name="MEM_RLD3_TDS_PS" value="-30" />
+  <parameter name="MEM_RLD3_TIH_DC_MV" value="100" />
   <parameter name="MEM_RLD3_TIH_PS" value="65" />
+  <parameter name="MEM_RLD3_TIS_AC_MV" value="150" />
   <parameter name="MEM_RLD3_TIS_PS" value="85" />
   <parameter name="MEM_RLD3_TQH_CYC" value="0.38" />
   <parameter name="MEM_RLD3_TQKQ_MAX_PS" value="75" />
@@ -1513,6 +1715,27 @@
   <parameter name="PHY_DDR4_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
   <parameter name="PHY_DDR4_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
   <parameter name="PHY_DDR4_USER_RZQ_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_LPDDR3_CONFIG_ENUM">CONFIG_PHY_AND_HARD_CTRL</parameter>
+  <parameter name="PHY_LPDDR3_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+  <parameter name="PHY_LPDDR3_DEFAULT_IO" value="true" />
+  <parameter name="PHY_LPDDR3_DEFAULT_REF_CLK_FREQ" value="true" />
+  <parameter name="PHY_LPDDR3_IO_VOLTAGE" value="1.2" />
+  <parameter name="PHY_LPDDR3_MEM_CLK_FREQ_MHZ" value="800.0" />
+  <parameter name="PHY_LPDDR3_RATE_ENUM" value="RATE_QUARTER" />
+  <parameter name="PHY_LPDDR3_REF_CLK_JITTER_PS" value="10.0" />
+  <parameter name="PHY_LPDDR3_USER_AC_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_LPDDR3_USER_AC_MODE_ENUM" value="unset" />
+  <parameter name="PHY_LPDDR3_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+  <parameter name="PHY_LPDDR3_USER_CK_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_LPDDR3_USER_CK_MODE_ENUM" value="unset" />
+  <parameter name="PHY_LPDDR3_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+  <parameter name="PHY_LPDDR3_USER_DATA_IN_MODE_ENUM" value="unset" />
+  <parameter name="PHY_LPDDR3_USER_DATA_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_LPDDR3_USER_DATA_OUT_MODE_ENUM" value="unset" />
+  <parameter name="PHY_LPDDR3_USER_PING_PONG_EN" value="false" />
+  <parameter name="PHY_LPDDR3_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+  <parameter name="PHY_LPDDR3_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+  <parameter name="PHY_LPDDR3_USER_RZQ_IO_STD_ENUM" value="unset" />
   <parameter name="PHY_QDR2_CONFIG_ENUM">CONFIG_PHY_AND_SOFT_CTRL</parameter>
   <parameter name="PHY_QDR2_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
   <parameter name="PHY_QDR2_DEFAULT_IO" value="true" />
@@ -1643,8 +1866,9 @@
   <parameter name="SYS_INFO_DEVICE_FAMILY" value="Arria 10" />
   <parameter name="SYS_INFO_DEVICE_SPEEDGRADE" value="2" />
   <parameter name="SYS_INFO_UNIQUE_ID">$${FILENAME}_sys_ddr3_cntrl</parameter>
+  <parameter name="TRAIT_SUPPORTS_VID" value="0" />
  </module>
- <module name="sys_ethernet" kind="altera_eth_tse" version="15.0" enabled="1">
+ <module name="sys_ethernet" kind="altera_eth_tse" version="15.1" enabled="1">
   <parameter name="AUTO_DEVICE" value="10AX115S3F45I2SGE2" />
   <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
   <parameter name="core_variation" value="MAC_PCS" />
@@ -1688,14 +1912,22 @@
  <module
    name="sys_ethernet_dma_rx"
    kind="altera_msgdma"
-   version="15.0"
+   version="15.1"
    enabled="1">
+  <parameter name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_MAP" value="" />
+  <parameter
+     name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_WIDTH"
+     value="AddressWidth = -1" />
+  <parameter name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_MAP" value="" />
+  <parameter
+     name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH"
+     value="AddressWidth = -1" />
   <parameter name="AUTO_DEVICE" value="10AX115S3F45I2SGE2" />
   <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
   <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
   <parameter name="AUTO_MM_READ_ADDRESS_MAP" value="" />
   <parameter name="AUTO_MM_READ_ADDRESS_WIDTH" value="AddressWidth = -1" />
-  <parameter name="AUTO_MM_WRITE_ADDRESS_MAP"><![CDATA[<address-map><slave name='sys_ddr3_cntrl.ctrl_amm_0' start='0x0' end='0x10000000' /></address-map>]]></parameter>
+  <parameter name="AUTO_MM_WRITE_ADDRESS_MAP"><![CDATA[<address-map><slave name='sys_ddr3_cntrl_arch.ctrl_amm_0' start='0x0' end='0x10000000' /></address-map>]]></parameter>
   <parameter name="AUTO_MM_WRITE_ADDRESS_WIDTH" value="AddressWidth = 28" />
   <parameter name="BURST_ENABLE" value="1" />
   <parameter name="BURST_WRAPPING_SUPPORT" value="0" />
@@ -1707,25 +1939,39 @@
   <parameter name="ENHANCED_FEATURES" value="1" />
   <parameter name="ERROR_ENABLE" value="1" />
   <parameter name="ERROR_WIDTH" value="6" />
+  <parameter name="FIX_ADDRESS_WIDTH" value="32" />
   <parameter name="MAX_BURST_COUNT" value="64" />
   <parameter name="MAX_BYTE" value="2048" />
   <parameter name="MAX_STRIDE" value="1" />
   <parameter name="MODE" value="2" />
   <parameter name="PACKET_ENABLE" value="1" />
+  <parameter name="PREFETCHER_DATA_WIDTH" value="32" />
+  <parameter name="PREFETCHER_ENABLE" value="0" />
+  <parameter name="PREFETCHER_MAX_READ_BURST_COUNT" value="2" />
+  <parameter name="PREFETCHER_READ_BURST_ENABLE" value="0" />
   <parameter name="PROGRAMMABLE_BURST_ENABLE" value="0" />
   <parameter name="RESPONSE_PORT" value="0" />
   <parameter name="STRIDE_ENABLE" value="0" />
   <parameter name="TRANSFER_TYPE" value="Unaligned Accesses" />
+  <parameter name="USE_FIX_ADDRESS_WIDTH" value="0" />
  </module>
  <module
    name="sys_ethernet_dma_tx"
    kind="altera_msgdma"
-   version="15.0"
+   version="15.1"
    enabled="1">
+  <parameter name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_MAP" value="" />
+  <parameter
+     name="AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_WIDTH"
+     value="AddressWidth = -1" />
+  <parameter name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_MAP" value="" />
+  <parameter
+     name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH"
+     value="AddressWidth = -1" />
   <parameter name="AUTO_DEVICE" value="10AX115S3F45I2SGE2" />
   <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
   <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
-  <parameter name="AUTO_MM_READ_ADDRESS_MAP"><![CDATA[<address-map><slave name='sys_ddr3_cntrl.ctrl_amm_0' start='0x0' end='0x10000000' /></address-map>]]></parameter>
+  <parameter name="AUTO_MM_READ_ADDRESS_MAP"><![CDATA[<address-map><slave name='sys_ddr3_cntrl_arch.ctrl_amm_0' start='0x0' end='0x10000000' /></address-map>]]></parameter>
   <parameter name="AUTO_MM_READ_ADDRESS_WIDTH" value="AddressWidth = 28" />
   <parameter name="AUTO_MM_WRITE_ADDRESS_MAP" value="" />
   <parameter name="AUTO_MM_WRITE_ADDRESS_WIDTH" value="AddressWidth = -1" />
@@ -1739,20 +1985,26 @@
   <parameter name="ENHANCED_FEATURES" value="1" />
   <parameter name="ERROR_ENABLE" value="1" />
   <parameter name="ERROR_WIDTH" value="1" />
+  <parameter name="FIX_ADDRESS_WIDTH" value="32" />
   <parameter name="MAX_BURST_COUNT" value="64" />
   <parameter name="MAX_BYTE" value="2048" />
   <parameter name="MAX_STRIDE" value="1" />
   <parameter name="MODE" value="1" />
   <parameter name="PACKET_ENABLE" value="1" />
+  <parameter name="PREFETCHER_DATA_WIDTH" value="32" />
+  <parameter name="PREFETCHER_ENABLE" value="0" />
+  <parameter name="PREFETCHER_MAX_READ_BURST_COUNT" value="2" />
+  <parameter name="PREFETCHER_READ_BURST_ENABLE" value="0" />
   <parameter name="PROGRAMMABLE_BURST_ENABLE" value="0" />
   <parameter name="RESPONSE_PORT" value="2" />
   <parameter name="STRIDE_ENABLE" value="0" />
   <parameter name="TRANSFER_TYPE" value="Unaligned Accesses" />
+  <parameter name="USE_FIX_ADDRESS_WIDTH" value="0" />
  </module>
  <module
    name="sys_ethernet_reset"
    kind="altera_reset_bridge"
-   version="15.0"
+   version="15.1"
    enabled="1">
   <parameter name="ACTIVE_LOW_RESET" value="0" />
   <parameter name="AUTO_CLK_CLOCK_RATE" value="100000000" />
@@ -1763,7 +2015,7 @@
  <module
    name="sys_gpio_bd"
    kind="altera_avalon_pio"
-   version="15.0"
+   version="15.1"
    enabled="1">
   <parameter name="bitClearingEdgeCapReg" value="false" />
   <parameter name="bitModifyingOutReg" value="false" />
@@ -1781,7 +2033,7 @@
  <module
    name="sys_gpio_in"
    kind="altera_avalon_pio"
-   version="15.0"
+   version="15.1"
    enabled="1">
   <parameter name="bitClearingEdgeCapReg" value="false" />
   <parameter name="bitModifyingOutReg" value="false" />
@@ -1799,7 +2051,7 @@
  <module
    name="sys_gpio_out"
    kind="altera_avalon_pio"
-   version="15.0"
+   version="15.1"
    enabled="1">
   <parameter name="bitClearingEdgeCapReg" value="false" />
   <parameter name="bitModifyingOutReg" value="false" />
@@ -1817,7 +2069,7 @@
  <module
    name="sys_id"
    kind="altera_avalon_sysid_qsys"
-   version="15.0"
+   version="15.1"
    enabled="1">
   <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
   <parameter name="id" value="182193580" />
@@ -1825,7 +2077,7 @@
  <module
    name="sys_int_mem"
    kind="altera_avalon_onchip_memory2"
-   version="15.0"
+   version="15.1"
    enabled="1">
   <parameter name="allowInSystemMemoryContentEditor" value="false" />
   <parameter name="autoInitializationFileName">$${FILENAME}_sys_int_mem</parameter>
@@ -1833,7 +2085,7 @@
   <parameter name="copyInitFile" value="false" />
   <parameter name="dataWidth" value="32" />
   <parameter name="deviceFamily" value="Arria 10" />
-  <parameter name="deviceFeatures">ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 1 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</parameter>
+  <parameter name="deviceFeatures">ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 1 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</parameter>
   <parameter name="dualPort" value="false" />
   <parameter name="ecc_enabled" value="false" />
   <parameter name="initMemContent" value="false" />
@@ -1851,7 +2103,7 @@
   <parameter name="useShallowMemBlocks" value="false" />
   <parameter name="writable" value="true" />
  </module>
- <module name="sys_irq" kind="altera_irq_bridge" version="15.0" enabled="1">
+ <module name="sys_irq" kind="altera_irq_bridge" version="15.1" enabled="1">
   <parameter name="AUTO_CLK_CLOCK_RATE" value="100000000" />
   <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
   <parameter name="AUTO_RECEIVER_IRQ_INTERRUPTS_USED" value="0" />
@@ -1861,7 +2113,7 @@
  <module
    name="sys_mem_interconnect"
    kind="altera_avalon_mm_bridge"
-   version="15.0"
+   version="15.1"
    enabled="1">
   <parameter name="ADDRESS_UNITS" value="SYMBOLS" />
   <parameter name="ADDRESS_WIDTH" value="29" />
@@ -1878,14 +2130,14 @@
   <parameter name="USE_AUTO_ADDRESS_WIDTH" value="0" />
   <parameter name="USE_RESPONSE" value="0" />
  </module>
- <module name="sys_rst" kind="altera_reset_bridge" version="15.0" enabled="1">
+ <module name="sys_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
   <parameter name="ACTIVE_LOW_RESET" value="0" />
   <parameter name="AUTO_CLK_CLOCK_RATE" value="100000000" />
   <parameter name="NUM_RESET_OUTPUTS" value="1" />
   <parameter name="SYNCHRONOUS_EDGES" value="deassert" />
   <parameter name="USE_RESET_REQUEST" value="0" />
  </module>
- <module name="sys_spi" kind="altera_avalon_spi" version="15.0" enabled="1">
+ <module name="sys_spi" kind="altera_avalon_spi" version="15.1" enabled="1">
   <parameter name="avalonSpec" value="2.0" />
   <parameter name="clockPhase" value="0" />
   <parameter name="clockPolarity" value="0" />
@@ -1904,7 +2156,7 @@
  <module
    name="sys_timer"
    kind="altera_avalon_timer"
-   version="15.0"
+   version="15.1"
    enabled="1">
   <parameter name="alwaysRun" value="false" />
   <parameter name="counterSize" value="32" />
@@ -1920,7 +2172,7 @@
  <module
    name="sys_timer_2nd"
    kind="altera_avalon_timer"
-   version="15.0"
+   version="15.1"
    enabled="1">
   <parameter name="alwaysRun" value="false" />
   <parameter name="counterSize" value="32" />
@@ -1936,7 +2188,7 @@
  <module
    name="sys_tlb_mem"
    kind="altera_avalon_onchip_memory2"
-   version="15.0"
+   version="15.1"
    enabled="1">
   <parameter name="allowInSystemMemoryContentEditor" value="false" />
   <parameter name="autoInitializationFileName">$${FILENAME}_sys_tlb_mem</parameter>
@@ -1944,7 +2196,7 @@
   <parameter name="copyInitFile" value="false" />
   <parameter name="dataWidth" value="32" />
   <parameter name="deviceFamily" value="Arria 10" />
-  <parameter name="deviceFeatures">ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 1 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</parameter>
+  <parameter name="deviceFeatures">ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 1 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</parameter>
   <parameter name="dualPort" value="true" />
   <parameter name="ecc_enabled" value="false" />
   <parameter name="initMemContent" value="true" />
@@ -1965,7 +2217,7 @@
  <module
    name="sys_uart"
    kind="altera_avalon_jtag_uart"
-   version="15.0"
+   version="15.1"
    enabled="1">
   <parameter name="allowMultipleConnections" value="false" />
   <parameter name="avalonSpec" value="2.0" />
@@ -1983,7 +2235,7 @@
  </module>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.data_master"
    end="sys_uart.avalon_jtag_slave">
   <parameter name="arbitrationPriority" value="1" />
@@ -1992,7 +2244,7 @@
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.data_master"
    end="sys_ethernet.control_port">
   <parameter name="arbitrationPriority" value="1" />
@@ -2001,7 +2253,7 @@
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.data_master"
    end="sys_id.control_slave">
   <parameter name="arbitrationPriority" value="1" />
@@ -2010,7 +2262,7 @@
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.data_master"
    end="sys_ethernet_dma_rx.csr">
   <parameter name="arbitrationPriority" value="1" />
@@ -2019,7 +2271,7 @@
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.data_master"
    end="sys_ethernet_dma_tx.csr">
   <parameter name="arbitrationPriority" value="1" />
@@ -2028,7 +2280,7 @@
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.data_master"
    end="sys_ddr3_cntrl.ctrl_amm_0">
   <parameter name="arbitrationPriority" value="1" />
@@ -2037,7 +2289,7 @@
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.data_master"
    end="sys_cpu.debug_mem_slave">
   <parameter name="arbitrationPriority" value="1" />
@@ -2046,7 +2298,7 @@
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.data_master"
    end="sys_ethernet_dma_tx.descriptor_slave">
   <parameter name="arbitrationPriority" value="1" />
@@ -2055,7 +2307,7 @@
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.data_master"
    end="sys_ethernet_dma_rx.descriptor_slave">
   <parameter name="arbitrationPriority" value="1" />
@@ -2064,7 +2316,7 @@
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.data_master"
    end="sys_ethernet_dma_rx.response">
   <parameter name="arbitrationPriority" value="1" />
@@ -2073,7 +2325,7 @@
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.data_master"
    end="sys_cpu_interconnect.s0">
   <parameter name="arbitrationPriority" value="1" />
@@ -2082,7 +2334,7 @@
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.data_master"
    end="sys_int_mem.s1">
   <parameter name="arbitrationPriority" value="1" />
@@ -2091,7 +2343,7 @@
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.data_master"
    end="sys_timer.s1">
   <parameter name="arbitrationPriority" value="1" />
@@ -2100,7 +2352,7 @@
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.data_master"
    end="sys_gpio_bd.s1">
   <parameter name="arbitrationPriority" value="1" />
@@ -2109,7 +2361,7 @@
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.data_master"
    end="sys_gpio_in.s1">
   <parameter name="arbitrationPriority" value="1" />
@@ -2118,7 +2370,7 @@
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.data_master"
    end="sys_gpio_out.s1">
   <parameter name="arbitrationPriority" value="1" />
@@ -2127,7 +2379,7 @@
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.data_master"
    end="sys_timer_2nd.s1">
   <parameter name="arbitrationPriority" value="1" />
@@ -2136,7 +2388,7 @@
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.data_master"
    end="sys_spi.spi_control_port">
   <parameter name="arbitrationPriority" value="1" />
@@ -2145,7 +2397,7 @@
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.instruction_master"
    end="sys_ddr3_cntrl.ctrl_amm_0">
   <parameter name="arbitrationPriority" value="1" />
@@ -2154,7 +2406,7 @@
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.instruction_master"
    end="sys_cpu.debug_mem_slave">
   <parameter name="arbitrationPriority" value="1" />
@@ -2163,7 +2415,7 @@
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.instruction_master"
    end="sys_int_mem.s1">
   <parameter name="arbitrationPriority" value="1" />
@@ -2172,7 +2424,7 @@
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="sys_mem_interconnect.m0"
    end="sys_ddr3_cntrl.ctrl_amm_0">
   <parameter name="arbitrationPriority" value="1" />
@@ -2181,7 +2433,7 @@
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="sys_ethernet_dma_tx.mm_read"
    end="sys_ddr3_cntrl.ctrl_amm_0">
   <parameter name="arbitrationPriority" value="1" />
@@ -2190,7 +2442,7 @@
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="sys_ethernet_dma_rx.mm_write"
    end="sys_ddr3_cntrl.ctrl_amm_0">
   <parameter name="arbitrationPriority" value="1" />
@@ -2199,7 +2451,7 @@
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.tightly_coupled_data_master_0"
    end="sys_tlb_mem.s1">
   <parameter name="arbitrationPriority" value="1" />
@@ -2208,7 +2460,7 @@
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.tightly_coupled_instruction_master_0"
    end="sys_tlb_mem.s2">
   <parameter name="arbitrationPriority" value="1" />
@@ -2217,330 +2469,330 @@
  </connection>
  <connection
    kind="avalon_streaming"
-   version="15.0"
+   version="15.1"
    start="sys_ethernet.receive"
    end="sys_ethernet_dma_rx.st_sink" />
  <connection
    kind="avalon_streaming"
-   version="15.0"
+   version="15.1"
    start="sys_ethernet_dma_tx.st_source"
    end="sys_ethernet.transmit" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_ddr3_cntrl.emif_usr_clk"
    end="sys_mem_interconnect.clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_ddr3_cntrl.emif_usr_clk"
    end="mem_rst.clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_ddr3_cntrl.emif_usr_clk"
    end="mem_clk.in_clk" />
- <connection kind="clock" version="15.0" start="sys_clk.out_clk" end="sys_cpu.clk" />
- <connection kind="clock" version="15.0" start="sys_clk.out_clk" end="sys_rst.clk" />
+ <connection kind="clock" version="15.1" start="sys_clk.out_clk" end="sys_cpu.clk" />
+ <connection kind="clock" version="15.1" start="sys_clk.out_clk" end="sys_rst.clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
    end="sys_uart.clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
    end="sys_timer.clk" />
- <connection kind="clock" version="15.0" start="sys_clk.out_clk" end="sys_id.clk" />
+ <connection kind="clock" version="15.1" start="sys_clk.out_clk" end="sys_id.clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
    end="sys_gpio_bd.clk" />
- <connection kind="clock" version="15.0" start="sys_clk.out_clk" end="sys_spi.clk" />
+ <connection kind="clock" version="15.1" start="sys_clk.out_clk" end="sys_spi.clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
    end="sys_cpu_interconnect.clk" />
- <connection kind="clock" version="15.0" start="sys_clk.out_clk" end="sys_irq.clk" />
+ <connection kind="clock" version="15.1" start="sys_clk.out_clk" end="sys_irq.clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
    end="sys_ethernet_reset.clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
    end="sys_gpio_in.clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
    end="sys_gpio_out.clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
    end="sys_timer_2nd.clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
    end="sys_int_mem.clk1" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
    end="sys_tlb_mem.clk1" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
    end="sys_tlb_mem.clk2" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
    end="sys_ethernet_dma_rx.clock" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
    end="sys_ethernet_dma_tx.clock" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
    end="sys_ethernet.control_port_clock_connection" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
    end="sys_ethernet.receive_clock_connection" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
    end="sys_ethernet.transmit_clock_connection" />
  <connection
    kind="interrupt"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.irq"
    end="sys_ethernet_dma_rx.csr_irq">
   <parameter name="irqNumber" value="3" />
  </connection>
  <connection
    kind="interrupt"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.irq"
    end="sys_ethernet_dma_tx.csr_irq">
   <parameter name="irqNumber" value="1" />
  </connection>
  <connection
    kind="interrupt"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.irq"
    end="sys_uart.irq">
   <parameter name="irqNumber" value="2" />
  </connection>
  <connection
    kind="interrupt"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.irq"
    end="sys_timer.irq">
   <parameter name="irqNumber" value="0" />
  </connection>
- <connection kind="interrupt" version="15.0" start="sys_cpu.irq" end="sys_spi.irq">
+ <connection kind="interrupt" version="15.1" start="sys_cpu.irq" end="sys_spi.irq">
   <parameter name="irqNumber" value="4" />
  </connection>
  <connection
    kind="interrupt"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.irq"
    end="sys_gpio_bd.irq">
   <parameter name="irqNumber" value="5" />
  </connection>
  <connection
    kind="interrupt"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.irq"
    end="sys_gpio_in.irq">
   <parameter name="irqNumber" value="8" />
  </connection>
  <connection
    kind="interrupt"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.irq"
    end="sys_timer_2nd.irq">
   <parameter name="irqNumber" value="15" />
  </connection>
  <connection
    kind="interrupt"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.irq"
    end="sys_irq.sender0_irq">
   <parameter name="irqNumber" value="6" />
  </connection>
  <connection
    kind="interrupt"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.irq"
    end="sys_irq.sender1_irq">
   <parameter name="irqNumber" value="7" />
  </connection>
  <connection
    kind="interrupt"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.irq"
    end="sys_irq.sender2_irq">
   <parameter name="irqNumber" value="9" />
  </connection>
  <connection
    kind="interrupt"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.irq"
    end="sys_irq.sender3_irq">
   <parameter name="irqNumber" value="10" />
  </connection>
  <connection
    kind="interrupt"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.irq"
    end="sys_irq.sender4_irq">
   <parameter name="irqNumber" value="11" />
  </connection>
  <connection
    kind="interrupt"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.irq"
    end="sys_irq.sender5_irq">
   <parameter name="irqNumber" value="12" />
  </connection>
  <connection
    kind="interrupt"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.irq"
    end="sys_irq.sender6_irq">
   <parameter name="irqNumber" value="13" />
  </connection>
  <connection
    kind="interrupt"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.irq"
    end="sys_irq.sender7_irq">
   <parameter name="irqNumber" value="14" />
  </connection>
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_cpu.debug_reset_request"
    end="sys_cpu.reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_ddr3_cntrl.emif_usr_reset_n"
    end="mem_rst.in_reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_ddr3_cntrl.emif_usr_reset_n"
    end="sys_mem_interconnect.reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="sys_irq.clk_reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="sys_ddr3_cntrl.global_reset_n" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="sys_ethernet_reset.in_reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="sys_cpu.reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="sys_uart.reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="sys_timer.reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="sys_id.reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="sys_gpio_bd.reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="sys_spi.reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="sys_cpu_interconnect.reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="sys_gpio_in.reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="sys_gpio_out.reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="sys_timer_2nd.reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="sys_int_mem.reset1" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="sys_tlb_mem.reset1" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="sys_tlb_mem.reset2" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="sys_ethernet.reset_connection" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="sys_ethernet_dma_rx.reset_n" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="sys_ethernet_dma_tx.reset_n" />
  <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
diff --git a/projects/daq2/a10gx/system_bd.qsys b/projects/daq2/a10gx/system_bd.qsys
index 1a8f91dd9..9f991b1ec 100755
--- a/projects/daq2/a10gx/system_bd.qsys
+++ b/projects/daq2/a10gx/system_bd.qsys
@@ -9,14 +9,6 @@
    categories="System" />
  <parameter name="bonusData"><![CDATA[bonusData 
 {
-   element $${FILENAME}
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
    element a10gx_base
    {
       datum _sortIndex
@@ -445,11 +437,11 @@
   <parameter name="AUTO_UNIQUE_ID">$${FILENAME}_a10gx_base</parameter>
  </module>
  <module name="daq2" kind="daq2_bd" version="1.0" enabled="1">
-  <parameter name="AUTO_AXI_AD9144_DMA_M_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10gx_base_sys_ddr3_cntrl.ctrl_amm_0' start='0x0' end='0x10000000' /></address-map>]]></parameter>
+  <parameter name="AUTO_AXI_AD9144_DMA_M_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10gx_base_sys_ddr3_cntrl_arch.ctrl_amm_0' start='0x0' end='0x10000000' /></address-map>]]></parameter>
   <parameter
      name="AUTO_AXI_AD9144_DMA_M_AXI_ADDRESS_WIDTH"
      value="AddressWidth = 29" />
-  <parameter name="AUTO_AXI_AD9680_DMA_M_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10gx_base_sys_ddr3_cntrl.ctrl_amm_0' start='0x0' end='0x10000000' /></address-map>]]></parameter>
+  <parameter name="AUTO_AXI_AD9680_DMA_M_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10gx_base_sys_ddr3_cntrl_arch.ctrl_amm_0' start='0x0' end='0x10000000' /></address-map>]]></parameter>
   <parameter
      name="AUTO_AXI_AD9680_DMA_M_AXI_ADDRESS_WIDTH"
      value="AddressWidth = 29" />
@@ -471,7 +463,7 @@
   <parameter name="AUTO_TX_REF_CLK_RESET_DOMAIN" value="5" />
   <parameter name="AUTO_UNIQUE_ID" value="$${FILENAME}_daq2" />
  </module>
- <module name="sys_clk" kind="clock_source" version="15.0" enabled="1">
+ <module name="sys_clk" kind="clock_source" version="15.1" enabled="1">
   <parameter name="clockFrequency" value="100000000" />
   <parameter name="clockFrequencyKnown" value="true" />
   <parameter name="inputClockFrequency" value="0" />
@@ -479,7 +471,7 @@
  </module>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="daq2.axi_ad9144_dma_m_axi"
    end="a10gx_base.sys_mem_s_avl">
   <parameter name="arbitrationPriority" value="1" />
@@ -488,7 +480,7 @@
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="daq2.axi_ad9680_dma_m_axi"
    end="a10gx_base.sys_mem_s_avl">
   <parameter name="arbitrationPriority" value="1" />
@@ -497,7 +489,7 @@
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="a10gx_base.sys_cpu_m_avl"
    end="daq2.axi_ad9144_core_s_axi">
   <parameter name="arbitrationPriority" value="1" />
@@ -506,7 +498,7 @@
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="a10gx_base.sys_cpu_m_avl"
    end="daq2.axi_ad9144_dma_s_axi">
   <parameter name="arbitrationPriority" value="1" />
@@ -515,7 +507,7 @@
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="a10gx_base.sys_cpu_m_avl"
    end="daq2.axi_ad9680_core_s_axi">
   <parameter name="arbitrationPriority" value="1" />
@@ -524,7 +516,7 @@
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="a10gx_base.sys_cpu_m_avl"
    end="daq2.axi_ad9680_dma_s_axi">
   <parameter name="arbitrationPriority" value="1" />
@@ -533,7 +525,7 @@
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="a10gx_base.sys_cpu_m_avl"
    end="daq2.axi_jesd_xcvr_s_axi">
   <parameter name="arbitrationPriority" value="1" />
@@ -542,42 +534,42 @@
  </connection>
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.clk"
    end="a10gx_base.sys_clk" />
- <connection kind="clock" version="15.0" start="sys_clk.clk" end="daq2.sys_clk" />
+ <connection kind="clock" version="15.1" start="sys_clk.clk" end="daq2.sys_clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="a10gx_base.mem_clk"
    end="daq2.mem_clk" />
  <connection
    kind="interrupt"
-   version="15.0"
+   version="15.1"
    start="a10gx_base.sys_intr"
    end="daq2.axi_ad9144_dma_intr">
   <parameter name="irqNumber" value="1" />
  </connection>
  <connection
    kind="interrupt"
-   version="15.0"
+   version="15.1"
    start="a10gx_base.sys_intr"
    end="daq2.axi_ad9680_dma_intr">
   <parameter name="irqNumber" value="0" />
  </connection>
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_clk.clk_reset"
    end="a10gx_base.sys_rst" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_clk.clk_reset"
    end="daq2.sys_rst" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="a10gx_base.mem_rst"
    end="daq2.mem_rst" />
  <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
diff --git a/projects/daq2/a10gx/system_constr.sdc b/projects/daq2/a10gx/system_constr.sdc
index 86ef79f85..c55dd576c 100644
--- a/projects/daq2/a10gx/system_constr.sdc
+++ b/projects/daq2/a10gx/system_constr.sdc
@@ -14,3 +14,5 @@ set_false_path -from [get_clocks {sys_clk_100mhz}] -to [get_clocks {\
   i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_l_1 \
   i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_l_2}]
  
+set_false_path -from [get_clocks {sys_clk_100mhz}] -to [get_clocks {\
+  i_system_bd|a10gx_base|sys_ddr3_cntrl_core_nios_clk}]
\ No newline at end of file
diff --git a/projects/daq2/common/daq2_bd.qsys b/projects/daq2/common/daq2_bd.qsys
index 836c28c8e..6ead3df40 100755
--- a/projects/daq2/common/daq2_bd.qsys
+++ b/projects/daq2/common/daq2_bd.qsys
@@ -9,14 +9,6 @@
    categories="System" />
  <parameter name="bonusData"><![CDATA[bonusData 
 {
-   element $${FILENAME}
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Arria 10";
-         type = "String";
-      }
-   }
    element ad9680_adcfifo
    {
       datum _sortIndex
@@ -882,24 +874,24 @@
   <parameter name="RX_NUM_OF_LANES" value="4" />
   <parameter name="TX_NUM_OF_LANES" value="4" />
  </module>
- <module name="mem_clk" kind="altera_clock_bridge" version="15.0" enabled="1">
+ <module name="mem_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
   <parameter name="DERIVED_CLOCK_RATE" value="0" />
   <parameter name="EXPLICIT_CLOCK_RATE" value="125000000" />
   <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
  </module>
- <module name="mem_rst" kind="altera_reset_bridge" version="15.0" enabled="1">
+ <module name="mem_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
   <parameter name="ACTIVE_LOW_RESET" value="0" />
   <parameter name="AUTO_CLK_CLOCK_RATE" value="125000000" />
   <parameter name="NUM_RESET_OUTPUTS" value="1" />
   <parameter name="SYNCHRONOUS_EDGES" value="deassert" />
   <parameter name="USE_RESET_REQUEST" value="0" />
  </module>
- <module name="sys_clk" kind="altera_clock_bridge" version="15.0" enabled="1">
+ <module name="sys_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
   <parameter name="DERIVED_CLOCK_RATE" value="0" />
   <parameter name="EXPLICIT_CLOCK_RATE" value="100000000" />
   <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
  </module>
- <module name="sys_rst" kind="altera_reset_bridge" version="15.0" enabled="1">
+ <module name="sys_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
   <parameter name="ACTIVE_LOW_RESET" value="0" />
   <parameter name="AUTO_CLK_CLOCK_RATE" value="100000000" />
   <parameter name="NUM_RESET_OUTPUTS" value="1" />
@@ -914,7 +906,7 @@
   <parameter name="CHANNEL_DATA_WIDTH" value="64" />
   <parameter name="NUM_OF_CHANNELS" value="2" />
  </module>
- <module name="xcvr_core" kind="altera_jesd204" version="15.0" enabled="1">
+ <module name="xcvr_core" kind="altera_jesd204" version="15.1" enabled="1">
   <parameter name="ADJCNT" value="0" />
   <parameter name="ADJDIR" value="0" />
   <parameter name="AUTO_DEVICE" value="10AX115S3F45I2SGE2" />
@@ -927,6 +919,13 @@
   <parameter name="DID" value="0" />
   <parameter name="DLB_TEST" value="0" />
   <parameter name="ECC_EN" value="0" />
+  <parameter name="ED_DEV_KIT" value="NONE" />
+  <parameter name="ED_FILESET_SIM" value="false" />
+  <parameter name="ED_FILESET_SYNTH" value="false" />
+  <parameter name="ED_GENERIC_5SERIES" value="No" />
+  <parameter name="ED_GENERIC_A10" value="No" />
+  <parameter name="ED_HDL_FORMAT_SIM" value="VERILOG" />
+  <parameter name="ED_HDL_FORMAT_SYNTH" value="VERILOG" />
   <parameter name="GUI_CFG_F" value="1" />
   <parameter name="GUI_EN_CFG_F" value="true" />
   <parameter name="HD" value="1" />
@@ -973,7 +972,7 @@
  <module
    name="xcvr_rst_cntrl"
    kind="altera_xcvr_reset_control"
-   version="15.0"
+   version="15.1"
    enabled="1">
   <parameter name="CHANNELS" value="4" />
   <parameter name="PLLS" value="1" />
@@ -990,6 +989,7 @@
   <parameter name="T_PLL_POWERDOWN" value="1000" />
   <parameter name="T_RX_ANALOGRESET" value="40" />
   <parameter name="T_RX_DIGITALRESET" value="4000" />
+  <parameter name="T_TX_ANALOGRESET" value="0" />
   <parameter name="T_TX_DIGITALRESET" value="20" />
   <parameter name="device_family" value="Arria 10" />
   <parameter name="gui_pll_cal_busy" value="1" />
@@ -997,7 +997,7 @@
   <parameter name="gui_split_interfaces" value="0" />
   <parameter name="gui_tx_auto_reset" value="0" />
  </module>
- <module name="xcvr_rx_pll" kind="altera_iopll" version="15.0" enabled="1">
+ <module name="xcvr_rx_pll" kind="altera_iopll" version="15.1" enabled="1">
   <parameter name="gui_active_clk" value="false" />
   <parameter name="gui_actual_duty_cycle0" value="50.0" />
   <parameter name="gui_actual_duty_cycle1" value="50.0" />
@@ -1172,7 +1172,7 @@
   <parameter name="gui_en_adv_params" value="false" />
   <parameter name="gui_en_dps_ports" value="false" />
   <parameter name="gui_en_extclkout_ports" value="false" />
-  <parameter name="gui_en_lvds_ports" value="false" />
+  <parameter name="gui_en_lvds_ports" value="Disabled" />
   <parameter name="gui_en_phout_ports" value="false" />
   <parameter name="gui_en_reconf" value="false" />
   <parameter name="gui_enable_cascade_in" value="false" />
@@ -1272,7 +1272,9 @@
   <parameter name="gui_reference_clock_frequency" value="500.0" />
   <parameter name="gui_switchover_delay" value="0" />
   <parameter name="gui_switchover_mode">Automatic Switchover</parameter>
+  <parameter name="gui_use_NDFB_modes" value="false" />
   <parameter name="gui_use_locked" value="false" />
+  <parameter name="gui_vco_frequency" value="600.0" />
   <parameter name="system_info_device_component" value="10AX115S3F45I2SGE2" />
   <parameter name="system_info_device_family" value="Arria 10" />
   <parameter name="system_info_device_speed_grade" value="2" />
@@ -1281,7 +1283,7 @@
  <module
    name="xcvr_rx_ref_clk"
    kind="altera_clock_bridge"
-   version="15.0"
+   version="15.1"
    enabled="1">
   <parameter name="DERIVED_CLOCK_RATE" value="0" />
   <parameter name="EXPLICIT_CLOCK_RATE" value="500000000" />
@@ -1290,7 +1292,7 @@
  <module
    name="xcvr_tx_lane_pll"
    kind="altera_xcvr_atx_pll_a10"
-   version="15.0"
+   version="15.1"
    enabled="1">
   <parameter name="base_device" value="NIGHTFURY5ES2" />
   <parameter name="bw_sel" value="medium" />
@@ -1298,6 +1300,7 @@
   <parameter name="device_family" value="Arria 10" />
   <parameter name="enable_16G_path" value="0" />
   <parameter name="enable_8G_path" value="1" />
+  <parameter name="enable_analog_resets" value="0" />
   <parameter name="enable_atx_to_fpll_cascade_out" value="0" />
   <parameter name="enable_bonding_clks" value="1" />
   <parameter name="enable_cascade_out" value="0" />
@@ -1322,6 +1325,7 @@
   <parameter name="primary_pll_buffer">GX clock output buffer</parameter>
   <parameter name="prot_mode" value="Basic" />
   <parameter name="rcfg_debug" value="0" />
+  <parameter name="rcfg_enable_avmm_busy_port" value="0" />
   <parameter name="rcfg_file_prefix">altera_xcvr_atx_pll_a10</parameter>
   <parameter name="rcfg_h_file_enable" value="0" />
   <parameter name="rcfg_jtag_enable" value="0" />
@@ -1331,6 +1335,7 @@
   <parameter name="rcfg_param_vals2" value="" />
   <parameter name="rcfg_profile_cnt" value="2" />
   <parameter name="rcfg_profile_select" value="1" />
+  <parameter name="rcfg_separate_avmm_busy" value="0" />
   <parameter name="rcfg_sv_file_enable" value="0" />
   <parameter name="rcfg_txt_file_enable" value="0" />
   <parameter name="refclk_cnt" value="1" />
@@ -1344,6 +1349,7 @@
   <parameter name="set_hip_cal_en" value="0" />
   <parameter name="set_k_counter" value="1" />
   <parameter name="set_l_cascade_counter" value="4" />
+  <parameter name="set_l_cascade_predivider" value="1" />
   <parameter name="set_l_counter" value="4" />
   <parameter name="set_m_counter" value="50" />
   <parameter name="set_manual_reference_clock_frequency" value="100.0" />
@@ -1354,7 +1360,7 @@
   <parameter name="support_mode" value="user_mode" />
   <parameter name="test_mode" value="0" />
  </module>
- <module name="xcvr_tx_pll" kind="altera_iopll" version="15.0" enabled="1">
+ <module name="xcvr_tx_pll" kind="altera_iopll" version="15.1" enabled="1">
   <parameter name="gui_active_clk" value="false" />
   <parameter name="gui_actual_duty_cycle0" value="50.0" />
   <parameter name="gui_actual_duty_cycle1" value="50.0" />
@@ -1529,7 +1535,7 @@
   <parameter name="gui_en_adv_params" value="false" />
   <parameter name="gui_en_dps_ports" value="false" />
   <parameter name="gui_en_extclkout_ports" value="false" />
-  <parameter name="gui_en_lvds_ports" value="false" />
+  <parameter name="gui_en_lvds_ports" value="Disabled" />
   <parameter name="gui_en_phout_ports" value="false" />
   <parameter name="gui_en_reconf" value="false" />
   <parameter name="gui_enable_cascade_in" value="false" />
@@ -1629,7 +1635,9 @@
   <parameter name="gui_reference_clock_frequency" value="500.0" />
   <parameter name="gui_switchover_delay" value="0" />
   <parameter name="gui_switchover_mode">Automatic Switchover</parameter>
+  <parameter name="gui_use_NDFB_modes" value="false" />
   <parameter name="gui_use_locked" value="false" />
+  <parameter name="gui_vco_frequency" value="600.0" />
   <parameter name="system_info_device_component" value="10AX115S3F45I2SGE2" />
   <parameter name="system_info_device_family" value="Arria 10" />
   <parameter name="system_info_device_speed_grade" value="2" />
@@ -1638,7 +1646,7 @@
  <module
    name="xcvr_tx_ref_clk"
    kind="altera_clock_bridge"
-   version="15.0"
+   version="15.1"
    enabled="1">
   <parameter name="DERIVED_CLOCK_RATE" value="0" />
   <parameter name="EXPLICIT_CLOCK_RATE" value="500000000" />
@@ -1646,149 +1654,149 @@
  </module>
  <connection
    kind="avalon_streaming"
-   version="15.0"
+   version="15.1"
    start="axi_jesd_xcvr.if_tx_ip_avl"
    end="xcvr_core.jesd204_tx_link" />
  <connection
    kind="avalon_streaming"
-   version="15.0"
+   version="15.1"
    start="xcvr_core.jesd204_rx_link"
    end="axi_jesd_xcvr.if_rx_ip_avl" />
- <connection kind="clock" version="15.0" start="sys_clk.out_clk" end="sys_rst.clk" />
- <connection kind="clock" version="15.0" start="mem_clk.out_clk" end="mem_rst.clk" />
+ <connection kind="clock" version="15.1" start="sys_clk.out_clk" end="sys_rst.clk" />
+ <connection kind="clock" version="15.1" start="mem_clk.out_clk" end="mem_rst.clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
    end="xcvr_rst_cntrl.clock" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="mem_clk.out_clk"
    end="ad9680_adcfifo.if_dma_clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="mem_clk.out_clk"
    end="axi_ad9680_dma.if_s_axis_aclk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
    end="xcvr_core.jesd204_rx_avs_clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
    end="xcvr_core.jesd204_tx_avs_clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="mem_clk.out_clk"
    end="axi_ad9680_dma.m_dest_axi_clock" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="mem_clk.out_clk"
    end="axi_ad9144_dma.m_src_axi_clock" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="xcvr_tx_ref_clk.out_clk"
    end="xcvr_tx_lane_pll.pll_refclk0" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="xcvr_tx_ref_clk.out_clk"
    end="xcvr_tx_pll.refclk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="xcvr_rx_ref_clk.out_clk"
    end="xcvr_rx_pll.refclk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="xcvr_rx_ref_clk.out_clk"
    end="xcvr_core.rx_pll_ref_clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
    end="axi_ad9680_dma.s_axi_clock" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
    end="axi_ad9680_core.s_axi_clock" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
    end="axi_ad9144_core.s_axi_clock" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
    end="axi_jesd_xcvr.s_axi_clock" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
    end="axi_ad9144_dma.s_axi_clock" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="xcvr_rx_pll.outclk0"
    end="util_cpack_0.if_adc_clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="xcvr_rx_pll.outclk0"
    end="ad9680_adcfifo.if_adc_clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="xcvr_tx_pll.outclk0"
    end="util_upack_0.if_dac_clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="xcvr_tx_pll.outclk0"
    end="axi_ad9144_dma.if_fifo_rd_clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="xcvr_rx_pll.outclk0"
    end="axi_ad9680_core.if_rx_clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="xcvr_rx_pll.outclk0"
    end="axi_jesd_xcvr.if_rx_clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="xcvr_tx_pll.outclk0"
    end="axi_ad9144_core.if_tx_clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="xcvr_tx_pll.outclk0"
    end="axi_jesd_xcvr.if_tx_clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="xcvr_rx_pll.outclk0"
    end="xcvr_core.rxlink_clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="xcvr_tx_pll.outclk0"
    end="xcvr_core.txlink_clk" />
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="xcvr_core.alldev_lane_aligned"
    end="xcvr_core.dev_lane_aligned">
   <parameter name="endPort" value="" />
@@ -1799,7 +1807,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="axi_ad9680_core.fifo_ch_0"
    end="util_cpack_0.fifo_ch_0">
   <parameter name="endPort" value="" />
@@ -1810,7 +1818,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="util_cpack_0.fifo_ch_1"
    end="axi_ad9680_core.fifo_ch_1">
   <parameter name="endPort" value="" />
@@ -1821,7 +1829,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="util_cpack_0.if_adc_data"
    end="ad9680_adcfifo.if_adc_wdata">
   <parameter name="endPort" value="" />
@@ -1832,7 +1840,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="util_cpack_0.if_adc_valid"
    end="ad9680_adcfifo.if_adc_wr">
   <parameter name="endPort" value="" />
@@ -1843,7 +1851,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="util_upack_0.if_dac_valid"
    end="axi_ad9144_dma.if_fifo_rd_en">
   <parameter name="endPort" value="" />
@@ -1854,7 +1862,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="ad9680_adcfifo.if_dma_wdata"
    end="axi_ad9680_dma.if_s_axis_data">
   <parameter name="endPort" value="" />
@@ -1865,7 +1873,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="ad9680_adcfifo.if_dma_wr"
    end="axi_ad9680_dma.if_s_axis_valid">
   <parameter name="endPort" value="" />
@@ -1876,7 +1884,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="ad9680_adcfifo.if_dma_wready"
    end="axi_ad9680_dma.if_s_axis_ready">
   <parameter name="endPort" value="" />
@@ -1887,7 +1895,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="ad9680_adcfifo.if_dma_xfer_req"
    end="axi_ad9680_dma.if_s_axis_xfer_req">
   <parameter name="endPort" value="" />
@@ -1898,7 +1906,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="axi_ad9144_dma.if_fifo_rd_dout"
    end="util_upack_0.if_dac_data">
   <parameter name="endPort" value="" />
@@ -1909,7 +1917,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="axi_ad9680_core.if_rx_data"
    end="axi_jesd_xcvr.if_rx_data">
   <parameter name="endPort" value="" />
@@ -1920,7 +1928,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="axi_jesd_xcvr.if_rx_ip_sof"
    end="xcvr_core.rx_sof">
   <parameter name="endPort" value="" />
@@ -1931,7 +1939,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="axi_jesd_xcvr.if_rx_ip_sync"
    end="xcvr_core.rx_dev_sync_n">
   <parameter name="endPort" value="" />
@@ -1942,7 +1950,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="axi_jesd_xcvr.if_rx_ip_sysref"
    end="xcvr_core.rx_sysref">
   <parameter name="endPort" value="" />
@@ -1953,7 +1961,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="axi_jesd_xcvr.if_rx_ready"
    end="xcvr_rst_cntrl.rx_ready">
   <parameter name="endPort" value="" />
@@ -1964,7 +1972,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="axi_jesd_xcvr.if_tx_data"
    end="axi_ad9144_core.if_tx_data">
   <parameter name="endPort" value="" />
@@ -1975,7 +1983,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="axi_jesd_xcvr.if_tx_ip_sysref"
    end="xcvr_core.tx_sysref">
   <parameter name="endPort" value="" />
@@ -1986,7 +1994,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="axi_jesd_xcvr.if_tx_ready"
    end="xcvr_rst_cntrl.tx_ready">
   <parameter name="endPort" value="" />
@@ -1997,7 +2005,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="xcvr_rst_cntrl.pll_cal_busy"
    end="xcvr_tx_lane_pll.pll_cal_busy">
   <parameter name="endPort" value="" />
@@ -2008,7 +2016,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="xcvr_tx_lane_pll.pll_locked"
    end="xcvr_rst_cntrl.pll_locked">
   <parameter name="endPort" value="" />
@@ -2019,7 +2027,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="xcvr_tx_lane_pll.pll_powerdown"
    end="xcvr_rst_cntrl.pll_powerdown">
   <parameter name="endPort" value="" />
@@ -2030,7 +2038,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="xcvr_rst_cntrl.rx_analogreset"
    end="xcvr_core.rx_analogreset">
   <parameter name="endPort" value="" />
@@ -2041,7 +2049,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="xcvr_core.rx_cal_busy"
    end="xcvr_rst_cntrl.rx_cal_busy">
   <parameter name="endPort" value="" />
@@ -2052,7 +2060,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="xcvr_core.rx_digitalreset"
    end="xcvr_rst_cntrl.rx_digitalreset">
   <parameter name="endPort" value="" />
@@ -2063,7 +2071,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="xcvr_rst_cntrl.rx_is_lockedtodata"
    end="xcvr_core.rx_islockedtodata">
   <parameter name="endPort" value="" />
@@ -2074,7 +2082,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="xcvr_core.sync_n"
    end="axi_jesd_xcvr.if_tx_ip_sync">
   <parameter name="endPort" value="" />
@@ -2085,7 +2093,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="xcvr_rst_cntrl.tx_analogreset"
    end="xcvr_core.tx_analogreset">
   <parameter name="endPort" value="" />
@@ -2096,7 +2104,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="xcvr_rst_cntrl.tx_cal_busy"
    end="xcvr_core.tx_cal_busy">
   <parameter name="endPort" value="" />
@@ -2107,7 +2115,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="xcvr_core.tx_dev_sync_n"
    end="xcvr_core.mdev_sync_n">
   <parameter name="endPort" value="" />
@@ -2118,7 +2126,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="xcvr_rst_cntrl.tx_digitalreset"
    end="xcvr_core.tx_digitalreset">
   <parameter name="endPort" value="" />
@@ -2129,127 +2137,127 @@
  </connection>
  <connection
    kind="hssi_serial_clock"
-   version="15.0"
+   version="15.1"
    start="xcvr_tx_lane_pll.tx_serial_clk"
    end="xcvr_core.tx_serial_clk0_ch0" />
  <connection
    kind="hssi_serial_clock"
-   version="15.0"
+   version="15.1"
    start="xcvr_tx_lane_pll.tx_serial_clk"
    end="xcvr_core.tx_serial_clk0_ch1" />
  <connection
    kind="hssi_serial_clock"
-   version="15.0"
+   version="15.1"
    start="xcvr_tx_lane_pll.tx_serial_clk"
    end="xcvr_core.tx_serial_clk0_ch2" />
  <connection
    kind="hssi_serial_clock"
-   version="15.0"
+   version="15.1"
    start="xcvr_tx_lane_pll.tx_serial_clk"
    end="xcvr_core.tx_serial_clk0_ch3" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="axi_jesd_xcvr.if_rst"
    end="xcvr_tx_pll.reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="axi_jesd_xcvr.if_rst"
    end="xcvr_rx_pll.reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="axi_jesd_xcvr.if_rst"
    end="xcvr_rst_cntrl.reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="axi_jesd_xcvr.if_rx_rstn"
    end="xcvr_core.rxlink_rst_n" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="axi_jesd_xcvr.if_tx_rstn"
    end="xcvr_core.txlink_rst_n" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="util_cpack_0.if_adc_rst" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="mem_rst.out_reset"
    end="util_cpack_0.if_adc_rst" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="ad9680_adcfifo.if_adc_rst" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="mem_rst.out_reset"
    end="ad9680_adcfifo.if_adc_rst" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="xcvr_core.jesd204_rx_avs_rst_n" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="xcvr_core.jesd204_tx_avs_rst_n" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="mem_rst.out_reset"
    end="axi_ad9680_dma.m_dest_axi_reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="mem_rst.out_reset"
    end="axi_ad9144_dma.m_src_axi_reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="xcvr_rst_cntrl.reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="xcvr_tx_pll.reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="xcvr_rx_pll.reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="axi_jesd_xcvr.s_axi_reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="axi_ad9144_core.s_axi_reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="axi_ad9680_core.s_axi_reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="axi_ad9680_dma.s_axi_reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="axi_ad9144_dma.s_axi_reset" />
  <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />