zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

daq2: Updated a10gx project to quartus 15.1.1

main
Adrian Costina 2016-02-05 17:43:05 +02:00
parent 0d67af370f
commit ad9ecbbbb6
4 changed files with 535 additions and 281 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

548
projects/common/a10gx/a10gx_system_bd.qsys
View File

File diff suppressed because one or more lines are too long

44
projects/daq2/a10gx/system_bd.qsys
View File

@ -9,14 +9,6 @@
categories="System" />
<parameter name="bonusData"><![CDATA[bonusData
{
element $${FILENAME}
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element a10gx_base
{
datum _sortIndex
@ -445,11 +437,11 @@
<parameter name="AUTO_UNIQUE_ID">$${FILENAME}_a10gx_base</parameter>
</module>
<module name="daq2" kind="daq2_bd" version="1.0" enabled="1">
<parameter name="AUTO_AXI_AD9144_DMA_M_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10gx_base_sys_ddr3_cntrl.ctrl_amm_0' start='0x0' end='0x10000000' /></address-map>]]></parameter>
<parameter name="AUTO_AXI_AD9144_DMA_M_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10gx_base_sys_ddr3_cntrl_arch.ctrl_amm_0' start='0x0' end='0x10000000' /></address-map>]]></parameter>
<parameter
name="AUTO_AXI_AD9144_DMA_M_AXI_ADDRESS_WIDTH"
value="AddressWidth = 29" />
<parameter name="AUTO_AXI_AD9680_DMA_M_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10gx_base_sys_ddr3_cntrl.ctrl_amm_0' start='0x0' end='0x10000000' /></address-map>]]></parameter>
<parameter name="AUTO_AXI_AD9680_DMA_M_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10gx_base_sys_ddr3_cntrl_arch.ctrl_amm_0' start='0x0' end='0x10000000' /></address-map>]]></parameter>
<parameter
name="AUTO_AXI_AD9680_DMA_M_AXI_ADDRESS_WIDTH"
value="AddressWidth = 29" />
@ -471,7 +463,7 @@
<parameter name="AUTO_TX_REF_CLK_RESET_DOMAIN" value="5" />
<parameter name="AUTO_UNIQUE_ID" value="$${FILENAME}_daq2" />
</module>
<module name="sys_clk" kind="clock_source" version="15.0" enabled="1">
<module name="sys_clk" kind="clock_source" version="15.1" enabled="1">
<parameter name="clockFrequency" value="100000000" />
<parameter name="clockFrequencyKnown" value="true" />
<parameter name="inputClockFrequency" value="0" />
@ -479,7 +471,7 @@
</module>
<connection
kind="avalon"
version="15.0"
version="15.1"
start="daq2.axi_ad9144_dma_m_axi"
end="a10gx_base.sys_mem_s_avl">
<parameter name="arbitrationPriority" value="1" />
@ -488,7 +480,7 @@
</connection>
<connection
kind="avalon"
version="15.0"
version="15.1"
start="daq2.axi_ad9680_dma_m_axi"
end="a10gx_base.sys_mem_s_avl">
<parameter name="arbitrationPriority" value="1" />
@ -497,7 +489,7 @@
</connection>
<connection
kind="avalon"
version="15.0"
version="15.1"
start="a10gx_base.sys_cpu_m_avl"
end="daq2.axi_ad9144_core_s_axi">
<parameter name="arbitrationPriority" value="1" />
@ -506,7 +498,7 @@
</connection>
<connection
kind="avalon"
version="15.0"
version="15.1"
start="a10gx_base.sys_cpu_m_avl"
end="daq2.axi_ad9144_dma_s_axi">
<parameter name="arbitrationPriority" value="1" />
@ -515,7 +507,7 @@
</connection>
<connection
kind="avalon"
version="15.0"
version="15.1"
start="a10gx_base.sys_cpu_m_avl"
end="daq2.axi_ad9680_core_s_axi">
<parameter name="arbitrationPriority" value="1" />
@ -524,7 +516,7 @@
</connection>
<connection
kind="avalon"
version="15.0"
version="15.1"
start="a10gx_base.sys_cpu_m_avl"
end="daq2.axi_ad9680_dma_s_axi">
<parameter name="arbitrationPriority" value="1" />
@ -533,7 +525,7 @@
</connection>
<connection
kind="avalon"
version="15.0"
version="15.1"
start="a10gx_base.sys_cpu_m_avl"
end="daq2.axi_jesd_xcvr_s_axi">
<parameter name="arbitrationPriority" value="1" />
@ -542,42 +534,42 @@
</connection>
<connection
kind="clock"
version="15.0"
version="15.1"
start="sys_clk.clk"
end="a10gx_base.sys_clk" />
<connection kind="clock" version="15.0" start="sys_clk.clk" end="daq2.sys_clk" />
<connection kind="clock" version="15.1" start="sys_clk.clk" end="daq2.sys_clk" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="a10gx_base.mem_clk"
end="daq2.mem_clk" />
<connection
kind="interrupt"
version="15.0"
version="15.1"
start="a10gx_base.sys_intr"
end="daq2.axi_ad9144_dma_intr">
<parameter name="irqNumber" value="1" />
</connection>
<connection
kind="interrupt"
version="15.0"
version="15.1"
start="a10gx_base.sys_intr"
end="daq2.axi_ad9680_dma_intr">
<parameter name="irqNumber" value="0" />
</connection>
<connection
kind="reset"
version="15.0"
version="15.1"
start="sys_clk.clk_reset"
end="a10gx_base.sys_rst" />
<connection
kind="reset"
version="15.0"
version="15.1"
start="sys_clk.clk_reset"
end="daq2.sys_rst" />
<connection
kind="reset"
version="15.0"
version="15.1"
start="a10gx_base.mem_rst"
end="daq2.mem_rst" />
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />

2
projects/daq2/a10gx/system_constr.sdc
View File

@ -14,3 +14,5 @@ set_false_path -from [get_clocks {sys_clk_100mhz}] -to [get_clocks {\
i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_l_1 \
i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_l_2}]
set_false_path -from [get_clocks {sys_clk_100mhz}] -to [get_clocks {\
i_system_bd|a10gx_base|sys_ddr3_cntrl_core_nios_clk}]

222
projects/daq2/common/daq2_bd.qsys
View File

@ -9,14 +9,6 @@
categories="System" />
<parameter name="bonusData"><![CDATA[bonusData
{
element $${FILENAME}
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element ad9680_adcfifo
{
datum _sortIndex
@ -882,24 +874,24 @@
<parameter name="RX_NUM_OF_LANES" value="4" />
<parameter name="TX_NUM_OF_LANES" value="4" />
</module>
<module name="mem_clk" kind="altera_clock_bridge" version="15.0" enabled="1">
<module name="mem_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
<parameter name="DERIVED_CLOCK_RATE" value="0" />
<parameter name="EXPLICIT_CLOCK_RATE" value="125000000" />
<parameter name="NUM_CLOCK_OUTPUTS" value="1" />
</module>
<module name="mem_rst" kind="altera_reset_bridge" version="15.0" enabled="1">
<module name="mem_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
<parameter name="ACTIVE_LOW_RESET" value="0" />
<parameter name="AUTO_CLK_CLOCK_RATE" value="125000000" />
<parameter name="NUM_RESET_OUTPUTS" value="1" />
<parameter name="SYNCHRONOUS_EDGES" value="deassert" />
<parameter name="USE_RESET_REQUEST" value="0" />
</module>
<module name="sys_clk" kind="altera_clock_bridge" version="15.0" enabled="1">
<module name="sys_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
<parameter name="DERIVED_CLOCK_RATE" value="0" />
<parameter name="EXPLICIT_CLOCK_RATE" value="100000000" />
<parameter name="NUM_CLOCK_OUTPUTS" value="1" />
</module>
<module name="sys_rst" kind="altera_reset_bridge" version="15.0" enabled="1">
<module name="sys_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
<parameter name="ACTIVE_LOW_RESET" value="0" />
<parameter name="AUTO_CLK_CLOCK_RATE" value="100000000" />
<parameter name="NUM_RESET_OUTPUTS" value="1" />
@ -914,7 +906,7 @@
<parameter name="CHANNEL_DATA_WIDTH" value="64" />
<parameter name="NUM_OF_CHANNELS" value="2" />
</module>
<module name="xcvr_core" kind="altera_jesd204" version="15.0" enabled="1">
<module name="xcvr_core" kind="altera_jesd204" version="15.1" enabled="1">
<parameter name="ADJCNT" value="0" />
<parameter name="ADJDIR" value="0" />
<parameter name="AUTO_DEVICE" value="10AX115S3F45I2SGE2" />
@ -927,6 +919,13 @@
<parameter name="DID" value="0" />
<parameter name="DLB_TEST" value="0" />
<parameter name="ECC_EN" value="0" />
<parameter name="ED_DEV_KIT" value="NONE" />
<parameter name="ED_FILESET_SIM" value="false" />
<parameter name="ED_FILESET_SYNTH" value="false" />
<parameter name="ED_GENERIC_5SERIES" value="No" />
<parameter name="ED_GENERIC_A10" value="No" />
<parameter name="ED_HDL_FORMAT_SIM" value="VERILOG" />
<parameter name="ED_HDL_FORMAT_SYNTH" value="VERILOG" />
<parameter name="GUI_CFG_F" value="1" />
<parameter name="GUI_EN_CFG_F" value="true" />
<parameter name="HD" value="1" />
@ -973,7 +972,7 @@
<module
name="xcvr_rst_cntrl"
kind="altera_xcvr_reset_control"
version="15.0"
version="15.1"
enabled="1">
<parameter name="CHANNELS" value="4" />
<parameter name="PLLS" value="1" />
@ -990,6 +989,7 @@
<parameter name="T_PLL_POWERDOWN" value="1000" />
<parameter name="T_RX_ANALOGRESET" value="40" />
<parameter name="T_RX_DIGITALRESET" value="4000" />
<parameter name="T_TX_ANALOGRESET" value="0" />
<parameter name="T_TX_DIGITALRESET" value="20" />
<parameter name="device_family" value="Arria 10" />
<parameter name="gui_pll_cal_busy" value="1" />
@ -997,7 +997,7 @@
<parameter name="gui_split_interfaces" value="0" />
<parameter name="gui_tx_auto_reset" value="0" />
</module>
<module name="xcvr_rx_pll" kind="altera_iopll" version="15.0" enabled="1">
<module name="xcvr_rx_pll" kind="altera_iopll" version="15.1" enabled="1">
<parameter name="gui_active_clk" value="false" />
<parameter name="gui_actual_duty_cycle0" value="50.0" />
<parameter name="gui_actual_duty_cycle1" value="50.0" />
@ -1172,7 +1172,7 @@
<parameter name="gui_en_adv_params" value="false" />
<parameter name="gui_en_dps_ports" value="false" />
<parameter name="gui_en_extclkout_ports" value="false" />
<parameter name="gui_en_lvds_ports" value="false" />
<parameter name="gui_en_lvds_ports" value="Disabled" />
<parameter name="gui_en_phout_ports" value="false" />
<parameter name="gui_en_reconf" value="false" />
<parameter name="gui_enable_cascade_in" value="false" />
@ -1272,7 +1272,9 @@
<parameter name="gui_reference_clock_frequency" value="500.0" />
<parameter name="gui_switchover_delay" value="0" />
<parameter name="gui_switchover_mode">Automatic Switchover</parameter>
<parameter name="gui_use_NDFB_modes" value="false" />
<parameter name="gui_use_locked" value="false" />
<parameter name="gui_vco_frequency" value="600.0" />
<parameter name="system_info_device_component" value="10AX115S3F45I2SGE2" />
<parameter name="system_info_device_family" value="Arria 10" />
<parameter name="system_info_device_speed_grade" value="2" />
@ -1281,7 +1283,7 @@
<module
name="xcvr_rx_ref_clk"
kind="altera_clock_bridge"
version="15.0"
version="15.1"
enabled="1">
<parameter name="DERIVED_CLOCK_RATE" value="0" />
<parameter name="EXPLICIT_CLOCK_RATE" value="500000000" />
@ -1290,7 +1292,7 @@
<module
name="xcvr_tx_lane_pll"
kind="altera_xcvr_atx_pll_a10"
version="15.0"
version="15.1"
enabled="1">
<parameter name="base_device" value="NIGHTFURY5ES2" />
<parameter name="bw_sel" value="medium" />
@ -1298,6 +1300,7 @@
<parameter name="device_family" value="Arria 10" />
<parameter name="enable_16G_path" value="0" />
<parameter name="enable_8G_path" value="1" />
<parameter name="enable_analog_resets" value="0" />
<parameter name="enable_atx_to_fpll_cascade_out" value="0" />
<parameter name="enable_bonding_clks" value="1" />
<parameter name="enable_cascade_out" value="0" />
@ -1322,6 +1325,7 @@
<parameter name="primary_pll_buffer">GX clock output buffer</parameter>
<parameter name="prot_mode" value="Basic" />
<parameter name="rcfg_debug" value="0" />
<parameter name="rcfg_enable_avmm_busy_port" value="0" />
<parameter name="rcfg_file_prefix">altera_xcvr_atx_pll_a10</parameter>
<parameter name="rcfg_h_file_enable" value="0" />
<parameter name="rcfg_jtag_enable" value="0" />
@ -1331,6 +1335,7 @@
<parameter name="rcfg_param_vals2" value="" />
<parameter name="rcfg_profile_cnt" value="2" />
<parameter name="rcfg_profile_select" value="1" />
<parameter name="rcfg_separate_avmm_busy" value="0" />
<parameter name="rcfg_sv_file_enable" value="0" />
<parameter name="rcfg_txt_file_enable" value="0" />
<parameter name="refclk_cnt" value="1" />
@ -1344,6 +1349,7 @@
<parameter name="set_hip_cal_en" value="0" />
<parameter name="set_k_counter" value="1" />
<parameter name="set_l_cascade_counter" value="4" />
<parameter name="set_l_cascade_predivider" value="1" />
<parameter name="set_l_counter" value="4" />
<parameter name="set_m_counter" value="50" />
<parameter name="set_manual_reference_clock_frequency" value="100.0" />
@ -1354,7 +1360,7 @@
<parameter name="support_mode" value="user_mode" />
<parameter name="test_mode" value="0" />
</module>
<module name="xcvr_tx_pll" kind="altera_iopll" version="15.0" enabled="1">
<module name="xcvr_tx_pll" kind="altera_iopll" version="15.1" enabled="1">
<parameter name="gui_active_clk" value="false" />
<parameter name="gui_actual_duty_cycle0" value="50.0" />
<parameter name="gui_actual_duty_cycle1" value="50.0" />
@ -1529,7 +1535,7 @@
<parameter name="gui_en_adv_params" value="false" />
<parameter name="gui_en_dps_ports" value="false" />
<parameter name="gui_en_extclkout_ports" value="false" />
<parameter name="gui_en_lvds_ports" value="false" />
<parameter name="gui_en_lvds_ports" value="Disabled" />
<parameter name="gui_en_phout_ports" value="false" />
<parameter name="gui_en_reconf" value="false" />
<parameter name="gui_enable_cascade_in" value="false" />
@ -1629,7 +1635,9 @@
<parameter name="gui_reference_clock_frequency" value="500.0" />
<parameter name="gui_switchover_delay" value="0" />
<parameter name="gui_switchover_mode">Automatic Switchover</parameter>
<parameter name="gui_use_NDFB_modes" value="false" />
<parameter name="gui_use_locked" value="false" />
<parameter name="gui_vco_frequency" value="600.0" />
<parameter name="system_info_device_component" value="10AX115S3F45I2SGE2" />
<parameter name="system_info_device_family" value="Arria 10" />
<parameter name="system_info_device_speed_grade" value="2" />
@ -1638,7 +1646,7 @@
<module
name="xcvr_tx_ref_clk"
kind="altera_clock_bridge"
version="15.0"
version="15.1"
enabled="1">
<parameter name="DERIVED_CLOCK_RATE" value="0" />
<parameter name="EXPLICIT_CLOCK_RATE" value="500000000" />
@ -1646,149 +1654,149 @@
</module>
<connection
kind="avalon_streaming"
version="15.0"
version="15.1"
start="axi_jesd_xcvr.if_tx_ip_avl"
end="xcvr_core.jesd204_tx_link" />
<connection
kind="avalon_streaming"
version="15.0"
version="15.1"
start="xcvr_core.jesd204_rx_link"
end="axi_jesd_xcvr.if_rx_ip_avl" />
<connection kind="clock" version="15.0" start="sys_clk.out_clk" end="sys_rst.clk" />
<connection kind="clock" version="15.0" start="mem_clk.out_clk" end="mem_rst.clk" />
<connection kind="clock" version="15.1" start="sys_clk.out_clk" end="sys_rst.clk" />
<connection kind="clock" version="15.1" start="mem_clk.out_clk" end="mem_rst.clk" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="sys_clk.out_clk"
end="xcvr_rst_cntrl.clock" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="mem_clk.out_clk"
end="ad9680_adcfifo.if_dma_clk" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="mem_clk.out_clk"
end="axi_ad9680_dma.if_s_axis_aclk" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="sys_clk.out_clk"
end="xcvr_core.jesd204_rx_avs_clk" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="sys_clk.out_clk"
end="xcvr_core.jesd204_tx_avs_clk" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="mem_clk.out_clk"
end="axi_ad9680_dma.m_dest_axi_clock" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="mem_clk.out_clk"
end="axi_ad9144_dma.m_src_axi_clock" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="xcvr_tx_ref_clk.out_clk"
end="xcvr_tx_lane_pll.pll_refclk0" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="xcvr_tx_ref_clk.out_clk"
end="xcvr_tx_pll.refclk" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="xcvr_rx_ref_clk.out_clk"
end="xcvr_rx_pll.refclk" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="xcvr_rx_ref_clk.out_clk"
end="xcvr_core.rx_pll_ref_clk" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="sys_clk.out_clk"
end="axi_ad9680_dma.s_axi_clock" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="sys_clk.out_clk"
end="axi_ad9680_core.s_axi_clock" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="sys_clk.out_clk"
end="axi_ad9144_core.s_axi_clock" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="sys_clk.out_clk"
end="axi_jesd_xcvr.s_axi_clock" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="sys_clk.out_clk"
end="axi_ad9144_dma.s_axi_clock" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="xcvr_rx_pll.outclk0"
end="util_cpack_0.if_adc_clk" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="xcvr_rx_pll.outclk0"
end="ad9680_adcfifo.if_adc_clk" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="xcvr_tx_pll.outclk0"
end="util_upack_0.if_dac_clk" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="xcvr_tx_pll.outclk0"
end="axi_ad9144_dma.if_fifo_rd_clk" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="xcvr_rx_pll.outclk0"
end="axi_ad9680_core.if_rx_clk" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="xcvr_rx_pll.outclk0"
end="axi_jesd_xcvr.if_rx_clk" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="xcvr_tx_pll.outclk0"
end="axi_ad9144_core.if_tx_clk" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="xcvr_tx_pll.outclk0"
end="axi_jesd_xcvr.if_tx_clk" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="xcvr_rx_pll.outclk0"
end="xcvr_core.rxlink_clk" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="xcvr_tx_pll.outclk0"
end="xcvr_core.txlink_clk" />
<connection
kind="conduit"
version="15.0"
version="15.1"
start="xcvr_core.alldev_lane_aligned"
end="xcvr_core.dev_lane_aligned">
<parameter name="endPort" value="" />
@ -1799,7 +1807,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="axi_ad9680_core.fifo_ch_0"
end="util_cpack_0.fifo_ch_0">
<parameter name="endPort" value="" />
@ -1810,7 +1818,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="util_cpack_0.fifo_ch_1"
end="axi_ad9680_core.fifo_ch_1">
<parameter name="endPort" value="" />
@ -1821,7 +1829,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="util_cpack_0.if_adc_data"
end="ad9680_adcfifo.if_adc_wdata">
<parameter name="endPort" value="" />
@ -1832,7 +1840,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="util_cpack_0.if_adc_valid"
end="ad9680_adcfifo.if_adc_wr">
<parameter name="endPort" value="" />
@ -1843,7 +1851,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="util_upack_0.if_dac_valid"
end="axi_ad9144_dma.if_fifo_rd_en">
<parameter name="endPort" value="" />
@ -1854,7 +1862,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="ad9680_adcfifo.if_dma_wdata"
end="axi_ad9680_dma.if_s_axis_data">
<parameter name="endPort" value="" />
@ -1865,7 +1873,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="ad9680_adcfifo.if_dma_wr"
end="axi_ad9680_dma.if_s_axis_valid">
<parameter name="endPort" value="" />
@ -1876,7 +1884,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="ad9680_adcfifo.if_dma_wready"
end="axi_ad9680_dma.if_s_axis_ready">
<parameter name="endPort" value="" />
@ -1887,7 +1895,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="ad9680_adcfifo.if_dma_xfer_req"
end="axi_ad9680_dma.if_s_axis_xfer_req">
<parameter name="endPort" value="" />
@ -1898,7 +1906,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="axi_ad9144_dma.if_fifo_rd_dout"
end="util_upack_0.if_dac_data">
<parameter name="endPort" value="" />
@ -1909,7 +1917,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="axi_ad9680_core.if_rx_data"
end="axi_jesd_xcvr.if_rx_data">
<parameter name="endPort" value="" />
@ -1920,7 +1928,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="axi_jesd_xcvr.if_rx_ip_sof"
end="xcvr_core.rx_sof">
<parameter name="endPort" value="" />
@ -1931,7 +1939,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="axi_jesd_xcvr.if_rx_ip_sync"
end="xcvr_core.rx_dev_sync_n">
<parameter name="endPort" value="" />
@ -1942,7 +1950,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="axi_jesd_xcvr.if_rx_ip_sysref"
end="xcvr_core.rx_sysref">
<parameter name="endPort" value="" />
@ -1953,7 +1961,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="axi_jesd_xcvr.if_rx_ready"
end="xcvr_rst_cntrl.rx_ready">
<parameter name="endPort" value="" />
@ -1964,7 +1972,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="axi_jesd_xcvr.if_tx_data"
end="axi_ad9144_core.if_tx_data">
<parameter name="endPort" value="" />
@ -1975,7 +1983,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="axi_jesd_xcvr.if_tx_ip_sysref"
end="xcvr_core.tx_sysref">
<parameter name="endPort" value="" />
@ -1986,7 +1994,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="axi_jesd_xcvr.if_tx_ready"
end="xcvr_rst_cntrl.tx_ready">
<parameter name="endPort" value="" />
@ -1997,7 +2005,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="xcvr_rst_cntrl.pll_cal_busy"
end="xcvr_tx_lane_pll.pll_cal_busy">
<parameter name="endPort" value="" />
@ -2008,7 +2016,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="xcvr_tx_lane_pll.pll_locked"
end="xcvr_rst_cntrl.pll_locked">
<parameter name="endPort" value="" />
@ -2019,7 +2027,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="xcvr_tx_lane_pll.pll_powerdown"
end="xcvr_rst_cntrl.pll_powerdown">
<parameter name="endPort" value="" />
@ -2030,7 +2038,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="xcvr_rst_cntrl.rx_analogreset"
end="xcvr_core.rx_analogreset">
<parameter name="endPort" value="" />
@ -2041,7 +2049,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="xcvr_core.rx_cal_busy"
end="xcvr_rst_cntrl.rx_cal_busy">
<parameter name="endPort" value="" />
@ -2052,7 +2060,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="xcvr_core.rx_digitalreset"
end="xcvr_rst_cntrl.rx_digitalreset">
<parameter name="endPort" value="" />
@ -2063,7 +2071,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="xcvr_rst_cntrl.rx_is_lockedtodata"
end="xcvr_core.rx_islockedtodata">
<parameter name="endPort" value="" />
@ -2074,7 +2082,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="xcvr_core.sync_n"
end="axi_jesd_xcvr.if_tx_ip_sync">
<parameter name="endPort" value="" />
@ -2085,7 +2093,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="xcvr_rst_cntrl.tx_analogreset"
end="xcvr_core.tx_analogreset">
<parameter name="endPort" value="" />
@ -2096,7 +2104,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="xcvr_rst_cntrl.tx_cal_busy"
end="xcvr_core.tx_cal_busy">
<parameter name="endPort" value="" />
@ -2107,7 +2115,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="xcvr_core.tx_dev_sync_n"
end="xcvr_core.mdev_sync_n">
<parameter name="endPort" value="" />
@ -2118,7 +2126,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="xcvr_rst_cntrl.tx_digitalreset"
end="xcvr_core.tx_digitalreset">
<parameter name="endPort" value="" />
@ -2129,127 +2137,127 @@
</connection>
<connection
kind="hssi_serial_clock"
version="15.0"
version="15.1"
start="xcvr_tx_lane_pll.tx_serial_clk"
end="xcvr_core.tx_serial_clk0_ch0" />
<connection
kind="hssi_serial_clock"
version="15.0"
version="15.1"
start="xcvr_tx_lane_pll.tx_serial_clk"
end="xcvr_core.tx_serial_clk0_ch1" />
<connection
kind="hssi_serial_clock"
version="15.0"
version="15.1"
start="xcvr_tx_lane_pll.tx_serial_clk"
end="xcvr_core.tx_serial_clk0_ch2" />
<connection
kind="hssi_serial_clock"
version="15.0"
version="15.1"
start="xcvr_tx_lane_pll.tx_serial_clk"
end="xcvr_core.tx_serial_clk0_ch3" />
<connection
kind="reset"
version="15.0"
version="15.1"
start="axi_jesd_xcvr.if_rst"
end="xcvr_tx_pll.reset" />
<connection
kind="reset"
version="15.0"
version="15.1"
start="axi_jesd_xcvr.if_rst"
end="xcvr_rx_pll.reset" />
<connection
kind="reset"
version="15.0"
version="15.1"
start="axi_jesd_xcvr.if_rst"
end="xcvr_rst_cntrl.reset" />
<connection
kind="reset"
version="15.0"
version="15.1"
start="axi_jesd_xcvr.if_rx_rstn"
end="xcvr_core.rxlink_rst_n" />
<connection
kind="reset"
version="15.0"
version="15.1"
start="axi_jesd_xcvr.if_tx_rstn"
end="xcvr_core.txlink_rst_n" />
<connection
kind="reset"
version="15.0"
version="15.1"
start="sys_rst.out_reset"
end="util_cpack_0.if_adc_rst" />
<connection
kind="reset"
version="15.0"
version="15.1"
start="mem_rst.out_reset"
end="util_cpack_0.if_adc_rst" />
<connection
kind="reset"
version="15.0"
version="15.1"
start="sys_rst.out_reset"
end="ad9680_adcfifo.if_adc_rst" />
<connection
kind="reset"
version="15.0"
version="15.1"
start="mem_rst.out_reset"
end="ad9680_adcfifo.if_adc_rst" />
<connection
kind="reset"
version="15.0"
version="15.1"
start="sys_rst.out_reset"
end="xcvr_core.jesd204_rx_avs_rst_n" />
<connection
kind="reset"
version="15.0"
version="15.1"
start="sys_rst.out_reset"
end="xcvr_core.jesd204_tx_avs_rst_n" />
<connection
kind="reset"
version="15.0"
version="15.1"
start="mem_rst.out_reset"
end="axi_ad9680_dma.m_dest_axi_reset" />
<connection
kind="reset"
version="15.0"
version="15.1"
start="mem_rst.out_reset"
end="axi_ad9144_dma.m_src_axi_reset" />
<connection
kind="reset"
version="15.0"
version="15.1"
start="sys_rst.out_reset"
end="xcvr_rst_cntrl.reset" />
<connection
kind="reset"
version="15.0"
version="15.1"
start="sys_rst.out_reset"
end="xcvr_tx_pll.reset" />
<connection
kind="reset"
version="15.0"
version="15.1"
start="sys_rst.out_reset"
end="xcvr_rx_pll.reset" />
<connection
kind="reset"
version="15.0"
version="15.1"
start="sys_rst.out_reset"
end="axi_jesd_xcvr.s_axi_reset" />
<connection
kind="reset"
version="15.0"
version="15.1"
start="sys_rst.out_reset"
end="axi_ad9144_core.s_axi_reset" />
<connection
kind="reset"
version="15.0"
version="15.1"
start="sys_rst.out_reset"
end="axi_ad9680_core.s_axi_reset" />
<connection
kind="reset"
version="15.0"
version="15.1"
start="sys_rst.out_reset"
end="axi_ad9680_dma.s_axi_reset" />
<connection
kind="reset"
version="15.0"
version="15.1"
start="sys_rst.out_reset"
end="axi_ad9144_dma.s_axi_reset" />
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />