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fmcomms1: modified *_bd.tcl files formatting

main
Adrian Costina 2014-03-26 12:05:42 +02:00
parent ca7a70650d
commit ad5ef35b48
5 changed files with 202 additions and 204 deletions
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16
projects/fmcomms1/common/fmcomms1_bd.tcl
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@ -86,6 +86,12 @@ if {$sys_zynq == 1} {
set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {125.0}] $sys_ps7 set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {125.0}] $sys_ps7
} }
if {$sys_zynq == 0} {
delete_bd_objs [get_bd_nets sys_concat_intc_din_2] [get_bd_ports unc_int1]
delete_bd_objs [get_bd_nets sys_concat_intc_din_3] [get_bd_ports unc_int2]
}
# reference clock shared with audio clock # reference clock shared with audio clock
# foro microblaze based system, add an additional clock to use with the ILA fifo # foro microblaze based system, add an additional clock to use with the ILA fifo
@ -114,11 +120,7 @@ connect_bd_net -net axi_ad9122_dac_data_out_n [get_bd_ports dac_data_out_n]
connect_bd_net -net axi_ad9122_dac_drd [get_bd_pins axi_ad9122/dac_drd] [get_bd_pins axi_ad9122_dma/fifo_rd_en] connect_bd_net -net axi_ad9122_dac_drd [get_bd_pins axi_ad9122/dac_drd] [get_bd_pins axi_ad9122_dma/fifo_rd_en]
connect_bd_net -net axi_ad9122_dac_ddata [get_bd_pins axi_ad9122/dac_ddata_64] [get_bd_pins axi_ad9122_dma/fifo_rd_dout] connect_bd_net -net axi_ad9122_dac_ddata [get_bd_pins axi_ad9122/dac_ddata_64] [get_bd_pins axi_ad9122_dma/fifo_rd_dout]
connect_bd_net -net axi_ad9122_dac_dunf [get_bd_pins axi_ad9122/dac_dunf] [get_bd_pins axi_ad9122_dma/fifo_rd_underflow] connect_bd_net -net axi_ad9122_dac_dunf [get_bd_pins axi_ad9122/dac_dunf] [get_bd_pins axi_ad9122_dma/fifo_rd_underflow]
if {$sys_zynq == 0 } {
connect_bd_net -net axi_ad9122_dma_irq [get_bd_pins axi_ad9122_dma/irq] [get_bd_pins sys_concat_intc/In6]
} else {
connect_bd_net -net axi_ad9122_dma_irq [get_bd_pins axi_ad9122_dma/irq] [get_bd_pins sys_concat_intc/In3] connect_bd_net -net axi_ad9122_dma_irq [get_bd_pins axi_ad9122_dma/irq] [get_bd_pins sys_concat_intc/In3]
}
# connections (adc) # connections (adc)
@ -143,11 +145,7 @@ connect_bd_net -net axi_ad9643_adc_dovf [get_bd_pins axi_ad9643/adc_dovf
connect_bd_net -net axi_ad9643_dma_dwr [get_bd_pins sys_ad9643_util_wfifo/s_wr] [get_bd_pins axi_ad9643_dma/fifo_wr_en] connect_bd_net -net axi_ad9643_dma_dwr [get_bd_pins sys_ad9643_util_wfifo/s_wr] [get_bd_pins axi_ad9643_dma/fifo_wr_en]
connect_bd_net -net axi_ad9643_dma_ddata [get_bd_pins sys_ad9643_util_wfifo/s_wdata] [get_bd_pins axi_ad9643_dma/fifo_wr_din] connect_bd_net -net axi_ad9643_dma_ddata [get_bd_pins sys_ad9643_util_wfifo/s_wdata] [get_bd_pins axi_ad9643_dma/fifo_wr_din]
connect_bd_net -net axi_ad9643_dma_dovf [get_bd_pins sys_ad9643_util_wfifo/s_wovf] [get_bd_pins axi_ad9643_dma/fifo_wr_overflow] connect_bd_net -net axi_ad9643_dma_dovf [get_bd_pins sys_ad9643_util_wfifo/s_wovf] [get_bd_pins axi_ad9643_dma/fifo_wr_overflow]
if {$sys_zynq == 0} {
connect_bd_net -net axi_ad9643_dma_irq [get_bd_pins axi_ad9643_dma/irq] [get_bd_pins sys_concat_intc/In5]
} else {
connect_bd_net -net axi_ad9643_dma_irq [get_bd_pins axi_ad9643_dma/irq] [get_bd_pins sys_concat_intc/In2] connect_bd_net -net axi_ad9643_dma_irq [get_bd_pins axi_ad9643_dma/irq] [get_bd_pins sys_concat_intc/In2]
}
connect_bd_net -net axi_ad9643_fifo_rst [get_bd_pins sys_ad9643_util_wfifo/fifo_rst] [get_bd_pins sys_ad9643_fifo/rst] connect_bd_net -net axi_ad9643_fifo_rst [get_bd_pins sys_ad9643_util_wfifo/fifo_rst] [get_bd_pins sys_ad9643_fifo/rst]
connect_bd_net -net axi_ad9643_fifo_wr [get_bd_pins sys_ad9643_util_wfifo/fifo_wr] [get_bd_pins sys_ad9643_fifo/wr_en] connect_bd_net -net axi_ad9643_fifo_wr [get_bd_pins sys_ad9643_util_wfifo/fifo_wr] [get_bd_pins sys_ad9643_fifo/wr_en]
@ -271,8 +269,8 @@ connect_bd_net -net fmcomms1_ref_clk [get_bd_pins sys_audio_clkgen/clk_out2] [ge
# address map # address map
create_bd_addr_seg -range 0x00010000 -offset 0x74200000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9122/s_axi/axi_lite] SEG_data_ad9122 create_bd_addr_seg -range 0x00010000 -offset 0x74200000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9122/s_axi/axi_lite] SEG_data_ad9122
create_bd_addr_seg -range 0x00010000 -offset 0x7c400000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9643_dma/s_axi/axi_lite] SEG_data_ad9122_dma
create_bd_addr_seg -range 0x00010000 -offset 0x79020000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9643/s_axi/axi_lite] SEG_data_ad9643 create_bd_addr_seg -range 0x00010000 -offset 0x79020000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9643/s_axi/axi_lite] SEG_data_ad9643
create_bd_addr_seg -range 0x00010000 -offset 0x7c400000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9643_dma/s_axi/axi_lite] SEG_data_ad9122_dma
create_bd_addr_seg -range 0x00010000 -offset 0x7c420000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9122_dma/s_axi/axi_lite] SEG_data_ad9643_dma create_bd_addr_seg -range 0x00010000 -offset 0x7c420000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9122_dma/s_axi/axi_lite] SEG_data_ad9643_dma
if {$sys_zynq == 0} { if {$sys_zynq == 0} {