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axi_gpreg: compile fixes

main
Rejeesh Kutty 2015-11-03 14:26:55 -05:00
parent c8019b69fd
commit ad1cef1441
3 changed files with 29 additions and 49 deletions
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11
library/axi_gpreg/axi_gpreg.v
View File

@ -105,6 +105,10 @@ module axi_gpreg #(
output [ 1:0] s_axi_rresp,
input s_axi_rready);
// version
localparam PCORE_VERSION = 32'h00040063;
// internal registers
reg up_wack_d = 'd0;
@ -117,6 +121,13 @@ module axi_gpreg #(
// internal signals
wire up_rstn;
wire up_clk;
wire up_wreq;
wire [ 13:0] up_waddr;
wire [ 31:0] up_wdata;
wire up_rreq;
wire [ 13:0] up_raddr;
wire up_wreq_s;
wire up_rreq_s;
wire [ 31:0] up_gp_ioenb_s[7:0];

35
library/axi_gpreg/axi_gpreg_constr.xdc
View File

@ -1,35 +1,4 @@
set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_rst_done*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_pll_locked*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_status*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_rst_done*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_pll_locked*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_status*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/rx_sysref_sel*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/rx_up_sysref*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/rx_up_sync*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/tx_sysref_sel*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/tx_up_sysref*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/tx_up_sync*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *ad_rst_sync*}]
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_rst_done_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_rst_done_m_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_pll_locked_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_pll_locked_m_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_status_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_rst_done_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_rst_done_m_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_pll_locked_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_pll_locked_m_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_status_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/rx_sysref_sel_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/rx_up_sysref_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/rx_up_sync_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/tx_sysref_sel_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/tx_up_sysref_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/tx_up_sync_m1_reg && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *up_rx_preset_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *ad_rst_sync_m1_reg && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *up_tx_preset_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *ad_rst_sync_m1_reg && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *up_d_preset_reg && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *ad_rst_sync_m1_reg && IS_SEQUENTIAL}]

32
library/axi_gpreg/axi_gpreg_ip.tcl
View File

@ -19,38 +19,38 @@ adi_ip_constraints axi_gpreg [list \
"axi_gpreg_constr.xdc" ]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_IO')) > 0} \
[ipx::get_bus_interfaces up_gp_*_0 -of_objects [ipx::current_core]]
[ipx::get_ports up_gp_*_0 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_IO')) > 1} \
[ipx::get_bus_interfaces up_gp_*_1 -of_objects [ipx::current_core]]
[ipx::get_ports up_gp_*_1 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_IO')) > 2} \
[ipx::get_bus_interfaces up_gp_*_2 -of_objects [ipx::current_core]]
[ipx::get_ports up_gp_*_2 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_IO')) > 3} \
[ipx::get_bus_interfaces up_gp_*_3 -of_objects [ipx::current_core]]
[ipx::get_ports up_gp_*_3 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_IO')) > 4} \
[ipx::get_bus_interfaces up_gp_*_4 -of_objects [ipx::current_core]]
[ipx::get_ports up_gp_*_4 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_IO')) > 5} \
[ipx::get_bus_interfaces up_gp_*_5 -of_objects [ipx::current_core]]
[ipx::get_ports up_gp_*_5 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_IO')) > 6} \
[ipx::get_bus_interfaces up_gp_*_6 -of_objects [ipx::current_core]]
[ipx::get_ports up_gp_*_6 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_IO')) > 7} \
[ipx::get_bus_interfaces up_gp_*_7 -of_objects [ipx::current_core]]
[ipx::get_ports up_gp_*_7 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLK_MONS')) > 0} \
[ipx::get_bus_interfaces d_clk_0 -of_objects [ipx::current_core]]
[ipx::get_ports d_clk_0 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLK_MONS')) > 1} \
[ipx::get_bus_interfaces d_clk_1 -of_objects [ipx::current_core]]
[ipx::get_ports d_clk_1 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLK_MONS')) > 2} \
[ipx::get_bus_interfaces d_clk_2 -of_objects [ipx::current_core]]
[ipx::get_ports d_clk_2 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLK_MONS')) > 3} \
[ipx::get_bus_interfaces d_clk_3 -of_objects [ipx::current_core]]
[ipx::get_ports d_clk_3 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLK_MONS')) > 4} \
[ipx::get_bus_interfaces d_clk_4 -of_objects [ipx::current_core]]
[ipx::get_ports d_clk_4 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLK_MONS')) > 5} \
[ipx::get_bus_interfaces d_clk_5 -of_objects [ipx::current_core]]
[ipx::get_ports d_clk_5 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLK_MONS')) > 6} \
[ipx::get_bus_interfaces d_clk_6 -of_objects [ipx::current_core]]
[ipx::get_ports d_clk_6 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLK_MONS')) > 7} \
[ipx::get_bus_interfaces d_clk_7 -of_objects [ipx::current_core]]
[ipx::get_ports d_clk_7 -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports -filter "direction==in" -of_objects [ipx::current_core]]