diff --git a/library/Makefile b/library/Makefile index e8d89e0be..2a790386d 100644 --- a/library/Makefile +++ b/library/Makefile @@ -55,6 +55,7 @@ clean: make -C util_axis_resize clean make -C util_bsplit clean make -C util_ccat clean + make -C util_clkdiv clean make -C util_cpack clean make -C util_dac_unpack clean make -C util_dacfifo clean @@ -121,6 +122,7 @@ lib: -make -C util_axis_resize -make -C util_bsplit -make -C util_ccat + -make -C util_clkdiv -make -C util_cpack -make -C util_dac_unpack -make -C util_dacfifo diff --git a/library/axi_ad9152/axi_ad9152.v b/library/axi_ad9152/axi_ad9152.v index 2ab69a0ee..cc9c36e45 100644 --- a/library/axi_ad9152/axi_ad9152.v +++ b/library/axi_ad9152/axi_ad9152.v @@ -65,6 +65,7 @@ module axi_ad9152 ( s_axi_aresetn, s_axi_awvalid, s_axi_awaddr, + s_axi_awprot, s_axi_awready, s_axi_wvalid, s_axi_wdata, @@ -75,6 +76,7 @@ module axi_ad9152 ( s_axi_bready, s_axi_arvalid, s_axi_araddr, + s_axi_arprot, s_axi_arready, s_axi_rvalid, s_axi_rdata, @@ -110,6 +112,7 @@ module axi_ad9152 ( input s_axi_aresetn; input s_axi_awvalid; input [ 31:0] s_axi_awaddr; + input [ 2:0] s_axi_awprot; output s_axi_awready; input s_axi_wvalid; input [ 31:0] s_axi_wdata; @@ -120,6 +123,7 @@ module axi_ad9152 ( input s_axi_bready; input s_axi_arvalid; input [ 31:0] s_axi_araddr; + input [ 2:0] s_axi_arprot; output s_axi_arready; output s_axi_rvalid; output [ 31:0] s_axi_rdata; diff --git a/library/axi_ad9152/axi_ad9152_hw.tcl b/library/axi_ad9152/axi_ad9152_hw.tcl new file mode 100755 index 000000000..27c96ffd0 --- /dev/null +++ b/library/axi_ad9152/axi_ad9152_hw.tcl @@ -0,0 +1,97 @@ + + +package require -exact qsys 13.0 +source ../scripts/adi_env.tcl +source ../scripts/adi_ip_alt.tcl + +set_module_property NAME axi_ad9152 +set_module_property DESCRIPTION "AXI AD9152 Interface" +set_module_property VERSION 1.0 +set_module_property GROUP "Analog Devices" +set_module_property DISPLAY_NAME axi_ad9152 + +# files + +add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis" +set_fileset_property quartus_synth TOP_LEVEL axi_ad9152 +add_fileset_file MULT_MACRO.v VERILOG PATH $ad_hdl_dir/library/common/altera/MULT_MACRO.v +add_fileset_file ad_mul.v VERILOG PATH $ad_hdl_dir/library/common/ad_mul.v +add_fileset_file ad_dds_sine.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_sine.v +add_fileset_file ad_dds_1.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_1.v +add_fileset_file ad_dds.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds.v +add_fileset_file ad_rst.v VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v +add_fileset_file up_axi.v VERILOG PATH $ad_hdl_dir/library/common/up_axi.v +add_fileset_file up_xfer_cntrl.v VERILOG PATH $ad_hdl_dir/library/common/up_xfer_cntrl.v +add_fileset_file up_xfer_status.v VERILOG PATH $ad_hdl_dir/library/common/up_xfer_status.v +add_fileset_file up_clock_mon.v VERILOG PATH $ad_hdl_dir/library/common/up_clock_mon.v +add_fileset_file up_dac_common.v VERILOG PATH $ad_hdl_dir/library/common/up_dac_common.v +add_fileset_file up_dac_channel.v VERILOG PATH $ad_hdl_dir/library/common/up_dac_channel.v +add_fileset_file axi_ad9152_channel.v VERILOG PATH axi_ad9152_channel.v +add_fileset_file axi_ad9152_core.v VERILOG PATH axi_ad9152_core.v +add_fileset_file axi_ad9152_if.v VERILOG PATH axi_ad9152_if.v +add_fileset_file axi_ad9152.v VERILOG PATH axi_ad9152.v TOP_LEVEL_FILE +add_fileset_file ad_axi_ip_constr.sdc SDC PATH $ad_hdl_dir/library/common/ad_axi_ip_constr.sdc + +# parameters + +add_parameter ID INTEGER 0 +set_parameter_property ID DEFAULT_VALUE 0 +set_parameter_property ID DISPLAY_NAME ID +set_parameter_property ID TYPE INTEGER +set_parameter_property ID UNITS None +set_parameter_property ID HDL_PARAMETER true + +# axi4 slave + +add_interface s_axi_clock clock end +add_interface_port s_axi_clock s_axi_aclk clk Input 1 + +add_interface s_axi_reset reset end +set_interface_property s_axi_reset associatedClock s_axi_clock +add_interface_port s_axi_reset s_axi_aresetn reset_n Input 1 + +add_interface s_axi axi4lite end +set_interface_property s_axi associatedClock s_axi_clock +set_interface_property s_axi associatedReset s_axi_reset +add_interface_port s_axi s_axi_awvalid awvalid Input 1 +add_interface_port s_axi s_axi_awaddr awaddr Input 16 +add_interface_port s_axi s_axi_awprot awprot Input 3 +add_interface_port s_axi s_axi_awready awready Output 1 +add_interface_port s_axi s_axi_wvalid wvalid Input 1 +add_interface_port s_axi s_axi_wdata wdata Input 32 +add_interface_port s_axi s_axi_wstrb wstrb Input 4 +add_interface_port s_axi s_axi_wready wready Output 1 +add_interface_port s_axi s_axi_bvalid bvalid Output 1 +add_interface_port s_axi s_axi_bresp bresp Output 2 +add_interface_port s_axi s_axi_bready bready Input 1 +add_interface_port s_axi s_axi_arvalid arvalid Input 1 +add_interface_port s_axi s_axi_araddr araddr Input 16 +add_interface_port s_axi s_axi_arprot arprot Input 3 +add_interface_port s_axi s_axi_arready arready Output 1 +add_interface_port s_axi s_axi_rvalid rvalid Output 1 +add_interface_port s_axi s_axi_rresp rresp Output 2 +add_interface_port s_axi s_axi_rdata rdata Output 32 +add_interface_port s_axi s_axi_rready rready Input 1 + +# transceiver interface + +ad_alt_intf clock tx_clk input 1 +ad_alt_intf signal tx_data output 128 data + +# dma interface + +ad_alt_intf clock dac_clk output 1 + +add_interface fifo_ch_0_out conduit end +add_interface_port fifo_ch_0_out dac_enable_0 enable Output 1 +add_interface_port fifo_ch_0_out dac_valid_0 valid Output 1 +add_interface_port fifo_ch_0_out dac_ddata_0 data Input 64 + +add_interface fifo_ch_1_out conduit end +add_interface_port fifo_ch_1_out dac_enable_1 enable Output 1 +add_interface_port fifo_ch_1_out dac_valid_1 valid Output 1 +add_interface_port fifo_ch_1_out dac_ddata_1 data Input 64 + +ad_alt_intf signal dac_dovf input 1 ovf +ad_alt_intf signal dac_dunf input 1 unf + diff --git a/library/axi_dmac/axi_dmac_constr.ttcl b/library/axi_dmac/axi_dmac_constr.ttcl index 43befdab1..2ca055ecf 100644 --- a/library/axi_dmac/axi_dmac_constr.ttcl +++ b/library/axi_dmac/axi_dmac_constr.ttcl @@ -11,10 +11,12 @@ set req_clk [get_clocks -of_objects [get_ports s_axi_aclk]] set src_clk [get_clocks -of_objects [get_ports -quiet {fifo_wr_clk s_axis_aclk m_src_axi_aclk}]] set dest_clk [get_clocks -of_objects [get_ports -quiet {fifo_rd_clk m_axis_aclk m_dest_axi_aclk}]] +<: if {$async_req_src || $async_src_dest || $async_dest_req} { :> set_property ASYNC_REG TRUE \ [get_cells -quiet -hier *cdc_sync_stage1_reg*] \ [get_cells -quiet -hier *cdc_sync_stage2_reg*] +<: } :> <: if {$async_req_src} { :> set_max_delay -quiet -datapath_only \ -from $req_clk \ diff --git a/library/axi_dmac/data_mover.v b/library/axi_dmac/data_mover.v index 0c883d5fd..714e28cb2 100644 --- a/library/axi_dmac/data_mover.v +++ b/library/axi_dmac/data_mover.v @@ -68,6 +68,8 @@ parameter ID_WIDTH = 3; parameter DATA_WIDTH = 64; parameter DISABLE_WAIT_FOR_ID = 1; parameter BEATS_PER_BURST_WIDTH = 4; +parameter LAST = 0; /* 0 = last asserted at the end of each burst, 1 = last only asserted at the end of the transfer */ + localparam MAX_BEATS_PER_BURST = 2**(BEATS_PER_BURST_WIDTH); `include "inc_id.h" @@ -94,7 +96,7 @@ assign last = eot ? last_eot : last_non_eot; assign s_axi_ready = m_axi_ready & pending_burst & active; assign m_axi_valid = s_axi_valid & pending_burst & active; assign m_axi_data = s_axi_data; -assign m_axi_last = last; +assign m_axi_last = LAST ? (last_eot & eot) : last; // If we want to support zero delay between transfers we have to assert // req_ready on the same cycle on which the last load happens. diff --git a/library/axi_dmac/dest_axi_stream.v b/library/axi_dmac/dest_axi_stream.v index a72a24e80..48c5dea55 100644 --- a/library/axi_dmac/dest_axi_stream.v +++ b/library/axi_dmac/dest_axi_stream.v @@ -100,7 +100,8 @@ dmac_data_mover # ( .ID_WIDTH(ID_WIDTH), .DATA_WIDTH(S_AXIS_DATA_WIDTH), .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH), - .DISABLE_WAIT_FOR_ID(0) + .DISABLE_WAIT_FOR_ID(0), + .LAST(1) ) i_data_mover ( .clk(s_axis_aclk), .resetn(s_axis_aresetn), diff --git a/library/axi_hdmi_tx/axi_hdmi_tx.v b/library/axi_hdmi_tx/axi_hdmi_tx.v index 1413a39b3..056eb2fb3 100644 --- a/library/axi_hdmi_tx/axi_hdmi_tx.v +++ b/library/axi_hdmi_tx/axi_hdmi_tx.v @@ -202,6 +202,8 @@ module axi_hdmi_tx ( wire [15:0] hdmi_vs_width_s; wire [15:0] hdmi_ve_max_s; wire [15:0] hdmi_ve_min_s; + wire [31:0] hdmi_clip_max_s; + wire [31:0] hdmi_clip_min_s; wire hdmi_fs_toggle_s; wire [ 8:0] hdmi_raddr_g_s; wire hdmi_tpm_oos_s; @@ -271,6 +273,8 @@ module axi_hdmi_tx ( .hdmi_vs_width (hdmi_vs_width_s), .hdmi_ve_max (hdmi_ve_max_s), .hdmi_ve_min (hdmi_ve_min_s), + .hdmi_clip_max (hdmi_clip_max_s), + .hdmi_clip_min (hdmi_clip_min_s), .hdmi_status (hdmi_status_s), .hdmi_tpm_oos (hdmi_tpm_oos_s), .hdmi_clk_ratio (32'd1), @@ -356,7 +360,9 @@ module axi_hdmi_tx ( .hdmi_vf_width (hdmi_vf_width_s), .hdmi_vs_width (hdmi_vs_width_s), .hdmi_ve_max (hdmi_ve_max_s), - .hdmi_ve_min (hdmi_ve_min_s)); + .hdmi_ve_min (hdmi_ve_min_s), + .hdmi_clip_max (hdmi_clip_max_s), + .hdmi_clip_min (hdmi_clip_min_s)); // hdmi output clock diff --git a/library/axi_hdmi_tx/axi_hdmi_tx_core.v b/library/axi_hdmi_tx/axi_hdmi_tx_core.v index 3831a821e..fd1ccf12c 100644 --- a/library/axi_hdmi_tx/axi_hdmi_tx_core.v +++ b/library/axi_hdmi_tx/axi_hdmi_tx_core.v @@ -97,7 +97,9 @@ module axi_hdmi_tx_core ( hdmi_vf_width, hdmi_vs_width, hdmi_ve_max, - hdmi_ve_min); + hdmi_ve_min, + hdmi_clip_max, + hdmi_clip_min); // parameters @@ -164,6 +166,8 @@ module axi_hdmi_tx_core ( input [15:0] hdmi_vs_width; input [15:0] hdmi_ve_max; input [15:0] hdmi_ve_min; + input [23:0] hdmi_clip_max; + input [23:0] hdmi_clip_min; // internal registers @@ -205,12 +209,24 @@ module axi_hdmi_tx_core ( reg hdmi_vsync_data_e = 'd0; reg hdmi_data_e = 'd0; reg [23:0] hdmi_data = 'd0; + reg hdmi_24_csc_hsync = 'd0; + reg hdmi_24_csc_vsync = 'd0; + reg hdmi_24_csc_hsync_data_e = 'd0; + reg hdmi_24_csc_vsync_data_e = 'd0; + reg hdmi_24_csc_data_e = 'd0; + reg [23:0] hdmi_24_csc_data = 'd0; reg hdmi_24_hsync = 'd0; reg hdmi_24_vsync = 'd0; reg hdmi_24_hsync_data_e = 'd0; reg hdmi_24_vsync_data_e = 'd0; reg hdmi_24_data_e = 'd0; reg [23:0] hdmi_24_data = 'd0; + reg hdmi_24_hsync_ss = 'd0; + reg hdmi_24_vsync_ss = 'd0; + reg hdmi_24_hsync_data_e_ss = 'd0; + reg hdmi_24_vsync_data_e_ss = 'd0; + reg hdmi_24_data_e_ss = 'd0; + reg [23:0] hdmi_24_data_ss = 'd0; reg hdmi_16_hsync = 'd0; reg hdmi_16_vsync = 'd0; reg hdmi_16_hsync_data_e = 'd0; @@ -220,6 +236,12 @@ module axi_hdmi_tx_core ( reg hdmi_es_hs_de = 'd0; reg hdmi_es_vs_de = 'd0; reg [15:0] hdmi_es_data = 'd0; + reg [23:0] hdmi_clip_data = 'd0; + reg hdmi_clip_hs_de_d = 'd0; + reg hdmi_clip_vs_de_d = 'd0; + reg hdmi_clip_hs_d = 'd0; + reg hdmi_clip_vs_d = 'd0; + reg hdmi_clip_de_d = 'd0; // internal wires @@ -245,6 +267,10 @@ module axi_hdmi_tx_core ( wire hdmi_ss_vsync_data_e_s; wire hdmi_ss_data_e_s; wire [15:0] hdmi_ss_data_s; + wire hdmi_clip_hs_de_s; + wire hdmi_clip_vs_de_s; + wire hdmi_clip_de_s; + wire [23:0] hdmi_clip_data_s; wire hdmi_es_hs_de_s; wire hdmi_es_vs_de_s; wire hdmi_es_de_s; @@ -453,6 +479,68 @@ module axi_hdmi_tx_core ( endcase end + // Color space conversion bypass (RGB/YCbCr) + + always @(posedge hdmi_clk) begin + if (hdmi_csc_bypass == 1'b1) begin + hdmi_24_csc_hsync <= hdmi_hsync; + hdmi_24_csc_vsync <= hdmi_vsync; + hdmi_24_csc_hsync_data_e <= hdmi_hsync_data_e; + hdmi_24_csc_vsync_data_e <= hdmi_vsync_data_e; + hdmi_24_csc_data_e <= hdmi_data_e; + hdmi_24_csc_data <= hdmi_data; + end else begin + hdmi_24_csc_hsync <= hdmi_csc_hsync_s; + hdmi_24_csc_vsync <= hdmi_csc_vsync_s; + hdmi_24_csc_hsync_data_e <= hdmi_csc_hsync_data_e_s; + hdmi_24_csc_vsync_data_e <= hdmi_csc_vsync_data_e_s; + hdmi_24_csc_data_e <= hdmi_csc_data_e_s; + hdmi_24_csc_data <= hdmi_csc_data_s; + end + end + + // hdmi clipping + + assign hdmi_clip_data_s = hdmi_24_csc_data; + + always @(posedge hdmi_clk) begin + hdmi_clip_hs_d <= hdmi_24_csc_hsync; + hdmi_clip_vs_d <= hdmi_24_csc_vsync; + hdmi_clip_hs_de_d <= hdmi_24_csc_hsync_data_e; + hdmi_clip_vs_de_d <= hdmi_24_csc_vsync_data_e; + hdmi_clip_de_d <= hdmi_24_csc_data_e; + + // Cr (red-diff) / red + + if (hdmi_clip_data_s[23:16] > hdmi_clip_max[23:16]) begin + hdmi_clip_data[23:16] <= hdmi_clip_max[23:16]; + end else if (hdmi_clip_data_s[23:16] < hdmi_clip_min[23:16]) begin + hdmi_clip_data[23:16] <= hdmi_clip_min[23:16]; + end else begin + hdmi_clip_data[23:16] <= hdmi_clip_data_s[23:16]; + end + + // Y (luma) / green + + if (hdmi_clip_data_s[15:8] > hdmi_clip_max[15:8]) begin + hdmi_clip_data[15:8] <= hdmi_clip_max[15:8]; + end else if (hdmi_clip_data_s[15:8] < hdmi_clip_min[15:8]) begin + hdmi_clip_data[15:8] <= hdmi_clip_min[15:8]; + end else begin + hdmi_clip_data[15:8] <= hdmi_clip_data_s[15:8]; + end + + // Cb (blue-diff) / blue + + if (hdmi_clip_data_s[7:0] > hdmi_clip_max[7:0]) begin + hdmi_clip_data[7:0] <= hdmi_clip_max[7:0]; + end else if (hdmi_clip_data_s[7:0] < hdmi_clip_min[7:0]) begin + hdmi_clip_data[7:0] <= hdmi_clip_min[7:0]; + end else begin + hdmi_clip_data[7:0] <= hdmi_clip_data_s[7:0]; + end + end + // hdmi csc 16, 24 and 36 outputs assign hdmi_36_hsync = hdmi_24_hsync; @@ -463,21 +551,14 @@ module axi_hdmi_tx_core ( assign hdmi_36_data[11: 0] = {hdmi_24_data[ 7: 0], hdmi_24_data[ 7: 4]}; always @(posedge hdmi_clk) begin - if (hdmi_csc_bypass == 1'b1) begin - hdmi_24_hsync <= hdmi_hsync; - hdmi_24_vsync <= hdmi_vsync; - hdmi_24_hsync_data_e <= hdmi_hsync_data_e; - hdmi_24_vsync_data_e <= hdmi_vsync_data_e; - hdmi_24_data_e <= hdmi_data_e; - hdmi_24_data <= hdmi_data; - end else begin - hdmi_24_hsync <= hdmi_csc_hsync_s; - hdmi_24_vsync <= hdmi_csc_vsync_s; - hdmi_24_hsync_data_e <= hdmi_csc_hsync_data_e_s; - hdmi_24_vsync_data_e <= hdmi_csc_vsync_data_e_s; - hdmi_24_data_e <= hdmi_csc_data_e_s; - hdmi_24_data <= hdmi_csc_data_s; - end + + hdmi_24_hsync <= hdmi_clip_hs_d; + hdmi_24_vsync <= hdmi_clip_vs_d; + hdmi_24_hsync_data_e <= hdmi_clip_hs_de_d; + hdmi_24_vsync_data_e <= hdmi_clip_vs_de_d; + hdmi_24_data_e <= hdmi_clip_de_d; + hdmi_24_data <= hdmi_clip_data; + if (hdmi_ss_bypass == 1'b1) begin hdmi_16_hsync <= hdmi_24_hsync; hdmi_16_vsync <= hdmi_24_vsync; @@ -495,7 +576,7 @@ module axi_hdmi_tx_core ( end end - // hdmi embedded sync clipping + // hdmi embedded sync assign hdmi_es_hs_de_s = hdmi_16_hsync_data_e; assign hdmi_es_vs_de_s = hdmi_16_vsync_data_e; @@ -507,31 +588,11 @@ module axi_hdmi_tx_core ( hdmi_es_vs_de <= hdmi_es_vs_de_s; if (hdmi_es_de_s == 1'b0) begin hdmi_es_data[15:8] <= 8'h80; - end else if ((hdmi_full_range == 1'b0) && - (hdmi_es_data_s[15:8] > 8'heb)) begin - hdmi_es_data[15:8] <= 8'heb; - end else if ((hdmi_full_range == 1'b0) && - (hdmi_es_data_s[15:8] < 8'h10)) begin - hdmi_es_data[15:8] <= 8'h10; - end else if (hdmi_es_data_s[15:8] > 8'hfe) begin - hdmi_es_data[15:8] <= 8'hfe; - end else if (hdmi_es_data_s[15:8] < 8'h01) begin - hdmi_es_data[15:8] <= 8'h01; end else begin hdmi_es_data[15:8] <= hdmi_es_data_s[15:8]; end if (hdmi_es_de_s == 1'b0) begin hdmi_es_data[7:0] <= 8'h80; - end else if ((hdmi_full_range == 1'b0) && - (hdmi_es_data_s[7:0] > 8'heb)) begin - hdmi_es_data[7:0] <= 8'heb; - end else if ((hdmi_full_range == 1'b0) && - (hdmi_es_data_s[7:0] < 8'h10)) begin - hdmi_es_data[7:0] <= 8'h10; - end else if (hdmi_es_data_s[7:0] > 8'hfe) begin - hdmi_es_data[7:0] <= 8'hfe; - end else if (hdmi_es_data_s[7:0] < 8'h01) begin - hdmi_es_data[7:0] <= 8'h01; end else begin hdmi_es_data[7:0] <= hdmi_es_data_s[7:0]; end @@ -569,13 +630,13 @@ module axi_hdmi_tx_core ( ad_ss_444to422 #(.DELAY_DATA_WIDTH(5), .CR_CB_N(CR_CB_N)) i_ss_444to422 ( .clk (hdmi_clk), - .s444_de (hdmi_24_data_e), - .s444_sync ({hdmi_24_hsync, - hdmi_24_vsync, - hdmi_24_hsync_data_e, - hdmi_24_vsync_data_e, - hdmi_24_data_e}), - .s444_data (hdmi_24_data), + .s444_de (hdmi_clip_de_d), + .s444_sync ({hdmi_clip_hs_d, + hdmi_clip_vs_d, + hdmi_clip_hs_de_d, + hdmi_clip_vs_de_d, + hdmi_clip_de_d}), + .s444_data (hdmi_clip_data), .s422_sync ({hdmi_ss_hsync_s, hdmi_ss_vsync_s, hdmi_ss_hsync_data_e_s, diff --git a/library/axi_i2s_adi/axi_i2s_adi_ip.tcl b/library/axi_i2s_adi/axi_i2s_adi_ip.tcl index 7b036d481..d30ec0834 100644 --- a/library/axi_i2s_adi/axi_i2s_adi_ip.tcl +++ b/library/axi_i2s_adi/axi_i2s_adi_ip.tcl @@ -19,7 +19,7 @@ adi_ip_files axi_i2s_adi [list \ "axi_i2s_adi_constr.xdc" \ ] -adi_ip_properties_lite axi_i2s_adi +adi_ip_properties axi_i2s_adi adi_ip_constraints axi_spdif_tx axi_i2s_adi_constr.xdc late adi_add_bus "DMA_ACK_RX" "slave" \ @@ -30,6 +30,7 @@ adi_add_bus "DMA_ACK_RX" "slave" \ {"DMA_REQ_RX_DAREADY" "TREADY"} \ {"DMA_REQ_RX_DATYPE" "TUSER"} \ } + adi_add_bus "DMA_REQ_RX" "master" \ "xilinx.com:interface:axis_rtl:1.0" \ "xilinx.com:interface:axis:1.0" \ @@ -95,8 +96,9 @@ adi_set_ports_dependency "DMA_REQ_RX_ACLK" \ adi_set_ports_dependency "DMA_REQ_RX_RSTN" \ "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)" -set_property value S_AXI_ARESETN [ipx::get_bus_parameters ASSOCIATED_RESET \ - -of_objects [ipx::get_bus_interfaces S_AXI_ACLK -of_objects [ipx::current_core]]] +ipx::associate_bus_interfaces -clock s_axi_aclk -reset S_AXI_ARESETN [ipx::current_core] +ipx::associate_bus_interfaces -busif I2S -clock i2s_signal_clock [ipx::current_core] +ipx::associate_bus_interfaces -clock s_axi_aclk -reset S_AXIS_ARESETN -clear [ipx::current_core] ipx::save_core [ipx::current_core] diff --git a/library/axi_jesd_gt/axi_jesd_gt.v b/library/axi_jesd_gt/axi_jesd_gt.v index 41085bfbe..0612f9e6b 100644 --- a/library/axi_jesd_gt/axi_jesd_gt.v +++ b/library/axi_jesd_gt/axi_jesd_gt.v @@ -668,8 +668,8 @@ module axi_jesd_gt #( // axi - clock & reset - input axi_aclk, - input axi_aresetn, + input s_axi_aclk, + input s_axi_aresetn, // axi interface @@ -831,8 +831,8 @@ module axi_jesd_gt #( // signal name changes - assign up_rstn = axi_aresetn; - assign up_clk = axi_aclk; + assign up_rstn = s_axi_aresetn; + assign up_clk = s_axi_aclk; // pll diff --git a/library/axi_jesd_gt/axi_jesd_gt_ip.tcl b/library/axi_jesd_gt/axi_jesd_gt_ip.tcl index 558c74b07..79688653b 100644 --- a/library/axi_jesd_gt/axi_jesd_gt_ip.tcl +++ b/library/axi_jesd_gt/axi_jesd_gt_ip.tcl @@ -24,16 +24,7 @@ adi_ip_properties axi_jesd_gt adi_ip_constraints axi_jesd_gt [list \ "axi_jesd_gt_constr.xdc" ] -ipx::remove_bus_interface qpll0_rst [ipx::current_core] -ipx::remove_bus_interface qpll1_rst [ipx::current_core] - -set_property value m_axi:s_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \ - -of_objects [ipx::get_bus_interfaces axi_aclk \ - -of_objects [ipx::current_core]]] - -set_property value axi_aresetn [ipx::get_bus_parameters ASSOCIATED_RESET \ - -of_objects [ipx::get_bus_interfaces axi_aclk \ - -of_objects [ipx::current_core]]] +ipx::associate_bus_interfaces -busif m_axi -clock s_axi_aclk [ipx::current_core] adi_if_infer_bus ADI:user:if_gt_qpll slave gt_qpll_0 [list \ "qpll_rst qpll0_rst "\ diff --git a/library/axi_spdif_rx/axi_spdif_rx_ip.tcl b/library/axi_spdif_rx/axi_spdif_rx_ip.tcl index edbe7f930..9b22be7d6 100644 --- a/library/axi_spdif_rx/axi_spdif_rx_ip.tcl +++ b/library/axi_spdif_rx/axi_spdif_rx_ip.tcl @@ -16,7 +16,7 @@ adi_ip_files axi_spdif_rx [list \ "axi_spdif_rx.vhd" \ "axi_spdif_rx_constr.xdc"] -adi_ip_properties_lite axi_spdif_rx +adi_ip_properties axi_spdif_rx adi_ip_constraints axi_spdif_tx axi_spdif_rx_constr.xdc adi_add_bus "DMA_ACK" "slave" \ @@ -49,4 +49,5 @@ adi_set_ports_dependency "DMA_REQ_RSTN" \ "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)" ipx::save_core [ipx::current_core] +ipx::associate_bus_interfaces -clock s_axi_aclk -reset S_AXI_ARESETN [ipx::current_core] diff --git a/library/axi_spdif_tx/axi_spdif_tx_ip.tcl b/library/axi_spdif_tx/axi_spdif_tx_ip.tcl index 19d2d7c70..fdc4c38c3 100644 --- a/library/axi_spdif_tx/axi_spdif_tx_ip.tcl +++ b/library/axi_spdif_tx/axi_spdif_tx_ip.tcl @@ -14,7 +14,7 @@ adi_ip_files axi_spdif_tx [list \ "axi_spdif_tx.vhd" \ "axi_spdif_tx_constr.xdc" ] -adi_ip_properties_lite axi_spdif_tx +adi_ip_properties axi_spdif_tx adi_ip_constraints axi_spdif_tx axi_spdif_tx_constr.xdc adi_add_bus "DMA_ACK" "slave" \ @@ -46,8 +46,7 @@ adi_set_ports_dependency "DMA_REQ_ACLK" \ adi_set_ports_dependency "DMA_REQ_RSTN" \ "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)" -set_property value S_AXI_ARESETN [ipx::get_bus_parameters ASSOCIATED_RESET \ - -of_objects [ipx::get_bus_interfaces S_AXI_ACLK -of_objects [ipx::current_core]]] - +ipx::associate_bus_interfaces -clock s_axi_aclk -reset S_AXIS_ARESETN -clear [ipx::current_core] +ipx::associate_bus_interfaces -clock s_axi_aclk -reset S_AXI_ARESETN [ipx::current_core] ipx::save_core [ipx::current_core] diff --git a/library/common/up_axi.v b/library/common/up_axi.v index 91e1e7c1b..db62e659a 100644 --- a/library/common/up_axi.v +++ b/library/common/up_axi.v @@ -1,9 +1,9 @@ // *************************************************************************** // *************************************************************************** // Copyright 2011(c) Analog Devices, Inc. -// +// // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without modification, // are permitted provided that the following conditions are met: // - Redistributions of source code must retain the above copyright @@ -21,21 +21,19 @@ // patent holders to use this software. // - Use of the software either in source or binary form, must be run // on or directly connected to an Analog Devices Inc. component. -// +// // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A // PARTICULAR PURPOSE ARE DISCLAIMED. // // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// *************************************************************************** -// *************************************************************************** `timescale 1ns/100ps @@ -123,26 +121,30 @@ module up_axi ( reg up_axi_awready = 'd0; reg up_axi_wready = 'd0; reg up_axi_bvalid = 'd0; + reg up_wack_d = 'd0; reg up_wsel = 'd0; reg up_wreq = 'd0; reg [AW:0] up_waddr = 'd0; reg [31:0] up_wdata = 'd0; - reg [ 2:0] up_wcount = 'd0; - reg up_wack_int = 'd0; + reg [ 4:0] up_wcount = 'd0; reg up_axi_arready = 'd0; reg up_axi_rvalid = 'd0; reg [31:0] up_axi_rdata = 'd0; + reg up_rack_d = 'd0; + reg [31:0] up_rdata_d = 'd0; reg up_rsel = 'd0; reg up_rreq = 'd0; reg [AW:0] up_raddr = 'd0; - reg [ 3:0] up_rcount = 'd0; - reg up_rack_int = 'd0; - reg [31:0] up_rdata_int = 'd0; - reg up_rack_int_d = 'd0; - reg [31:0] up_rdata_int_d = 'd0; + reg [ 4:0] up_rcount = 'd0; + + // internal signals + + wire up_wack_s; + wire up_rack_s; + wire [31:0] up_rdata_s; // write channel interface - + assign up_axi_bresp = 2'd0; always @(negedge up_rstn or posedge up_clk) begin @@ -153,30 +155,34 @@ module up_axi ( end else begin if (up_axi_awready == 1'b1) begin up_axi_awready <= 1'b0; - end else if (up_wack_int == 1'b1) begin + end else if (up_wack_s == 1'b1) begin up_axi_awready <= 1'b1; end if (up_axi_wready == 1'b1) begin up_axi_wready <= 1'b0; - end else if (up_wack_int == 1'b1) begin + end else if (up_wack_s == 1'b1) begin up_axi_wready <= 1'b1; end if ((up_axi_bready == 1'b1) && (up_axi_bvalid == 1'b1)) begin up_axi_bvalid <= 1'b0; - end else if (up_wack_int == 1'b1) begin + end else if (up_wack_d == 1'b1) begin up_axi_bvalid <= 1'b1; end end - end + end + + assign up_wack_s = (up_wcount == 5'h1f) ? 1'b1 : (up_wcount[4] & up_wack); always @(negedge up_rstn or posedge up_clk) begin if (up_rstn == 1'b0) begin + up_wack_d <= 'd0; up_wsel <= 'd0; up_wreq <= 'd0; up_waddr <= 'd0; up_wdata <= 'd0; up_wcount <= 'd0; end else begin + up_wack_d <= up_wack_s; if (up_wsel == 1'b1) begin if ((up_axi_bready == 1'b1) && (up_axi_bvalid == 1'b1)) begin up_wsel <= 1'b0; @@ -184,25 +190,18 @@ module up_axi ( up_wreq <= 1'b0; up_waddr <= up_waddr; up_wdata <= up_wdata; - up_wcount <= up_wcount + 1'b1; end else begin up_wsel <= up_axi_awvalid & up_axi_wvalid; up_wreq <= up_axi_awvalid & up_axi_wvalid; up_waddr <= up_axi_awaddr[AW+2:2]; up_wdata <= up_axi_wdata; - up_wcount <= 3'd0; end - end - end - - always @(negedge up_rstn or posedge up_clk) begin - if (up_rstn == 0) begin - up_wack_int <= 'd0; - end else begin - if ((up_wcount == 3'h7) && (up_wack == 1'b0)) begin - up_wack_int <= 1'b1; - end else if (up_wsel == 1'b1) begin - up_wack_int <= up_wack; + if (up_wack_s == 1'b1) begin + up_wcount <= 5'h00; + end else if (up_wcount[4] == 1'b1) begin + up_wcount <= up_wcount + 1'b1; + end else if (up_wreq == 1'b1) begin + up_wcount <= 5'h10; end end end @@ -219,26 +218,33 @@ module up_axi ( end else begin if (up_axi_arready == 1'b1) begin up_axi_arready <= 1'b0; - end else if (up_rack_int == 1'b1) begin + end else if (up_rack_s == 1'b1) begin up_axi_arready <= 1'b1; end if ((up_axi_rready == 1'b1) && (up_axi_rvalid == 1'b1)) begin up_axi_rvalid <= 1'b0; up_axi_rdata <= 32'd0; - end else if (up_rack_int_d == 1'b1) begin + end else if (up_rack_d == 1'b1) begin up_axi_rvalid <= 1'b1; - up_axi_rdata <= up_rdata_int_d; + up_axi_rdata <= up_rdata_d; end end - end + end + + assign up_rack_s = (up_rcount == 5'h1f) ? 1'b1 : (up_rcount[4] & up_rack); + assign up_rdata_s = (up_rcount == 5'h1f) ? {2{16'hdead}} : up_rdata; always @(negedge up_rstn or posedge up_clk) begin if (up_rstn == 1'b0) begin + up_rack_d <= 'd0; + up_rdata_d <= 'd0; up_rsel <= 'd0; up_rreq <= 'd0; up_raddr <= 'd0; up_rcount <= 'd0; end else begin + up_rack_d <= up_rack_s; + up_rdata_d <= up_rdata_s; if (up_rsel == 1'b1) begin if ((up_axi_rready == 1'b1) && (up_axi_rvalid == 1'b1)) begin up_rsel <= 1'b0; @@ -250,35 +256,16 @@ module up_axi ( up_rreq <= up_axi_arvalid; up_raddr <= up_axi_araddr[AW+2:2]; end - if (up_rack_int == 1'b1) begin - up_rcount <= 4'd0; - end else if (up_rcount[3] == 1'b1) begin + if (up_rack_s == 1'b1) begin + up_rcount <= 5'h00; + end else if (up_rcount[4] == 1'b1) begin up_rcount <= up_rcount + 1'b1; end else if (up_rreq == 1'b1) begin - up_rcount <= 4'd8; + up_rcount <= 5'h10; end end end - always @(negedge up_rstn or posedge up_clk) begin - if (up_rstn == 0) begin - up_rack_int <= 'd0; - up_rdata_int <= 'd0; - up_rack_int_d <= 'd0; - up_rdata_int_d <= 'd0; - end else begin - if ((up_rcount == 4'hf) && (up_rack == 1'b0)) begin - up_rack_int <= 1'b1; - up_rdata_int <= {2{16'hdead}}; - end else begin - up_rack_int <= up_rack; - up_rdata_int <= up_rdata; - end - up_rack_int_d <= up_rack_int; - up_rdata_int_d <= up_rdata_int; - end - end - endmodule // *************************************************************************** diff --git a/library/common/up_hdmi_tx.v b/library/common/up_hdmi_tx.v index f63f93d60..e1750e76b 100644 --- a/library/common/up_hdmi_tx.v +++ b/library/common/up_hdmi_tx.v @@ -58,6 +58,8 @@ module up_hdmi_tx ( hdmi_vs_width, hdmi_ve_max, hdmi_ve_min, + hdmi_clip_max, + hdmi_clip_min, hdmi_status, hdmi_tpm_oos, hdmi_clk_ratio, @@ -107,6 +109,8 @@ module up_hdmi_tx ( output [15:0] hdmi_vs_width; output [15:0] hdmi_ve_max; output [15:0] hdmi_ve_min; + output [23:0] hdmi_clip_max; + output [23:0] hdmi_clip_min; input hdmi_status; input hdmi_tpm_oos; input [31:0] hdmi_clk_ratio; @@ -157,6 +161,8 @@ module up_hdmi_tx ( reg [15:0] up_vs_width = 'd0; reg [15:0] up_ve_max = 'd0; reg [15:0] up_ve_min = 'd0; + reg [23:0] up_clip_max = 'd0; + reg [23:0] up_clip_min = 'd0; reg up_rack = 'd0; reg [31:0] up_rdata = 'd0; @@ -203,6 +209,8 @@ module up_hdmi_tx ( up_vs_width <= 'd0; up_ve_max <= 'd0; up_ve_min <= 'd0; + up_clip_max <= 24'hf0ebf0; + up_clip_min <= 24'h101010; end else begin up_core_preset <= ~up_resetn; up_wack <= up_wreq_s; @@ -243,6 +251,21 @@ module up_hdmi_tx ( end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h019)) begin up_vdma_tpm_oos <= up_vdma_tpm_oos & ~up_wdata[0]; end + if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h011)) begin + if ((up_wdata[1]== 1'b1) || (up_wdata[0] == 1'b1)) begin + up_clip_max <= 24'hfefefe; + up_clip_min <= 24'h010101; + end else begin + up_clip_max <= 24'hf0ebf0; + up_clip_min <= 24'h101010; + end + end + if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h01a)) begin + up_clip_max <= up_wdata[23:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h01b)) begin + up_clip_min <= up_wdata[23:0]; + end if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h100)) begin up_hl_active <= up_wdata[31:16]; up_hl_width <= up_wdata[15:0]; @@ -290,6 +313,9 @@ module up_hdmi_tx ( 12'h017: up_rdata <= {31'd0, up_hdmi_status_s}; 12'h018: up_rdata <= {30'd0, up_vdma_ovf, up_vdma_unf}; 12'h019: up_rdata <= {30'd0, up_hdmi_tpm_oos, up_vdma_tpm_oos}; + 12'h01a: up_rdata <= {8'd0, up_clip_max}; + 12'h01b: up_rdata <= {8'd0, up_clip_min}; + 12'h100: up_rdata <= {up_hl_active, up_hl_width}; 12'h101: up_rdata <= {16'd0, up_hs_width}; 12'h102: up_rdata <= {up_he_max, up_he_min}; @@ -311,7 +337,7 @@ module up_hdmi_tx ( // hdmi control & status - up_xfer_cntrl #(.DATA_WIDTH(189)) i_xfer_cntrl ( + up_xfer_cntrl #(.DATA_WIDTH(237)) i_xfer_cntrl ( .up_rstn (up_rstn), .up_clk (up_clk), .up_data_cntrl ({ up_ss_bypass, @@ -328,7 +354,9 @@ module up_hdmi_tx ( up_vf_width, up_vs_width, up_ve_max, - up_ve_min}), + up_ve_min, + up_clip_max, + up_clip_min}), .up_xfer_done (), .d_rst (hdmi_rst), .d_clk (hdmi_clk), @@ -346,7 +374,9 @@ module up_hdmi_tx ( hdmi_vf_width, hdmi_vs_width, hdmi_ve_max, - hdmi_ve_min})); + hdmi_ve_min, + hdmi_clip_max, + hdmi_clip_min})); up_xfer_status #(.DATA_WIDTH(2)) i_xfer_status ( .up_rstn (up_rstn), diff --git a/library/scripts/adi_ip.tcl b/library/scripts/adi_ip.tcl index bd443c882..f9d416a59 100644 --- a/library/scripts/adi_ip.tcl +++ b/library/scripts/adi_ip.tcl @@ -2,7 +2,7 @@ # check tool version if {![info exists REQUIRED_VIVADO_VERSION]} { - set REQUIRED_VIVADO_VERSION "2015.2.1" + set REQUIRED_VIVADO_VERSION "2015.4.2" } if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { @@ -78,13 +78,6 @@ proc adi_ip_bd {ip_name ip_bd_files} { proc adi_ip_properties {ip_name} { ipx::package_project -root_dir . - ipx::remove_memory_map {s_axi} [ipx::current_core] - ipx::add_memory_map {s_axi} [ipx::current_core] - set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] - - ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] - set_property range {65536} [ipx::get_address_blocks axi_lite \ - -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] set_property vendor {analog.com} [ipx::current_core] set_property library {user} [ipx::current_core] @@ -109,6 +102,47 @@ proc adi_ip_properties {ip_name} { {qzynq} {Production} \ {azynq} {Production}} \ [ipx::current_core] + + ipx::remove_all_bus_interface [ipx::current_core] + ipx::infer_bus_interface {\ + s_axi_awvalid \ + s_axi_awaddr \ + s_axi_awprot \ + s_axi_awready \ + s_axi_wvalid \ + s_axi_wdata \ + s_axi_wstrb \ + s_axi_wready \ + s_axi_bvalid \ + s_axi_bresp \ + s_axi_bready \ + s_axi_arvalid \ + s_axi_araddr \ + s_axi_arprot \ + s_axi_arready \ + s_axi_rvalid \ + s_axi_rdata \ + s_axi_rresp \ + s_axi_rready} \ + xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] + + ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] + ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] + ipx::add_memory_map {s_axi} [ipx::current_core] + set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] + ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] + set_property range {65536} [ipx::get_address_blocks axi_lite \ + -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] + ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces s_axi_aclk \ + -of_objects [ipx::current_core]] + set_property value s_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \ + -of_objects [ipx::get_bus_interfaces s_axi_aclk \ + -of_objects [ipx::current_core]]] + + ipx::infer_bus_interfaces xilinx.com:interface:clock_rtl:1.0 [ipx::current_core] + ipx::infer_bus_interfaces xilinx.com:interface:reset_rtl:1.0 [ipx::current_core] + ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] + ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] } proc adi_ip_properties_lite {ip_name} { diff --git a/library/util_adcfifo/util_adcfifo_constr.xdc b/library/util_adcfifo/util_adcfifo_constr.xdc index d0f3cfbaa..2e7ab2b1c 100644 --- a/library/util_adcfifo/util_adcfifo_constr.xdc +++ b/library/util_adcfifo/util_adcfifo_constr.xdc @@ -1,6 +1,8 @@ -set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports adc_clk]] -set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports dma_clk]] - +set_property shreg_extract no [get_cells -hier -filter {name =~ *adc_xfer_req_m*}] +set_property shreg_extract no [get_cells -hier -filter {name =~ *dma_waddr_rel_t*}] +set_false_path -from [get_cells -hier -filter {name =~ *adc_waddr_rel_t_reg* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *dma_waddr_rel_t_m_reg[0]* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hier -filter {name =~ *adc_waddr_rel_reg* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *dma_waddr_rel_reg* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *adc_xfer_req_m_reg[0]* && IS_SEQUENTIAL}] diff --git a/library/util_clkdiv/Makefile b/library/util_clkdiv/Makefile new file mode 100644 index 000000000..b80a36fd4 --- /dev/null +++ b/library/util_clkdiv/Makefile @@ -0,0 +1,46 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS := util_clkdiv_ip.tcl +M_DEPS += ../scripts/adi_env.tcl +M_DEPS += ../scripts/adi_ip.tcl +M_DEPS += util_clkdiv.v + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.cache +M_FLIST += *.data +M_FLIST += *.xpr +M_FLIST += *.log +M_FLIST += component.xml +M_FLIST += *.jou +M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim +M_FLIST += .Xil + + + +.PHONY: all clean clean-all +all: util_clkdiv.xpr + + +clean:clean-all + + +clean-all: + rm -rf $(M_FLIST) + + +util_clkdiv.xpr: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) util_clkdiv_ip.tcl >> util_clkdiv_ip.log 2>&1 + +#################################################################################### +#################################################################################### diff --git a/library/util_clkdiv/util_clkdiv.v b/library/util_clkdiv/util_clkdiv.v new file mode 100644 index 000000000..712375621 --- /dev/null +++ b/library/util_clkdiv/util_clkdiv.v @@ -0,0 +1,64 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module util_clkdiv ( + clk, + clk_out + ); + + input clk; + output clk_out; + + BUFR #( + .BUFR_DIVIDE("4"), + .SIM_DEVICE("7SERIES") + ) clk_divide ( + .I(clk), + .CE(1), + .CLR(0), + .O(clk_div_s)); + + BUFG i_div_clk_gbuf ( + .I (clk_div_s), + .O (clk_out)); + +endmodule // util_clkdiv + diff --git a/library/util_clkdiv/util_clkdiv_ip.tcl b/library/util_clkdiv/util_clkdiv_ip.tcl new file mode 100644 index 000000000..66286de2a --- /dev/null +++ b/library/util_clkdiv/util_clkdiv_ip.tcl @@ -0,0 +1,10 @@ +source ../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create util_clkdiv +adi_ip_files util_clkdiv [list \ +"util_clkdiv.v" ] + +adi_ip_properties_lite util_clkdiv + +ipx::save_core [ipx::current_core] diff --git a/library/util_dacfifo/util_dacfifo.v b/library/util_dacfifo/util_dacfifo.v index a229aeacf..16e183acb 100644 --- a/library/util_dacfifo/util_dacfifo.v +++ b/library/util_dacfifo/util_dacfifo.v @@ -55,10 +55,14 @@ module util_dacfifo ( dac_clk, dac_valid, - dac_data + dac_data, + dac_xfer_out, + + dac_fifo_bypass ); // depth of the FIFO + parameter ADDRESS_WIDTH = 6; parameter DATA_WIDTH = 128; @@ -79,30 +83,36 @@ module util_dacfifo ( input dac_clk; input dac_valid; output [(DATA_WIDTH-1):0] dac_data; + output dac_xfer_out; + + input dac_fifo_bypass; // internal registers reg [(ADDRESS_WIDTH-1):0] dma_waddr = 'b0; reg [(ADDRESS_WIDTH-1):0] dma_lastaddr = 'b0; - reg [(ADDRESS_WIDTH-1):0] dma_lastaddr_d = 'b0; - reg [(ADDRESS_WIDTH-1):0] dma_lastaddr_2d = 'b0; + reg [(ADDRESS_WIDTH-1):0] dac_lastaddr_d = 'b0; + reg [(ADDRESS_WIDTH-1):0] dac_lastaddr_2d = 'b0; reg dma_xfer_req_ff = 1'b0; - reg dma_ready = 1'b0; + reg dma_ready_d = 1'b0; reg [(ADDRESS_WIDTH-1):0] dac_raddr = 'b0; - reg [(DATA_WIDTH-1):0] dac_data = 'b0; + reg dma_xfer_out = 1'b0; + reg [ 2:0] dac_xfer_out_m = 3'b0; // internal wires + wire dma_wren; wire [(DATA_WIDTH-1):0] dac_data_s; // write interface + always @(posedge dma_clk) begin if(dma_rst == 1'b1) begin - dma_ready <= 1'b0; + dma_ready_d <= 1'b0; dma_xfer_req_ff <= 1'b0; end else begin - dma_ready <= 1'b1; // Fifo is always ready + dma_ready_d <= 1'b1; // Fifo is always ready dma_xfer_req_ff <= dma_xfer_req; end end @@ -111,40 +121,44 @@ module util_dacfifo ( if(dma_rst == 1'b1) begin dma_waddr <= 'b0; dma_lastaddr <= 'b0; + dma_xfer_out <= 1'b0; end else begin if (dma_valid && dma_xfer_req) begin dma_waddr <= dma_waddr + 1; + dma_xfer_out <= 1'b0; end if (dma_xfer_last) begin dma_lastaddr <= dma_waddr; dma_waddr <= 'b0; + dma_xfer_out <= 1'b1; end end end assign dma_wren = dma_valid & dma_xfer_req; - // read interface - // sync lastaddr to dac clock domain + always @(posedge dac_clk) begin - dma_lastaddr_d <= dma_lastaddr; - dma_lastaddr_2d <= dma_lastaddr_d; + dac_lastaddr_d <= dma_lastaddr; + dac_lastaddr_2d <= dac_lastaddr_d; + dac_xfer_out_m <= {dac_xfer_out_m[1:0], dma_xfer_out}; end + assign dac_xfer_out = dac_xfer_out_m[2]; + // generate dac read address + always @(posedge dac_clk) begin if(dac_valid == 1'b1) begin - if (dma_lastaddr_2d == 'h0) begin + if (dac_lastaddr_2d == 'h0) begin dac_raddr <= dac_raddr + 1; end else begin - dac_raddr <= (dac_raddr < dma_lastaddr_2d) ? (dac_raddr + 1) : 'b0; + dac_raddr <= (dac_raddr < dac_lastaddr_2d) ? (dac_raddr + 1) : 'b0; end end - dac_data <= dac_data_s; end - // memory instantiation ad_mem #( @@ -159,5 +173,10 @@ module util_dacfifo ( .addrb (dac_raddr), .doutb (dac_data_s)); + // output logic + + assign dac_data = (dac_fifo_bypass) ? dma_data : dac_data_s; + assign dma_ready = (dac_fifo_bypass) ? dac_valid : dma_ready_d; + endmodule diff --git a/library/util_dacfifo/util_dacfifo_constr.xdc b/library/util_dacfifo/util_dacfifo_constr.xdc new file mode 100644 index 000000000..670b91327 --- /dev/null +++ b/library/util_dacfifo/util_dacfifo_constr.xdc @@ -0,0 +1,7 @@ + +set_property shreg_extract no [get_cells -hier -filter {name =~ *dac_lastaddr_d*}] +set_property shreg_extract no [get_cells -hier -filter {name =~ *dac_xfer_out_m*}] + +set_false_path -from [get_cells -hier -filter {name =~ *dma_lastaddr_reg* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *dac_lastaddr_d_reg* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *dac_xfer_out_m_reg[0]* && IS_SEQUENTIAL}] + diff --git a/library/util_dacfifo/util_dacfifo_ip.tcl b/library/util_dacfifo/util_dacfifo_ip.tcl index 5bb5d6c1d..50b7f1a08 100644 --- a/library/util_dacfifo/util_dacfifo_ip.tcl +++ b/library/util_dacfifo/util_dacfifo_ip.tcl @@ -6,9 +6,12 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl adi_ip_create util_dacfifo adi_ip_files util_dacfifo [list \ "$ad_hdl_dir/library/common/ad_mem.v" \ - "util_dacfifo.v" ] + "util_dacfifo.v" \ + "util_dacfifo_constr.xdc"] adi_ip_properties_lite util_dacfifo +adi_ip_constraints util_dacfifo [list \ + "util_dacfifo_constr.xdc" ] ipx::remove_all_bus_interface [ipx::current_core] ipx::save_core [ipx::current_core] diff --git a/library/util_gmii_to_rgmii/util_gmii_to_rgmii_ip.tcl b/library/util_gmii_to_rgmii/util_gmii_to_rgmii_ip.tcl index 48710bf7c..be06aa5d8 100644 --- a/library/util_gmii_to_rgmii/util_gmii_to_rgmii_ip.tcl +++ b/library/util_gmii_to_rgmii/util_gmii_to_rgmii_ip.tcl @@ -15,9 +15,8 @@ adi_ip_constraints util_gmii_to_rgmii [list \ "util_gmii_to_rgmii_constr.xdc" ] ipx::infer_bus_interface {gmii_tx_clk gmii_txd gmii_tx_en gmii_tx_er gmii_crs gmii_col gmii_rx_clk gmii_rxd gmii_rx_dv gmii_rx_er} xilinx.com:interface:gmii_rtl:1.0 [ipx::current_core] -set_property name {gmii} [ipx::get_bus_interface gmii_rtl_1 [ipx::current_core]] +set_property name {gmii} [ipx::get_bus_interface gmii_1 [ipx::current_core]] ipx::infer_bus_interface {rgmii_td rgmii_tx_ctl rgmii_txc rgmii_rd rgmii_rx_ctl rgmii_rxc} xilinx.com:interface:rgmii_rtl:1.0 [ipx::current_core] -set_property value ACTIVE_HIGH [ipx::get_bus_parameters POLARITY -of_objects [ipx::get_bus_interfaces reset -of_objects [ipx::current_core]]] set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.IODELAY_CTRL')) = 1} \ [ipx::get_ports idelayctrl_clk -of_objects [ipx::current_core]] diff --git a/projects/ad6676evb/common/ad6676evb_bd.tcl b/projects/ad6676evb/common/ad6676evb_bd.tcl index ed30915dc..11d73bd7f 100644 --- a/projects/ad6676evb/common/ad6676evb_bd.tcl +++ b/projects/ad6676evb/common/ad6676evb_bd.tcl @@ -11,7 +11,7 @@ create_bd_port -dir I -from 1 -to 0 rx_data_n set axi_ad6676_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad6676:1.0 axi_ad6676_core] -set axi_ad6676_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad6676_jesd] +set axi_ad6676_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad6676_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad6676_jesd set_property -dict [list CONFIG.C_LANES {2}] $axi_ad6676_jesd diff --git a/projects/ad6676evb/vc707/Makefile b/projects/ad6676evb/vc707/Makefile index 789699d30..5e0c9487c 100644 --- a/projects/ad6676evb/vc707/Makefile +++ b/projects/ad6676evb/vc707/Makefile @@ -34,6 +34,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/ad6676evb/zc706/Makefile b/projects/ad6676evb/zc706/Makefile index a6cbba810..b11811429 100644 --- a/projects/ad6676evb/zc706/Makefile +++ b/projects/ad6676evb/zc706/Makefile @@ -36,6 +36,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/ad9265_fmc/zc706/Makefile b/projects/ad9265_fmc/zc706/Makefile index d1dc365b9..9ad95e317 100644 --- a/projects/ad9265_fmc/zc706/Makefile +++ b/projects/ad9265_fmc/zc706/Makefile @@ -34,6 +34,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/ad9434_fmc/zc706/Makefile b/projects/ad9434_fmc/zc706/Makefile index 3f18dcb7a..70d247f5c 100644 --- a/projects/ad9434_fmc/zc706/Makefile +++ b/projects/ad9434_fmc/zc706/Makefile @@ -34,6 +34,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/ad9467_fmc/kc705/Makefile b/projects/ad9467_fmc/kc705/Makefile index b9b6a3516..887838189 100644 --- a/projects/ad9467_fmc/kc705/Makefile +++ b/projects/ad9467_fmc/kc705/Makefile @@ -32,6 +32,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/ad9467_fmc/zed/Makefile b/projects/ad9467_fmc/zed/Makefile index a08832b57..0eee2b11c 100644 --- a/projects/ad9467_fmc/zed/Makefile +++ b/projects/ad9467_fmc/zed/Makefile @@ -36,6 +36,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/ad9739a_fmc/zc706/Makefile b/projects/ad9739a_fmc/zc706/Makefile index f9e98a2b3..481327975 100644 --- a/projects/ad9739a_fmc/zc706/Makefile +++ b/projects/ad9739a_fmc/zc706/Makefile @@ -33,6 +33,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/adv7511/ac701/Makefile b/projects/adv7511/ac701/Makefile index 16e4a1588..0dfca3289 100644 --- a/projects/adv7511/ac701/Makefile +++ b/projects/adv7511/ac701/Makefile @@ -32,6 +32,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/adv7511/common/adv7511_bd.tcl b/projects/adv7511/common/adv7511_bd.tcl index 1d94c1e4f..51b9c2ab3 100755 --- a/projects/adv7511/common/adv7511_bd.tcl +++ b/projects/adv7511/common/adv7511_bd.tcl @@ -31,7 +31,7 @@ set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_hdmi_dma # audio peripherals -set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen] +set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_audio_clkgen] set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen diff --git a/projects/adv7511/kc705/Makefile b/projects/adv7511/kc705/Makefile index 970c44988..69dea3d47 100644 --- a/projects/adv7511/kc705/Makefile +++ b/projects/adv7511/kc705/Makefile @@ -32,6 +32,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/adv7511/kc705/system_bd.tcl b/projects/adv7511/kc705/system_bd.tcl index fca785858..56dcc8b7c 100644 --- a/projects/adv7511/kc705/system_bd.tcl +++ b/projects/adv7511/kc705/system_bd.tcl @@ -4,3 +4,5 @@ source $ad_hdl_dir/projects/adv7511/common/adv7511_bd.tcl set_property -dict [list CONFIG.c_m_axi_mm2s_data_width {512}] $axi_hdmi_dma set_property -dict [list CONFIG.c_m_axis_mm2s_tdata_width {64}] $axi_hdmi_dma +set_property -dict [list CONFIG.S04_HAS_REGSLICE {4}] [get_bd_cells axi_mem_interconnect] + diff --git a/projects/adv7511/kcu105/Makefile b/projects/adv7511/kcu105/Makefile index 7793cadb1..9a09b9f4f 100644 --- a/projects/adv7511/kcu105/Makefile +++ b/projects/adv7511/kcu105/Makefile @@ -32,6 +32,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/adv7511/mitx045/Makefile b/projects/adv7511/mitx045/Makefile index 3c03e7595..80c65e379 100644 --- a/projects/adv7511/mitx045/Makefile +++ b/projects/adv7511/mitx045/Makefile @@ -31,6 +31,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/adv7511/vc707/Makefile b/projects/adv7511/vc707/Makefile index 9fd0f4623..b347dcd33 100644 --- a/projects/adv7511/vc707/Makefile +++ b/projects/adv7511/vc707/Makefile @@ -32,6 +32,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/adv7511/zc702/Makefile b/projects/adv7511/zc702/Makefile index 6c520c266..876158ecd 100644 --- a/projects/adv7511/zc702/Makefile +++ b/projects/adv7511/zc702/Makefile @@ -29,6 +29,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/adv7511/zc706/Makefile b/projects/adv7511/zc706/Makefile index 3c4655c04..d00baa5e9 100644 --- a/projects/adv7511/zc706/Makefile +++ b/projects/adv7511/zc706/Makefile @@ -29,6 +29,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/adv7511/zed/Makefile b/projects/adv7511/zed/Makefile index d0360c3ce..26d233c0b 100644 --- a/projects/adv7511/zed/Makefile +++ b/projects/adv7511/zed/Makefile @@ -31,6 +31,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/arradio/c5soc/system_bd.qsys b/projects/arradio/c5soc/system_bd.qsys index ec86e336c..ff3917be9 100644 --- a/projects/arradio/c5soc/system_bd.qsys +++ b/projects/arradio/c5soc/system_bd.qsys @@ -113,6 +113,38 @@ type = "String"; } } + element system_bd + { + datum _originalDeviceFamily + { + value = "Cyclone V"; + type = "String"; + } + } + element system_bd + { + datum _originalDeviceFamily + { + value = "Cyclone V"; + type = "String"; + } + } + element system_bd + { + datum _originalDeviceFamily + { + value = "Cyclone V"; + type = "String"; + } + } + element system_bd + { + datum _originalDeviceFamily + { + value = "Cyclone V"; + type = "String"; + } + } } ]]> @@ -176,6 +208,21 @@ internal="c5soc.sys_hps_hps_io" type="conduit" dir="end" /> + + + - + - + @@ -237,6 +284,9 @@ + + + diff --git a/projects/arradio/c5soc/system_project.tcl b/projects/arradio/c5soc/system_project.tcl index a00f71e25..9c3eb0d9a 100644 --- a/projects/arradio/c5soc/system_project.tcl +++ b/projects/arradio/c5soc/system_project.tcl @@ -96,5 +96,18 @@ set_location_assignment PIN_H12 -to spi_clk set_location_assignment PIN_H13 -to spi_mosi set_location_assignment PIN_G11 -to spi_miso +set_instance_assignment -name IO_STANDARD "2.5 V" -to scl +set_instance_assignment -name IO_STANDARD "2.5 V" -to sda +set_instance_assignment -name IO_STANDARD "2.5 V" -to ga0 +set_instance_assignment -name IO_STANDARD "2.5 V" -to ga1 + +set_location_assignment PIN_F15 -to scl +set_location_assignment PIN_G13 -to sda +set_location_assignment PIN_C7 -to ga0 +set_location_assignment PIN_H14 -to ga1 + +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to scl +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sda + execute_flow -compile diff --git a/projects/arradio/c5soc/system_top.v b/projects/arradio/c5soc/system_top.v index e3ee25a18..47f5af1f2 100644 --- a/projects/arradio/c5soc/system_top.v +++ b/projects/arradio/c5soc/system_top.v @@ -140,6 +140,13 @@ module system_top ( ad9361_enable, ad9361_txnrx, + // iic interface + + scl, + sda, + ga0, + ga1, + // spi spi_csn, @@ -248,6 +255,14 @@ module system_top ( output ad9361_enable; output ad9361_txnrx; + // iic interface + + inout scl; + inout sda; + output ga0; + output ga1; + + // spi interface output spi_csn; @@ -300,14 +315,26 @@ module system_top ( wire vid_h_sync; wire [7:0] vid_r,vid_g,vid_b; + wire i2c0_out_data; + wire i2c0_sda; + wire i2c0_out_clk; + wire i2c0_scl_in_clk; + // defaults - + assign vga_clk = vga_pixel_clock; assign vga_blank_n = 1'b1; assign vga_sync_n = 1'b0; assign vga_hs = vid_h_sync; assign vga_vs = vid_v_sync; assign {vga_b,vga_g,vga_r} = {vid_b,vid_g,vid_r}; + assign ga0 = 1'b0; + assign ga1 = 1'b0; + + +ALT_IOBUF scl_iobuf (.i(1'b0), .oe(i2c0_out_clk), .o(i2c0_scl_in_clk), .io(scl)); // +ALT_IOBUF sda_iobuf (.i(1'b0), .oe(i2c0_out_data), .o(i2c0_sda), .io(sda)); // + // instantiations @@ -437,6 +464,10 @@ module system_top ( .vga_clock_video_output_clocked_video_vid_f (), .vga_clock_video_output_clocked_video_vid_h (), .vga_clock_video_output_clocked_video_vid_v (), + .sys_hps_i2c0_out_data(i2c0_out_data), + .sys_hps_i2c0_sda(i2c0_sda), + .sys_hps_i2c0_clk_clk(i2c0_out_clk), + .sys_hps_i2c0_scl_in_clk(i2c0_scl_in_clk), .gpio_external_connection_export ({ad9361_resetb, ad9361_en_agc, ad9361_sync, ad9361_enable, ad9361_txnrx}) ); diff --git a/projects/arradio/common/arradio_bd.qsys b/projects/arradio/common/arradio_bd.qsys index ffbb1cae5..52bcd0e88 100755 --- a/projects/arradio/common/arradio_bd.qsys +++ b/projects/arradio/common/arradio_bd.qsys @@ -86,6 +86,14 @@ type = "String"; } } + element arradio_bd + { + datum _originalDeviceFamily + { + value = "Cyclone V"; + type = "String"; + } + } element axi_ad9361 { datum _sortIndex diff --git a/projects/cftl_cip/zed/Makefile b/projects/cftl_cip/zed/Makefile index 33231bac1..687b6a0e0 100644 --- a/projects/cftl_cip/zed/Makefile +++ b/projects/cftl_cip/zed/Makefile @@ -36,6 +36,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/cftl_std/zed/Makefile b/projects/cftl_std/zed/Makefile index ad3de3c44..55923a3eb 100644 --- a/projects/cftl_std/zed/Makefile +++ b/projects/cftl_std/zed/Makefile @@ -33,6 +33,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/cn0363/zed/Makefile b/projects/cn0363/zed/Makefile index 7d982d5dd..c9f80d8c5 100644 --- a/projects/cn0363/zed/Makefile +++ b/projects/cn0363/zed/Makefile @@ -43,6 +43,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/common/a10gx/a10gx_system_assign.tcl b/projects/common/a10gx/a10gx_system_assign.tcl index 106b99b48..145c90666 100755 --- a/projects/common/a10gx/a10gx_system_assign.tcl +++ b/projects/common/a10gx/a10gx_system_assign.tcl @@ -2,13 +2,14 @@ # device settings set_global_assignment -name FAMILY "Arria 10" -set_global_assignment -name DEVICE 10AX115S3F45I2SGE2 +set_global_assignment -name DEVICE 10AX115S3F45E2SGE3 # clocks and resets -set_location_assignment PIN_BD32 -to sys_clk +set_location_assignment PIN_AR36 -to sys_clk +set_location_assignment PIN_AR37 -to "sys_clk(n)" set_location_assignment PIN_BD27 -to sys_resetn -set_instance_assignment -name IO_STANDARD "1.8 V" -to sys_clk +set_instance_assignment -name IO_STANDARD LVDS -to sys_clk set_instance_assignment -name IO_STANDARD "1.8 V" -to sys_resetn # ddr3 @@ -170,61 +171,61 @@ set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to eth_ref_clk # leds -set_location_assignment PIN_L28 -to gpio_bd[0] ; ## led-g0-d10 -set_location_assignment PIN_K26 -to gpio_bd[1] ; ## led-g1-d9 -set_location_assignment PIN_K25 -to gpio_bd[2] ; ## led-g2-d8 -set_location_assignment PIN_L25 -to gpio_bd[3] ; ## led-g3-d7 -set_location_assignment PIN_J24 -to gpio_bd[4] ; ## led-g4-d6 -set_location_assignment PIN_A19 -to gpio_bd[5] ; ## led-g5-d5 -set_location_assignment PIN_C18 -to gpio_bd[6] ; ## led-g6-d4 -set_location_assignment PIN_D18 -to gpio_bd[7] ; ## led-g7-d3 -set_location_assignment PIN_L27 -to gpio_bd[8] ; ## led-r0-d10 -set_location_assignment PIN_J26 -to gpio_bd[9] ; ## led-r1-d9 -set_location_assignment PIN_K24 -to gpio_bd[10] ; ## led-r2-d8 -set_location_assignment PIN_L23 -to gpio_bd[11] ; ## led-r3-d7 -set_location_assignment PIN_B20 -to gpio_bd[12] ; ## led-r4-d6 -set_location_assignment PIN_C19 -to gpio_bd[13] ; ## led-r5-d5 -set_location_assignment PIN_D19 -to gpio_bd[14] ; ## led-r6-d4 -set_location_assignment PIN_M23 -to gpio_bd[15] ; ## led-r7-d3 -set_location_assignment PIN_A24 -to gpio_bd[16] ; ## dipsw0 -set_location_assignment PIN_B23 -to gpio_bd[17] ; ## dipsw1 -set_location_assignment PIN_A23 -to gpio_bd[18] ; ## dipsw2 -set_location_assignment PIN_B22 -to gpio_bd[19] ; ## dipsw3 -set_location_assignment PIN_A22 -to gpio_bd[20] ; ## dipsw4 -set_location_assignment PIN_B21 -to gpio_bd[21] ; ## dipsw5 -set_location_assignment PIN_C21 -to gpio_bd[22] ; ## dipsw6 -set_location_assignment PIN_A20 -to gpio_bd[23] ; ## dipsw7 -set_location_assignment PIN_T12 -to gpio_bd[24] ; ## pb0-s3 -set_location_assignment PIN_U12 -to gpio_bd[25] ; ## pb1-s2 -set_location_assignment PIN_U11 -to gpio_bd[26] ; ## pb2-s1 +set_location_assignment PIN_L28 -to gpio_bd_o[0] ; ## led-g0-d10 +set_location_assignment PIN_K26 -to gpio_bd_o[1] ; ## led-g1-d9 +set_location_assignment PIN_K25 -to gpio_bd_o[2] ; ## led-g2-d8 +set_location_assignment PIN_L25 -to gpio_bd_o[3] ; ## led-g3-d7 +set_location_assignment PIN_J24 -to gpio_bd_o[4] ; ## led-g4-d6 +set_location_assignment PIN_A19 -to gpio_bd_o[5] ; ## led-g5-d5 +set_location_assignment PIN_C18 -to gpio_bd_o[6] ; ## led-g6-d4 +set_location_assignment PIN_D18 -to gpio_bd_o[7] ; ## led-g7-d3 +set_location_assignment PIN_L27 -to gpio_bd_o[8] ; ## led-r0-d10 +set_location_assignment PIN_J26 -to gpio_bd_o[9] ; ## led-r1-d9 +set_location_assignment PIN_K24 -to gpio_bd_o[10] ; ## led-r2-d8 +set_location_assignment PIN_L23 -to gpio_bd_o[11] ; ## led-r3-d7 +set_location_assignment PIN_B20 -to gpio_bd_o[12] ; ## led-r4-d6 +set_location_assignment PIN_C19 -to gpio_bd_o[13] ; ## led-r5-d5 +set_location_assignment PIN_D19 -to gpio_bd_o[14] ; ## led-r6-d4 +set_location_assignment PIN_M23 -to gpio_bd_o[15] ; ## led-r7-d3 +set_location_assignment PIN_A24 -to gpio_bd_i[0] ; ## dipsw0 +set_location_assignment PIN_B23 -to gpio_bd_i[1] ; ## dipsw1 +set_location_assignment PIN_A23 -to gpio_bd_i[2] ; ## dipsw2 +set_location_assignment PIN_B22 -to gpio_bd_i[3] ; ## dipsw3 +set_location_assignment PIN_A22 -to gpio_bd_i[4] ; ## dipsw4 +set_location_assignment PIN_B21 -to gpio_bd_i[5] ; ## dipsw5 +set_location_assignment PIN_C21 -to gpio_bd_i[6] ; ## dipsw6 +set_location_assignment PIN_A20 -to gpio_bd_i[7] ; ## dipsw7 +set_location_assignment PIN_T12 -to gpio_bd_i[8] ; ## pb0-s3 +set_location_assignment PIN_U12 -to gpio_bd_i[9] ; ## pb1-s2 +set_location_assignment PIN_U11 -to gpio_bd_i[10] ; ## pb2-s1 -set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[0] -set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[1] -set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[2] -set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[3] -set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[4] -set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[5] -set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[6] -set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[7] -set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[8] -set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[9] -set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[10] -set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[11] -set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[12] -set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[13] -set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[14] -set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[15] -set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[16] -set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[17] -set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[18] -set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[19] -set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[20] -set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[21] -set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[22] -set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[23] -set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[24] -set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[25] -set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[26] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[4] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[5] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[6] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[7] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[8] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[9] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[10] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[11] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[12] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[13] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[14] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[15] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[4] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[5] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[6] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[7] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[8] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[9] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[10] # globals diff --git a/projects/common/a10gx/a10gx_system_bd.qsys b/projects/common/a10gx/a10gx_system_bd.qsys index c49ad0640..9cb193b00 100644 --- a/projects/common/a10gx/a10gx_system_bd.qsys +++ b/projects/common/a10gx/a10gx_system_bd.qsys @@ -601,7 +601,7 @@ } ]]> - + @@ -733,7 +733,7 @@ - + @@ -1862,14 +1862,14 @@ - + $${FILENAME}_sys_ddr3_cntrl - + @@ -1922,7 +1922,7 @@ - + @@ -1968,7 +1968,7 @@ - + ]]> @@ -2046,7 +2046,7 @@ - + - + - fmcjesdadc1_a5soc.qpf + @@ -247,7 +239,7 @@ internal="sys_rst_out.out_reset" type="reset" dir="start" /> - + @@ -255,7 +247,7 @@ @@ -272,7 +264,7 @@ - + @@ -289,7 +281,7 @@ @@ -304,7 +296,7 @@ - + @@ -652,6 +644,7 @@ + @@ -808,6 +801,7 @@ + @@ -833,7 +827,7 @@ @@ -841,7 +835,7 @@ $${FILENAME}_sys_int_mem @@ -849,7 +843,7 @@ - ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 + ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 @@ -867,14 +861,14 @@ - + - + @@ -884,7 +878,7 @@ @@ -894,7 +888,7 @@ @@ -903,7 +897,7 @@ @@ -912,7 +906,7 @@ @@ -921,7 +915,7 @@ @@ -930,7 +924,7 @@ @@ -939,172 +933,172 @@ diff --git a/projects/common/ac701/ac701_system_bd.tcl b/projects/common/ac701/ac701_system_bd.tcl index 32439a5a4..2ee349106 100644 --- a/projects/common/ac701/ac701_system_bd.tcl +++ b/projects/common/ac701/ac701_system_bd.tcl @@ -62,7 +62,7 @@ set_property -dict [list CONFIG.C_ECC {0}] $sys_dlmb_cntlr set sys_ilmb_cntlr [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 sys_ilmb_cntlr] set_property -dict [list CONFIG.C_ECC {0}] $sys_ilmb_cntlr -set sys_lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.2 sys_lmb_bram] +set sys_lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.3 sys_lmb_bram] set_property -dict [list CONFIG.Memory_Type {True_Dual_Port_RAM} CONFIG.use_bram_block {BRAM_Controller}] $sys_lmb_bram # instance: microblaze- mdm @@ -76,14 +76,14 @@ set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 s # instance: ddr (mig) -set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.3 axi_ddr_cntrl] +set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.4 axi_ddr_cntrl] set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl]]] file copy -force $ad_hdl_dir/projects/common/ac701/ac701_system_mig.prj "$axi_ddr_cntrl_dir/" set_property -dict [list CONFIG.XML_INPUT_FILE {ac701_system_mig.prj}] $axi_ddr_cntrl # instance: default peripherals -set sys_ethernet_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_ethernet_clkgen] +set sys_ethernet_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_ethernet_clkgen] set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_ethernet_clkgen set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {125.000}] $sys_ethernet_clkgen diff --git a/projects/common/c5soc/c5soc_system_bd.qsys b/projects/common/c5soc/c5soc_system_bd.qsys index dab5f0d2f..8f6673b95 100644 --- a/projects/common/c5soc/c5soc_system_bd.qsys +++ b/projects/common/c5soc/c5soc_system_bd.qsys @@ -39,7 +39,7 @@ } datum sopceditor_expanded { - value = "0"; + value = "1"; type = "boolean"; } } @@ -107,7 +107,7 @@ } datum sopceditor_expanded { - value = "0"; + value = "1"; type = "boolean"; } } @@ -419,6 +419,17 @@ internal="sys_hps.hps_io" type="conduit" dir="end" /> + + + - + @@ -721,8 +732,8 @@ - - + + diff --git a/projects/common/kc705/kc705_system_bd.tcl b/projects/common/kc705/kc705_system_bd.tcl index 50d907d5b..f762c2b5d 100644 --- a/projects/common/kc705/kc705_system_bd.tcl +++ b/projects/common/kc705/kc705_system_bd.tcl @@ -68,7 +68,7 @@ set_property -dict [list CONFIG.C_ECC {0}] $sys_dlmb_cntlr set sys_ilmb_cntlr [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 sys_ilmb_cntlr] set_property -dict [list CONFIG.C_ECC {0}] $sys_ilmb_cntlr -set sys_lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.2 sys_lmb_bram] +set sys_lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.3 sys_lmb_bram] set_property -dict [list CONFIG.Memory_Type {True_Dual_Port_RAM} CONFIG.use_bram_block {BRAM_Controller}] $sys_lmb_bram # instance: microblaze- mdm @@ -82,7 +82,7 @@ set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 s # instance: ddr (mig) -set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.3 axi_ddr_cntrl] +set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.4 axi_ddr_cntrl] set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl]]] file copy -force $ad_hdl_dir/projects/common/kc705/kc705_system_mig.prj "$axi_ddr_cntrl_dir/" set_property -dict [list CONFIG.XML_INPUT_FILE {kc705_system_mig.prj}] $axi_ddr_cntrl diff --git a/projects/common/kcu105/kcu105_system_bd.tcl b/projects/common/kcu105/kcu105_system_bd.tcl index 512058517..715b597e0 100644 --- a/projects/common/kcu105/kcu105_system_bd.tcl +++ b/projects/common/kcu105/kcu105_system_bd.tcl @@ -66,7 +66,7 @@ set_property -dict [list CONFIG.C_ECC {0}] $sys_dlmb_cntlr set sys_ilmb_cntlr [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 sys_ilmb_cntlr] set_property -dict [list CONFIG.C_ECC {0}] $sys_ilmb_cntlr -set sys_lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.2 sys_lmb_bram] +set sys_lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.3 sys_lmb_bram] set_property -dict [list CONFIG.Memory_Type {True_Dual_Port_RAM} CONFIG.use_bram_block {BRAM_Controller}] $sys_lmb_bram # instance: microblaze- mdm @@ -80,32 +80,23 @@ set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 s # instance: ddr (mig) -set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig:7.1 axi_ddr_cntrl] -source $ad_hdl_dir/projects/common/kcu105/kcu105_system_mig.tcl +set axi_ddr_cntrl [ create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:1.1 axi_ddr_cntrl ] +set_property -dict [list CONFIG.C0_CLOCK_BOARD_INTERFACE {default_sysclk_300}] $axi_ddr_cntrl +set_property -dict [list CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram}] $axi_ddr_cntrl +set_property -dict [list CONFIG.RESET_BOARD_INTERFACE {reset}] $axi_ddr_cntrl +set_property -dict [list CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100}] $axi_ddr_cntrl +set_property -dict [list CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {200}] $axi_ddr_cntrl set axi_ddr_cntrl_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 axi_ddr_cntrl_rstgen] # instance: default peripherals -set axi_ethernet_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 axi_ethernet_clkgen] -set_property -dict [list CONFIG.PRIM_IN_FREQ {625}] $axi_ethernet_clkgen -set_property -dict [list CONFIG.PRIM_SOURCE {Differential_clock_capable_pin}] $axi_ethernet_clkgen -set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {125}] $axi_ethernet_clkgen -set_property -dict [list CONFIG.CLKOUT2_USED {true}] $axi_ethernet_clkgen -set_property -dict [list CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {312}] $axi_ethernet_clkgen -set_property -dict [list CONFIG.CLKOUT3_USED {true}] $axi_ethernet_clkgen -set_property -dict [list CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {625}] $axi_ethernet_clkgen -set_property -dict [list CONFIG.CLKOUT4_USED {false}] $axi_ethernet_clkgen -set_property -dict [list CONFIG.USE_LOCKED {true}] $axi_ethernet_clkgen -set_property -dict [list CONFIG.USE_RESET {false}] $axi_ethernet_clkgen - -set axi_ethernet_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 axi_ethernet_rstgen] -set axi_ethernet_idelayctrl [create_bd_cell -type ip -vlnv xilinx.com:ip:util_idelay_ctrl:1.0 axi_ethernet_idelayctrl] - set axi_ethernet [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_ethernet:7.0 axi_ethernet] -set_property -dict [list CONFIG.PHY_TYPE {SGMII}] $axi_ethernet -set_property -dict [list CONFIG.ENABLE_LVDS {true}] $axi_ethernet -set_property -dict [list CONFIG.SupportLevel {0}] $axi_ethernet +set_property -dict [list CONFIG.SupportLevel {1}] $axi_ethernet +set_property -dict [list CONFIG.ETHERNET_BOARD_INTERFACE {sgmii_lvds}] $axi_ethernet +set_property -dict [list CONFIG.MDIO_BOARD_INTERFACE {mdio_mdc}] $axi_ethernet +set_property -dict [list CONFIG.DIFFCLK_BOARD_INTERFACE {sgmii_phyclk}] $axi_ethernet +set_property -dict [list CONFIG.lvdsclkrate {625}] $axi_ethernet set_property -dict [list CONFIG.TXCSUM {Full}] $axi_ethernet set_property -dict [list CONFIG.RXCSUM {Full}] $axi_ethernet set_property -dict [list CONFIG.TXMEM {8k}] $axi_ethernet @@ -210,13 +201,12 @@ ad_connect c0_ddr4 axi_ddr_cntrl/C0_DDR4 ad_connect sys_clk axi_ddr_cntrl/C0_SYS_CLK ad_connect axi_ddr_cntrl/c0_ddr4_ui_clk_sync_rst sys_rstgen/ext_reset_in -ad_connect axi_ddr_cntrl/c0_ddr4_ui_clk_sync_rst axi_ethernet_rstgen/ext_reset_in ad_connect axi_ddr_cntrl/c0_ddr4_ui_clk_sync_rst axi_ddr_cntrl_rstgen/ext_reset_in ad_connect sys_mem_clk axi_ddr_cntrl_rstgen/slowest_sync_clk # defaults (ethernet) -ad_connect phy_clk axi_ethernet_clkgen/CLK_IN1_D +ad_connect phy_clk axi_ethernet/lvds_clk ad_connect mdio axi_ethernet/mdio ad_connect sgmii axi_ethernet/sgmii ad_connect axi_ethernet/s_axis_txd axi_ethernet_dma/M_AXIS_MM2S @@ -225,19 +215,10 @@ ad_connect axi_ethernet/m_axis_rxd axi_ethernet_dma/S_AXIS_S2MM ad_connect axi_ethernet/m_axis_rxs axi_ethernet_dma/S_AXIS_STS ad_connect phy_sd axi_ethernet/signal_detect ad_connect sys_cpu_resetn phy_rst_n -ad_connect axi_ethernet_clkgen/clk_out1 axi_ethernet/clk125m -ad_connect axi_ethernet_clkgen/clk_out1 axi_ethernet_rstgen/slowest_sync_clk -ad_connect axi_ethernet_clkgen/clk_out2 axi_ethernet/clk312 -ad_connect axi_ethernet_clkgen/clk_out3 axi_ethernet/clk625 -ad_connect axi_ethernet_clkgen/locked axi_ethernet/mmcm_locked -ad_connect axi_ethernet_rstgen/peripheral_reset axi_ethernet/rst_125 ad_connect axi_ethernet/axi_txd_arstn axi_ethernet_dma/mm2s_prmry_reset_out_n ad_connect axi_ethernet/axi_txc_arstn axi_ethernet_dma/mm2s_cntrl_reset_out_n ad_connect axi_ethernet/axi_rxd_arstn axi_ethernet_dma/s2mm_prmry_reset_out_n ad_connect axi_ethernet/axi_rxs_arstn axi_ethernet_dma/s2mm_sts_reset_out_n -ad_connect axi_ethernet_idelayctrl/rdy axi_ethernet/idelay_rdy_in -ad_connect axi_ethernet_idelayctrl/rst axi_ethernet_rstgen/peripheral_reset -ad_connect axi_ethernet_idelayctrl/ref_clk axi_ethernet_clkgen/clk_out3 # defaults (misc) @@ -274,6 +255,8 @@ ad_cpu_interconnect 0x44A70000 axi_spi create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ddr_interconnect set_property CONFIG.NUM_MI {1} [get_bd_cells axi_ddr_interconnect] set_property CONFIG.NUM_SI {1} [get_bd_cells axi_ddr_interconnect] +set_property CONFIG.S00_HAS_REGSLICE {4} [get_bd_cells axi_ddr_interconnect] +set_property CONFIG.S00_HAS_DATA_FIFO {1} [get_bd_cells axi_ddr_interconnect] ad_connect axi_ddr_interconnect/M00_AXI axi_ddr_cntrl/C0_DDR4_S_AXI ad_connect sys_mem_clk axi_ddr_interconnect/ACLK diff --git a/projects/common/kcu105/kcu105_system_constr.xdc b/projects/common/kcu105/kcu105_system_constr.xdc index fb6306582..1688c660e 100644 --- a/projects/common/kcu105/kcu105_system_constr.xdc +++ b/projects/common/kcu105/kcu105_system_constr.xdc @@ -3,26 +3,15 @@ set_property -dict {PACKAGE_PIN AN8 IOSTANDARD LVCMOS18} [get_ports sys_rst] -# clocks - -set_property -dict {PACKAGE_PIN P26 IOSTANDARD LVDS_25} [get_ports phy_clk_p] -set_property -dict {PACKAGE_PIN N26 IOSTANDARD LVDS_25} [get_ports phy_clk_n] - -# ethernet - -set_property -dict {PACKAGE_PIN L25 IOSTANDARD LVCMOS18} [get_ports mdio_mdc] -set_property -dict {PACKAGE_PIN H26 IOSTANDARD LVCMOS18} [get_ports mdio_mdio] -set_property -dict {PACKAGE_PIN J23 IOSTANDARD LVCMOS18} [get_ports phy_rst_n] -set_property -dict {PACKAGE_PIN N24 IOSTANDARD DIFF_HSTL_I_18} [get_ports phy_tx_p] -set_property -dict {PACKAGE_PIN M24 IOSTANDARD DIFF_HSTL_I_18} [get_ports phy_tx_n] -set_property -dict {PACKAGE_PIN P24 IOSTANDARD DIFF_HSTL_I_18} [get_ports phy_rx_p] -set_property -dict {PACKAGE_PIN P25 IOSTANDARD DIFF_HSTL_I_18} [get_ports phy_rx_n] - # uart set_property -dict {PACKAGE_PIN K26 IOSTANDARD LVCMOS18} [get_ports uart_sout] set_property -dict {PACKAGE_PIN G25 IOSTANDARD LVCMOS18} [get_ports uart_sin] +# ethernet (phy_rst_n automation cannot be used with axi_ethernet 7.0) + +set_property -dict {PACKAGE_PIN J23 IOSTANDARD LVCMOS18} [get_ports phy_rst_n] + # fan set_property -dict {PACKAGE_PIN AJ9 IOSTANDARD LVCMOS18} [get_ports fan_pwm] @@ -56,125 +45,11 @@ set_property -dict {PACKAGE_PIN J25 IOSTANDARD LVCMOS18} [get_ports iic_sda set_property -dict {PACKAGE_PIN AK17} [get_ports sys_clk_p] set_property -dict {PACKAGE_PIN AK16} [get_ports sys_clk_n] -set_property -dict {PACKAGE_PIN AH14} [get_ports ddr4_act_n] -set_property -dict {PACKAGE_PIN AE17} [get_ports ddr4_addr[0]] -set_property -dict {PACKAGE_PIN AH17} [get_ports ddr4_addr[1]] -set_property -dict {PACKAGE_PIN AE18} [get_ports ddr4_addr[2]] -set_property -dict {PACKAGE_PIN AJ15} [get_ports ddr4_addr[3]] -set_property -dict {PACKAGE_PIN AG16} [get_ports ddr4_addr[4]] -set_property -dict {PACKAGE_PIN AL17} [get_ports ddr4_addr[5]] -set_property -dict {PACKAGE_PIN AK18} [get_ports ddr4_addr[6]] -set_property -dict {PACKAGE_PIN AG17} [get_ports ddr4_addr[7]] -set_property -dict {PACKAGE_PIN AF18} [get_ports ddr4_addr[8]] -set_property -dict {PACKAGE_PIN AH19} [get_ports ddr4_addr[9]] -set_property -dict {PACKAGE_PIN AF15} [get_ports ddr4_addr[10]] -set_property -dict {PACKAGE_PIN AD19} [get_ports ddr4_addr[11]] -set_property -dict {PACKAGE_PIN AJ14} [get_ports ddr4_addr[12]] -set_property -dict {PACKAGE_PIN AG19} [get_ports ddr4_addr[13]] -set_property -dict {PACKAGE_PIN AD16} [get_ports ddr4_addr[14]] -set_property -dict {PACKAGE_PIN AG14} [get_ports ddr4_addr[15]] -set_property -dict {PACKAGE_PIN AF14} [get_ports ddr4_addr[16]] -set_property -dict {PACKAGE_PIN AF17} [get_ports ddr4_ba[0]] -set_property -dict {PACKAGE_PIN AL15} [get_ports ddr4_ba[1]] -set_property -dict {PACKAGE_PIN AG15} [get_ports ddr4_bg[0]] -set_property -dict {PACKAGE_PIN AE16} [get_ports ddr4_ck_p] -set_property -dict {PACKAGE_PIN AE15} [get_ports ddr4_ck_n] -set_property -dict {PACKAGE_PIN AD15} [get_ports ddr4_cke[0]] -set_property -dict {PACKAGE_PIN AL19} [get_ports ddr4_cs_n[0]] -set_property -dict {PACKAGE_PIN AD21} [get_ports ddr4_dm_n[0]] -set_property -dict {PACKAGE_PIN AE25} [get_ports ddr4_dm_n[1]] -set_property -dict {PACKAGE_PIN AJ21} [get_ports ddr4_dm_n[2]] -set_property -dict {PACKAGE_PIN AM21} [get_ports ddr4_dm_n[3]] -set_property -dict {PACKAGE_PIN AH26} [get_ports ddr4_dm_n[4]] -set_property -dict {PACKAGE_PIN AN26} [get_ports ddr4_dm_n[5]] -set_property -dict {PACKAGE_PIN AJ29} [get_ports ddr4_dm_n[6]] -set_property -dict {PACKAGE_PIN AL32} [get_ports ddr4_dm_n[7]] -set_property -dict {PACKAGE_PIN AE23} [get_ports ddr4_dq[0]] -set_property -dict {PACKAGE_PIN AG20} [get_ports ddr4_dq[1]] -set_property -dict {PACKAGE_PIN AF22} [get_ports ddr4_dq[2]] -set_property -dict {PACKAGE_PIN AF20} [get_ports ddr4_dq[3]] -set_property -dict {PACKAGE_PIN AE22} [get_ports ddr4_dq[4]] -set_property -dict {PACKAGE_PIN AD20} [get_ports ddr4_dq[5]] -set_property -dict {PACKAGE_PIN AG22} [get_ports ddr4_dq[6]] -set_property -dict {PACKAGE_PIN AE20} [get_ports ddr4_dq[7]] -set_property -dict {PACKAGE_PIN AJ24} [get_ports ddr4_dq[8]] -set_property -dict {PACKAGE_PIN AG24} [get_ports ddr4_dq[9]] -set_property -dict {PACKAGE_PIN AJ23} [get_ports ddr4_dq[10]] -set_property -dict {PACKAGE_PIN AF23} [get_ports ddr4_dq[11]] -set_property -dict {PACKAGE_PIN AH23} [get_ports ddr4_dq[12]] -set_property -dict {PACKAGE_PIN AF24} [get_ports ddr4_dq[13]] -set_property -dict {PACKAGE_PIN AH22} [get_ports ddr4_dq[14]] -set_property -dict {PACKAGE_PIN AG25} [get_ports ddr4_dq[15]] -set_property -dict {PACKAGE_PIN AL22} [get_ports ddr4_dq[16]] -set_property -dict {PACKAGE_PIN AL25} [get_ports ddr4_dq[17]] -set_property -dict {PACKAGE_PIN AM20} [get_ports ddr4_dq[18]] -set_property -dict {PACKAGE_PIN AK23} [get_ports ddr4_dq[19]] -set_property -dict {PACKAGE_PIN AK22} [get_ports ddr4_dq[20]] -set_property -dict {PACKAGE_PIN AL24} [get_ports ddr4_dq[21]] -set_property -dict {PACKAGE_PIN AL20} [get_ports ddr4_dq[22]] -set_property -dict {PACKAGE_PIN AL23} [get_ports ddr4_dq[23]] -set_property -dict {PACKAGE_PIN AM24} [get_ports ddr4_dq[24]] -set_property -dict {PACKAGE_PIN AN23} [get_ports ddr4_dq[25]] -set_property -dict {PACKAGE_PIN AN24} [get_ports ddr4_dq[26]] -set_property -dict {PACKAGE_PIN AP23} [get_ports ddr4_dq[27]] -set_property -dict {PACKAGE_PIN AP25} [get_ports ddr4_dq[28]] -set_property -dict {PACKAGE_PIN AN22} [get_ports ddr4_dq[29]] -set_property -dict {PACKAGE_PIN AP24} [get_ports ddr4_dq[30]] -set_property -dict {PACKAGE_PIN AM22} [get_ports ddr4_dq[31]] -set_property -dict {PACKAGE_PIN AH28} [get_ports ddr4_dq[32]] -set_property -dict {PACKAGE_PIN AK26} [get_ports ddr4_dq[33]] -set_property -dict {PACKAGE_PIN AK28} [get_ports ddr4_dq[34]] -set_property -dict {PACKAGE_PIN AM27} [get_ports ddr4_dq[35]] -set_property -dict {PACKAGE_PIN AJ28} [get_ports ddr4_dq[36]] -set_property -dict {PACKAGE_PIN AH27} [get_ports ddr4_dq[37]] -set_property -dict {PACKAGE_PIN AK27} [get_ports ddr4_dq[38]] -set_property -dict {PACKAGE_PIN AM26} [get_ports ddr4_dq[39]] -set_property -dict {PACKAGE_PIN AL30} [get_ports ddr4_dq[40]] -set_property -dict {PACKAGE_PIN AP29} [get_ports ddr4_dq[41]] -set_property -dict {PACKAGE_PIN AM30} [get_ports ddr4_dq[42]] -set_property -dict {PACKAGE_PIN AN28} [get_ports ddr4_dq[43]] -set_property -dict {PACKAGE_PIN AL29} [get_ports ddr4_dq[44]] -set_property -dict {PACKAGE_PIN AP28} [get_ports ddr4_dq[45]] -set_property -dict {PACKAGE_PIN AM29} [get_ports ddr4_dq[46]] -set_property -dict {PACKAGE_PIN AN27} [get_ports ddr4_dq[47]] -set_property -dict {PACKAGE_PIN AH31} [get_ports ddr4_dq[48]] -set_property -dict {PACKAGE_PIN AH32} [get_ports ddr4_dq[49]] -set_property -dict {PACKAGE_PIN AJ34} [get_ports ddr4_dq[50]] -set_property -dict {PACKAGE_PIN AK31} [get_ports ddr4_dq[51]] -set_property -dict {PACKAGE_PIN AJ31} [get_ports ddr4_dq[52]] -set_property -dict {PACKAGE_PIN AJ30} [get_ports ddr4_dq[53]] -set_property -dict {PACKAGE_PIN AH34} [get_ports ddr4_dq[54]] -set_property -dict {PACKAGE_PIN AK32} [get_ports ddr4_dq[55]] -set_property -dict {PACKAGE_PIN AN33} [get_ports ddr4_dq[56]] -set_property -dict {PACKAGE_PIN AP33} [get_ports ddr4_dq[57]] -set_property -dict {PACKAGE_PIN AM34} [get_ports ddr4_dq[58]] -set_property -dict {PACKAGE_PIN AP31} [get_ports ddr4_dq[59]] -set_property -dict {PACKAGE_PIN AM32} [get_ports ddr4_dq[60]] -set_property -dict {PACKAGE_PIN AN31} [get_ports ddr4_dq[61]] -set_property -dict {PACKAGE_PIN AL34} [get_ports ddr4_dq[62]] -set_property -dict {PACKAGE_PIN AN32} [get_ports ddr4_dq[63]] -set_property -dict {PACKAGE_PIN AG21} [get_ports ddr4_dqs_p[0]] -set_property -dict {PACKAGE_PIN AH24} [get_ports ddr4_dqs_p[1]] -set_property -dict {PACKAGE_PIN AJ20} [get_ports ddr4_dqs_p[2]] -set_property -dict {PACKAGE_PIN AP20} [get_ports ddr4_dqs_p[3]] -set_property -dict {PACKAGE_PIN AL27} [get_ports ddr4_dqs_p[4]] -set_property -dict {PACKAGE_PIN AN29} [get_ports ddr4_dqs_p[5]] -set_property -dict {PACKAGE_PIN AH33} [get_ports ddr4_dqs_p[6]] -set_property -dict {PACKAGE_PIN AN34} [get_ports ddr4_dqs_p[7]] -set_property -dict {PACKAGE_PIN AH21} [get_ports ddr4_dqs_n[0]] -set_property -dict {PACKAGE_PIN AJ25} [get_ports ddr4_dqs_n[1]] -set_property -dict {PACKAGE_PIN AK20} [get_ports ddr4_dqs_n[2]] -set_property -dict {PACKAGE_PIN AP21} [get_ports ddr4_dqs_n[3]] -set_property -dict {PACKAGE_PIN AL28} [get_ports ddr4_dqs_n[4]] -set_property -dict {PACKAGE_PIN AP30} [get_ports ddr4_dqs_n[5]] -set_property -dict {PACKAGE_PIN AJ33} [get_ports ddr4_dqs_n[6]] -set_property -dict {PACKAGE_PIN AP34} [get_ports ddr4_dqs_n[7]] -set_property -dict {PACKAGE_PIN AJ18} [get_ports ddr4_odt[0]] -set_property -dict {PACKAGE_PIN AL18} [get_ports ddr4_reset_n] set_property -dict {INTERNAL_VREF {0.84}} [get_iobanks 44] set_property -dict {INTERNAL_VREF {0.84}} [get_iobanks 45] set_property -dict {INTERNAL_VREF {0.84}} [get_iobanks 46] -set_false_path -to [get_pins -hier -filter {name =~ *axi_ethernet_idelayctrl*/RST}] +create_clock -name phy_clk -period 1.60 [get_ports phy_clk_p] +set_false_path -to [get_pins -hier -filter {name =~ *ethernet*idelayctrl*/RST}] diff --git a/projects/common/mitx045/mitx045_system_bd.tcl b/projects/common/mitx045/mitx045_system_bd.tcl index ce55e0b17..c114e8302 100644 --- a/projects/common/mitx045/mitx045_system_bd.tcl +++ b/projects/common/mitx045/mitx045_system_bd.tcl @@ -111,7 +111,7 @@ set_property -dict [list CONFIG.C_INCLUDE_S2MM {0}] $axi_hdmi_dma # audio peripherals -set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen] +set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_audio_clkgen] set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen diff --git a/projects/common/vc707/vc707_system_bd.tcl b/projects/common/vc707/vc707_system_bd.tcl index 2ddd6d1ba..37c94841f 100644 --- a/projects/common/vc707/vc707_system_bd.tcl +++ b/projects/common/vc707/vc707_system_bd.tcl @@ -64,7 +64,7 @@ set_property -dict [list CONFIG.C_ECC {0}] $sys_dlmb_cntlr set sys_ilmb_cntlr [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 sys_ilmb_cntlr] set_property -dict [list CONFIG.C_ECC {0}] $sys_ilmb_cntlr -set sys_lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.2 sys_lmb_bram] +set sys_lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.3 sys_lmb_bram] set_property -dict [list CONFIG.Memory_Type {True_Dual_Port_RAM} CONFIG.use_bram_block {BRAM_Controller}] $sys_lmb_bram # instance: microblaze- mdm @@ -78,7 +78,7 @@ set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 s # instance: ddr (mig) -set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.3 axi_ddr_cntrl] +set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.4 axi_ddr_cntrl] set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl]]] file copy -force $ad_hdl_dir/projects/common/vc707/vc707_system_mig.prj "$axi_ddr_cntrl_dir/" set_property -dict [list CONFIG.XML_INPUT_FILE {vc707_system_mig.prj}] $axi_ddr_cntrl diff --git a/projects/common/xilinx/compression_system_constr.xdc b/projects/common/xilinx/compression_system_constr.xdc new file mode 100644 index 000000000..94ea80e52 --- /dev/null +++ b/projects/common/xilinx/compression_system_constr.xdc @@ -0,0 +1 @@ +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] diff --git a/projects/common/xilinx/sys_dmafifo.tcl b/projects/common/xilinx/sys_dmafifo.tcl index dec208f4f..f6876fd9b 100644 --- a/projects/common/xilinx/sys_dmafifo.tcl +++ b/projects/common/xilinx/sys_dmafifo.tcl @@ -67,10 +67,12 @@ proc p_sys_dacfifo {p_name m_name data_width addr_width} { create_bd_pin -dir I -from [expr ($data_width-1)] -to 0 dma_data create_bd_pin -dir I dma_xfer_req create_bd_pin -dir I dma_xfer_last + create_bd_pin -dir I dac_fifo_bypass create_bd_pin -dir I dac_clk create_bd_pin -dir I dac_valid create_bd_pin -dir O -from [expr ($data_width - 1)] -to 0 dac_data + create_bd_pin -dir O dac_xfer_out set util_dacfifo [create_bd_cell -type ip -vlnv analog.com:user:util_dacfifo:1.0 util_dacfifo] set_property -dict [list CONFIG.DATA_WIDTH $data_width] $util_dacfifo @@ -86,6 +88,8 @@ proc p_sys_dacfifo {p_name m_name data_width addr_width} { ad_connect dma_xfer_last util_dacfifo/dma_xfer_last ad_connect dac_valid util_dacfifo/dac_valid ad_connect dac_data util_dacfifo/dac_data + ad_connect dac_xfer_out util_dacfifo/dac_xfer_out + ad_connect dac_fifo_bypass util_dacfifo/dac_fifo_bypass current_bd_instance $c_instance } diff --git a/projects/common/zc702/zc702_system_bd.tcl b/projects/common/zc702/zc702_system_bd.tcl index 6b1359b0e..bbcf32a50 100644 --- a/projects/common/zc702/zc702_system_bd.tcl +++ b/projects/common/zc702/zc702_system_bd.tcl @@ -100,7 +100,7 @@ set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_hdmi_dma # audio peripherals -set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen] +set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_audio_clkgen] set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen diff --git a/projects/common/zc706/zc706_system_bd.tcl b/projects/common/zc706/zc706_system_bd.tcl index 04aead65f..49380211b 100644 --- a/projects/common/zc706/zc706_system_bd.tcl +++ b/projects/common/zc706/zc706_system_bd.tcl @@ -103,7 +103,7 @@ set_property -dict [list CONFIG.C_INCLUDE_S2MM {0}] $axi_hdmi_dma # audio peripherals -set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen] +set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_audio_clkgen] set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen diff --git a/projects/common/zc706/zc706_system_plddr3.tcl b/projects/common/zc706/zc706_system_plddr3.tcl index 38bc92777..799f55021 100644 --- a/projects/common/zc706/zc706_system_plddr3.tcl +++ b/projects/common/zc706/zc706_system_plddr3.tcl @@ -31,7 +31,7 @@ proc p_plddr3_fifo {p_name m_name adc_data_width} { create_bd_pin -dir I dma_xfer_req create_bd_pin -dir O -from 3 -to 0 dma_xfer_status - set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.3 axi_ddr_cntrl] + set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.4 axi_ddr_cntrl] set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl]]] file copy -force $ad_hdl_dir/projects/common/zc706/zc706_system_mig.prj "$axi_ddr_cntrl_dir/" set_property -dict [list CONFIG.XML_INPUT_FILE {zc706_system_mig.prj}] $axi_ddr_cntrl diff --git a/projects/common/zed/zed_system_bd.tcl b/projects/common/zed/zed_system_bd.tcl index 09bed96d4..57e47c751 100644 --- a/projects/common/zed/zed_system_bd.tcl +++ b/projects/common/zed/zed_system_bd.tcl @@ -125,7 +125,7 @@ set_property -dict [list CONFIG.C_INCLUDE_S2MM {0}] $axi_hdmi_dma # audio peripherals -set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen] +set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_audio_clkgen] set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen diff --git a/projects/daq1/common/daq1_bd.tcl b/projects/daq1/common/daq1_bd.tcl index 1dd1448a8..4f2fe6dee 100644 --- a/projects/daq1/common/daq1_bd.tcl +++ b/projects/daq1/common/daq1_bd.tcl @@ -57,7 +57,7 @@ set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] [get_bd_cells axi_a set axi_ad9250_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9250:1.0 axi_ad9250_core] -set axi_ad9250_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.0 axi_ad9250_jesd] +set axi_ad9250_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9250_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9250_jesd set_property -dict [list CONFIG.C_LANES {2}] $axi_ad9250_jesd diff --git a/projects/daq1/zc706/Makefile b/projects/daq1/zc706/Makefile index bcb19e751..8df754906 100644 --- a/projects/daq1/zc706/Makefile +++ b/projects/daq1/zc706/Makefile @@ -37,6 +37,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/daq2/a10gx/system_bd.qsys b/projects/daq2/a10gx/system_bd.qsys index 9f991b1ec..fac722018 100755 --- a/projects/daq2/a10gx/system_bd.qsys +++ b/projects/daq2/a10gx/system_bd.qsys @@ -50,7 +50,7 @@ { datum baseAddress { - value = "212992"; + value = "229376"; type = "String"; } } @@ -66,7 +66,7 @@ { datum baseAddress { - value = "196608"; + value = "212992"; type = "String"; } } @@ -78,6 +78,54 @@ type = "String"; } } + element daq2.xcvr_core_jesd204_rx_s_avl + { + datum baseAddress + { + value = "254976"; + type = "String"; + } + } + element daq2.xcvr_core_jesd204_tx_s_avl + { + datum baseAddress + { + value = "253952"; + type = "String"; + } + } + element daq2.xcvr_core_reconfig_s_avl + { + datum baseAddress + { + value = "196608"; + type = "String"; + } + } + element daq2.xcvr_rx_pll_reconfig_s_avl + { + datum baseAddress + { + value = "251904"; + type = "String"; + } + } + element daq2.xcvr_tx_lane_pll_s_avl + { + datum baseAddress + { + value = "245760"; + type = "String"; + } + } + element daq2.xcvr_tx_pll_reconfig_s_avl + { + datum baseAddress + { + value = "249856"; + type = "String"; + } + } element sys_clk { datum _sortIndex @@ -313,7 +361,7 @@ } ]]> - + @@ -418,14 +466,14 @@ type="reset" dir="end" /> - + - ]]> + ]]> @@ -445,7 +493,7 @@ - + @@ -502,7 +550,7 @@ start="a10gx_base.sys_cpu_m_avl" end="daq2.axi_ad9144_dma_s_axi"> - + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + @@ -821,6 +837,36 @@ internal="axi_jesd_xcvr.if_tx_ext_sysref_in" type="conduit" dir="end" /> + + + + + + @@ -909,7 +955,7 @@ - + @@ -957,14 +1003,14 @@ - - - + + + - - + + @@ -978,19 +1024,19 @@ - + - + - + - - + + @@ -1174,7 +1220,7 @@ - + @@ -1275,11 +1321,21 @@ - + + + + + + + - + - + - + @@ -1315,7 +1371,7 @@ - + @@ -1335,7 +1391,7 @@ - + @@ -1343,16 +1399,16 @@ - - - + + + - - + + - - - + + + @@ -1537,7 +1593,7 @@ - + @@ -1638,11 +1694,21 @@ - + + + + + + + + + + + - - - - - - - + start="xcvr_tx_lane_pll.pll_cal_busy" + end="xcvr_rst_cntrl.pll_cal_busy"> @@ -2028,8 +2103,52 @@ + start="xcvr_rst_cntrl.pll_powerdown" + end="xcvr_tx_lane_pll.pll_powerdown"> + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -2127,8 +2246,19 @@ + start="xcvr_core.tx_digitalreset" + end="xcvr_rst_cntrl.tx_digitalreset"> + + + + + + + @@ -2220,6 +2350,26 @@ version="15.1" start="mem_rst.out_reset" end="axi_ad9144_dma.m_src_axi_reset" /> + + + + + > daq3_a10gx_quartus.log 2>&1 + +#################################################################################### +#################################################################################### diff --git a/projects/daq3/a10gx/system_bd.qsys b/projects/daq3/a10gx/system_bd.qsys new file mode 100755 index 000000000..ec6989ffe --- /dev/null +++ b/projects/daq3/a10gx/system_bd.qsys @@ -0,0 +1,680 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ]]> + + + + + + + + + $${FILENAME}_a10gx_base + + + ]]> + + ]]> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/daq3/a10gx/system_constr.sdc b/projects/daq3/a10gx/system_constr.sdc new file mode 100755 index 000000000..542f5e9d8 --- /dev/null +++ b/projects/daq3/a10gx/system_constr.sdc @@ -0,0 +1,43 @@ + +create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}] +create_clock -period "2.000 ns" -name rx_ref_clk_500mhz [get_ports {rx_ref_clk}] +create_clock -period "2.000 ns" -name tx_ref_clk_500mhz [get_ports {tx_ref_clk}] + +derive_pll_clocks +derive_clock_uncertainty + +set_false_path -from [get_clocks {sys_clk_100mhz}] -to [get_clocks {\ + i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_0 \ + i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_1 \ + i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_2 \ + i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_l_0 \ + i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_l_1 \ + i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_l_2}] + +set_false_path -from [get_clocks {sys_clk_100mhz}] -to [get_clocks {\ + i_system_bd|a10gx_base|sys_ddr3_cntrl_core_nios_clk}] + +set_false_path -from [get_clocks {sys_clk_100mhz}]\ + -through [get_nets *altera_jesd204_tx_csr_inst*]\ + -to [get_clocks {i_system_bd|daq3|xcvr_tx_pll|outclk0}] + +set_false_path -from [get_clocks {sys_clk_100mhz}]\ + -through [get_nets *altera_jesd204_tx_ctl_inst*]\ + -to [get_clocks {i_system_bd|daq3|xcvr_tx_pll|outclk0}] + +set_false_path -from [get_clocks {sys_clk_100mhz}]\ + -through [get_nets *altera_jesd204_rx_csr_inst*]\ + -to [get_clocks {i_system_bd|daq3|xcvr_rx_pll|outclk0}] + +set_false_path -from [get_clocks {i_system_bd|daq3|xcvr_tx_pll|outclk0}]\ + -through [get_nets *altera_jesd204_tx_csr_inst*]\ + -to [get_clocks {sys_clk_100mhz}] + +set_false_path -from [get_clocks {i_system_bd|daq3|xcvr_tx_pll|outclk0}]\ + -through [get_nets *altera_jesd204_tx_ctl_inst*]\ + -to [get_clocks {sys_clk_100mhz}] + +set_false_path -from [get_clocks {i_system_bd|daq3|xcvr_rx_pll|outclk0}]\ + -through [get_nets *altera_jesd204_rx_csr_inst*]\ + -to [get_clocks {sys_clk_100mhz}] + diff --git a/projects/daq3/a10gx/system_project.tcl b/projects/daq3/a10gx/system_project.tcl new file mode 100755 index 000000000..a28b59e65 --- /dev/null +++ b/projects/daq3/a10gx/system_project.tcl @@ -0,0 +1,92 @@ + +load_package flow + +source ../../scripts/adi_env.tcl +project_new daq3_a10gx -overwrite + +source "../../common/a10gx/a10gx_system_assign.tcl" +set_user_option -name USER_IP_SEARCH_PATHS "../common/;../../common/a10gx/;../../../library/**/*" +set_global_assignment -name IP_SEARCH_PATHS "../common/;../../common/a10gx;../../../library/**/*" +set_global_assignment -name QSYS_FILE system_bd.qsys + +set_global_assignment -name VERILOG_FILE ../common/daq3_spi.v +set_global_assignment -name VERILOG_FILE system_top.v + +set_global_assignment -name SDC_FILE system_constr.sdc +set_global_assignment -name TOP_LEVEL_ENTITY system_top + +# lane interface + +set_location_assignment PIN_AJ8 -to rx_ref_clk ; ## B20 FMCA_GBTCLK1_M2C_P +set_location_assignment PIN_AJ7 -to "rx_ref_clk(n)" ; ## B21 FMCA_GBTCLK1_M2C_N +set_location_assignment PIN_AV5 -to rx_data[0] ; ## A10 FMCA_DP3_M2C_P +set_location_assignment PIN_AV6 -to "rx_data[0](n)" ; ## A11 FMCA_DP3_M2C_N +set_location_assignment PIN_AW7 -to rx_data[1] ; ## C06 FMCA_DP0_M2C_P +set_location_assignment PIN_AW8 -to "rx_data[1](n)" ; ## C07 FMCA_DP0_M2C_N +set_location_assignment PIN_AY5 -to rx_data[2] ; ## A06 FMCA_DP2_M2C_P +set_location_assignment PIN_AY6 -to "rx_data[2](n)" ; ## A07 FMCA_DP2_M2C_N +set_location_assignment PIN_BA7 -to rx_data[3] ; ## A02 FMCA_DP1_M2C_P +set_location_assignment PIN_BA8 -to "rx_data[3](n)" ; ## A03 FMCA_DP1_M2C_N +set_location_assignment PIN_AT10 -to rx_sync ; ## D08 FMCA_LA01_CC_P +set_location_assignment PIN_AR11 -to "rx_sync(n)" ; ## D09 FMCA_LA01_CC_N +set_location_assignment PIN_AR20 -to rx_sysref ; ## G09 FMCA_LA03_P +set_location_assignment PIN_AR19 -to "rx_sysref(n)" ; ## G10 FMCA_LA03_N +set_location_assignment PIN_AL8 -to tx_ref_clk ; ## D04 FMCA_GBTCLK0_M2C_P +set_location_assignment PIN_AL7 -to "tx_ref_clk(n)" ; ## D05 FMCA_GBTCLK0_M2C_N +set_location_assignment PIN_BC3 -to tx_data[0] ; ## A30 FMCA_DP3_C2M_P (tx_data_p[0]) +set_location_assignment PIN_BC4 -to "tx_data[0](n)" ; ## A31 FMCA_DP3_C2M_N (tx_data_n[0]) +set_location_assignment PIN_BC7 -to tx_data[1] ; ## C02 FMCA_DP0_C2M_P (tx_data_p[3]) +set_location_assignment PIN_BC8 -to "tx_data[1](n)" ; ## C03 FMCA_DP0_C2M_N (tx_data_n[3]) +set_location_assignment PIN_BB5 -to tx_data[2] ; ## A26 FMCA_DP2_C2M_P (tx_data_p[1]) +set_location_assignment PIN_BB6 -to "tx_data[2](n)" ; ## A27 FMCA_DP2_C2M_N (tx_data_n[1]) +set_location_assignment PIN_BD5 -to tx_data[3] ; ## A22 FMCA_DP1_C2M_P (tx_data_p[2]) +set_location_assignment PIN_BD6 -to "tx_data[3](n)" ; ## A23 FMCA_DP1_C2M_N (tx_data_n[2]) +set_location_assignment PIN_AR22 -to tx_sync ; ## H07 FMCA_LA02_P +set_location_assignment PIN_AT22 -to "tx_sync(n)" ; ## H08 FMCA_LA02_N +set_location_assignment PIN_AN20 -to tx_sysref ; ## H10 FMCA_LA04_P +set_location_assignment PIN_AP19 -to "tx_sysref(n)" ; ## H11 FMCA_LA04_N + +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[0] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[1] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[2] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[3] +set_instance_assignment -name IO_STANDARD LVDS -to rx_sync +set_instance_assignment -name IO_STANDARD LVDS -to rx_sysref +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_sysref +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[0] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[1] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[2] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[3] +set_instance_assignment -name IO_STANDARD LVDS -to tx_sync +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to tx_sync +set_instance_assignment -name IO_STANDARD LVDS -to tx_sysref +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to tx_sysref + +# gpio + +set_location_assignment PIN_AT17 -to trig ; ## H13 FMCA_LA07_P +set_location_assignment PIN_AU17 -to "trig(n)" ; ## H14 FMCA_LA07_N +set_location_assignment PIN_AR14 -to adc_fdb ; ## H17 FMCA_LA11_N +set_location_assignment PIN_AT14 -to adc_fda ; ## H16 FMCA_LA11_P +set_location_assignment PIN_AR16 -to dac_irq ; ## G15 FMCA_LA12_P +set_location_assignment PIN_AN19 -to clkd_status[1] ; ## G13 FMCA_LA08_N +set_location_assignment PIN_AP18 -to clkd_status[0] ; ## G12 FMCA_LA08_P +set_location_assignment PIN_AV14 -to adc_pd ; ## C10 FMCA_LA06_P +set_location_assignment PIN_AP16 -to dac_txen ; ## G16 FMCA_LA12_N +set_location_assignment PIN_AR17 -to sysref ; ## D17 FMCA_LA13_P +set_location_assignment PIN_AP17 -to "sysref(n)" ; ## D18 FMCA_LA13_N + +set_instance_assignment -name IO_STANDARD LVDS -to trig +set_instance_assignment -name IO_STANDARD LVDS -to sysref + +# spi + +set_location_assignment PIN_AV11 -to spi_csn_clk ; ## D11 FMCA_LA05_P +set_location_assignment PIN_AR15 -to spi_csn_dac ; ## C14 FMCA_LA10_P +set_location_assignment PIN_AV13 -to spi_csn_adc ; ## D15 FMCA_LA09_N +set_location_assignment PIN_AW11 -to spi_clk ; ## D12 FMCA_LA05_N +set_location_assignment PIN_AW13 -to spi_sdio ; ## D14 FMCA_LA09_P +set_location_assignment PIN_AW14 -to spi_dir ; ## C11 FMCA_LA06_N + +execute_flow -compile + diff --git a/projects/daq3/a10gx/system_top.v b/projects/daq3/a10gx/system_top.v new file mode 100755 index 000000000..8524d6ead --- /dev/null +++ b/projects/daq3/a10gx/system_top.v @@ -0,0 +1,285 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + // clock and resets + + sys_clk, + sys_resetn, + + // ddr3 + + ddr3_clk_p, + ddr3_clk_n, + ddr3_a, + ddr3_ba, + ddr3_cke, + ddr3_cs_n, + ddr3_odt, + ddr3_reset_n, + ddr3_we_n, + ddr3_ras_n, + ddr3_cas_n, + ddr3_dqs_p, + ddr3_dqs_n, + ddr3_dq, + ddr3_dm, + ddr3_rzq, + ddr3_ref_clk, + + // ethernet + + eth_ref_clk, + eth_rxd, + eth_txd, + eth_mdc, + eth_mdio, + eth_resetn, + eth_intn, + + // board gpio + + gpio_bd_i, + gpio_bd_o, + + // lane interface + + rx_ref_clk, + rx_sysref, + rx_sync, + rx_data, + tx_ref_clk, + tx_sysref, + tx_sync, + tx_data, + + // gpio + + trig, + adc_fdb, + adc_fda, + dac_irq, + clkd_status, + adc_pd, + dac_txen, + sysref, + + // spi + + spi_csn_clk, + spi_csn_dac, + spi_csn_adc, + spi_clk, + spi_sdio, + spi_dir); + + // clock and resets + + input sys_clk; + input sys_resetn; + + // ddr3 + + output ddr3_clk_p; + output ddr3_clk_n; + output [ 14:0] ddr3_a; + output [ 2:0] ddr3_ba; + output ddr3_cke; + output ddr3_cs_n; + output ddr3_odt; + output ddr3_reset_n; + output ddr3_we_n; + output ddr3_ras_n; + output ddr3_cas_n; + inout [ 7:0] ddr3_dqs_p; + inout [ 7:0] ddr3_dqs_n; + inout [ 63:0] ddr3_dq; + output [ 7:0] ddr3_dm; + input ddr3_rzq; + input ddr3_ref_clk; + + // ethernet + + input eth_ref_clk; + input eth_rxd; + output eth_txd; + output eth_mdc; + inout eth_mdio; + output eth_resetn; + input eth_intn; + + // board gpio + + inout [ 10:0] gpio_bd_i; + inout [ 15:0] gpio_bd_o; + + // lane interface + + input rx_ref_clk; + input rx_sysref; + output rx_sync; + input [ 3:0] rx_data; + input tx_ref_clk; + input tx_sysref; + input tx_sync; + output [ 3:0] tx_data; + + // gpio + + input trig; + input adc_fdb; + input adc_fda; + input dac_irq; + input [ 1:0] clkd_status; + output adc_pd; + output dac_txen; + output sysref; + + // spi + + output spi_csn_clk; + output spi_csn_dac; + output spi_csn_adc; + output spi_clk; + inout spi_sdio; + output spi_dir; + + // internal signals + + wire eth_reset; + wire eth_mdio_i; + wire eth_mdio_o; + wire eth_mdio_t; + wire [ 63:0] gpio_i; + wire [ 63:0] gpio_o; + wire spi_miso_s; + wire spi_mosi_s; + wire [ 7:0] spi_csn_s; + + // daq3 + + assign spi_csn_adc = spi_csn_s[2]; + assign spi_csn_dac = spi_csn_s[1]; + assign spi_csn_clk = spi_csn_s[0]; + + daq3_spi i_daq3_spi ( + .spi_csn (spi_csn_s[2:0]), + .spi_clk (spi_clk), + .spi_mosi (spi_mosi_s), + .spi_miso (spi_miso_s), + .spi_sdio (spi_sdio), + .spi_dir (spi_dir)); + + // gpio in & out are separate cores + + assign sysref = gpio_o[36]; + assign adc_pd = gpio_o[35]; + assign dac_txen = gpio_o[34]; + + assign gpio_i[63:38] = 26'd0; + assign gpio_i[37:37] = trig; + assign gpio_i[36:36] = adc_fdb; + assign gpio_i[35:35] = adc_fda; + assign gpio_i[34:34] = dac_irq; + assign gpio_i[33:32] = clkd_status; + + // board stuff + + assign eth_resetn = ~eth_reset; + assign eth_mdio_i = eth_mdio; + assign eth_mdio = (eth_mdio_t == 1'b1) ? 1'bz : eth_mdio_o; + + assign ddr3_a[14:12] = 3'd0; + + assign gpio_i[31:27] = gpio_o[31:27]; + assign gpio_i[26:16] = gpio_bd_i; + assign gpio_i[15: 0] = gpio_o[15:0]; + + assign gpio_bd_o = gpio_o[15:0]; + + system_bd i_system_bd ( + .a10gx_base_sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p), + .a10gx_base_sys_ddr3_cntrl_mem_mem_ck_n (ddr3_clk_n), + .a10gx_base_sys_ddr3_cntrl_mem_mem_a (ddr3_a[11:0]), + .a10gx_base_sys_ddr3_cntrl_mem_mem_ba (ddr3_ba), + .a10gx_base_sys_ddr3_cntrl_mem_mem_cke (ddr3_cke), + .a10gx_base_sys_ddr3_cntrl_mem_mem_cs_n (ddr3_cs_n), + .a10gx_base_sys_ddr3_cntrl_mem_mem_odt (ddr3_odt), + .a10gx_base_sys_ddr3_cntrl_mem_mem_reset_n (ddr3_reset_n), + .a10gx_base_sys_ddr3_cntrl_mem_mem_we_n (ddr3_we_n), + .a10gx_base_sys_ddr3_cntrl_mem_mem_ras_n (ddr3_ras_n), + .a10gx_base_sys_ddr3_cntrl_mem_mem_cas_n (ddr3_cas_n), + .a10gx_base_sys_ddr3_cntrl_mem_mem_dqs (ddr3_dqs_p[7:0]), + .a10gx_base_sys_ddr3_cntrl_mem_mem_dqs_n (ddr3_dqs_n[7:0]), + .a10gx_base_sys_ddr3_cntrl_mem_mem_dq (ddr3_dq[63:0]), + .a10gx_base_sys_ddr3_cntrl_mem_mem_dm (ddr3_dm[7:0]), + .a10gx_base_sys_ddr3_cntrl_oct_oct_rzqin (ddr3_rzq), + .a10gx_base_sys_ddr3_cntrl_pll_ref_clk_clk (ddr3_ref_clk), + .a10gx_base_sys_ethernet_mdio_mdc (eth_mdc), + .a10gx_base_sys_ethernet_mdio_mdio_in (eth_mdio_i), + .a10gx_base_sys_ethernet_mdio_mdio_out (eth_mdio_o), + .a10gx_base_sys_ethernet_mdio_mdio_oen (eth_mdio_t), + .a10gx_base_sys_ethernet_ref_clk_clk (eth_ref_clk), + .a10gx_base_sys_ethernet_reset_reset (eth_reset), + .a10gx_base_sys_ethernet_sgmii_rxp_0 (eth_rxd), + .a10gx_base_sys_ethernet_sgmii_txp_0 (eth_txd), + .a10gx_base_sys_gpio_in_export (gpio_i[63:32]), + .a10gx_base_sys_gpio_out_export (gpio_o[63:32]), + .a10gx_base_sys_gpio_bd_in_port (gpio_i[31:0]), + .a10gx_base_sys_gpio_bd_out_port (gpio_o[31:0]), + .a10gx_base_sys_spi_MISO (spi_miso_s), + .a10gx_base_sys_spi_MOSI (spi_mosi_s), + .a10gx_base_sys_spi_SCLK (spi_clk), + .a10gx_base_sys_spi_SS_n (spi_csn_s), + .daq3_rx_data_rx_serial_data (rx_data), + .daq3_rx_ref_clk_clk (rx_ref_clk), + .daq3_rx_sync_rx_sync (rx_sync), + .daq3_rx_sysref_rx_ext_sysref_in (rx_sysref), + .daq3_tx_data_tx_serial_data (tx_data), + .daq3_tx_ref_clk_clk (tx_ref_clk), + .daq3_tx_sync_tx_sync (tx_sync), + .daq3_tx_sysref_tx_ext_sysref_in (tx_sysref), + .sys_clk_clk (sys_clk), + .sys_reset_reset_n (sys_resetn)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/daq3/common/daq3_bd.qsys b/projects/daq3/common/daq3_bd.qsys new file mode 100755 index 000000000..912f0c087 --- /dev/null +++ b/projects/daq3/common/daq3_bd.qsys @@ -0,0 +1,2413 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Automatic Switchover + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GX clock output buffer + + + + altera_xcvr_atx_pll_a10 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Automatic Switchover + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/daq3/common/daq3_bd.tcl b/projects/daq3/common/daq3_bd.tcl index cfb78a5b8..2eb48bf37 100644 --- a/projects/daq3/common/daq3_bd.tcl +++ b/projects/daq3/common/daq3_bd.tcl @@ -17,7 +17,7 @@ create_bd_port -dir O -from 3 -to 0 tx_data_n set axi_ad9152_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9152:1.0 axi_ad9152_core] -set axi_ad9152_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9152_jesd] +set axi_ad9152_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9152_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9152_jesd set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9152_jesd @@ -41,7 +41,7 @@ set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9152_upack set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core] -set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9680_jesd] +set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9680_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9680_jesd diff --git a/projects/daq3/common/daq3_spi.v b/projects/daq3/common/daq3_spi.v index afbc05eca..8236ddace 100644 --- a/projects/daq3/common/daq3_spi.v +++ b/projects/daq3/common/daq3_spi.v @@ -98,13 +98,11 @@ module daq3_spi ( end end - // io butter + // io buffer + + assign spi_miso = spi_sdio; + assign spi_sdio = (spi_enable_s == 1'b1) ? 1'bz : spi_mosi; - IOBUF i_iobuf_sdio ( - .T (spi_enable_s), - .I (spi_mosi), - .O (spi_miso), - .IO (spi_sdio)); endmodule diff --git a/projects/daq3/zc706/Makefile b/projects/daq3/zc706/Makefile index 260244908..2e77582c0 100644 --- a/projects/daq3/zc706/Makefile +++ b/projects/daq3/zc706/Makefile @@ -47,6 +47,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/daq3/zc706/system_bd.tcl b/projects/daq3/zc706/system_bd.tcl index 8332b3431..655c77173 100644 --- a/projects/daq3/zc706/system_bd.tcl +++ b/projects/daq3/zc706/system_bd.tcl @@ -30,7 +30,7 @@ set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $mfifo_adc set_property -dict [list CONFIG.DIN_DATA_WIDTH {64}] $mfifo_adc set_property -dict [list CONFIG.ADDRESS_WIDTH {8}] $mfifo_adc -set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_adc] +set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_adc] set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc diff --git a/projects/fmcadc2/common/fmcadc2_bd.tcl b/projects/fmcadc2/common/fmcadc2_bd.tcl index fb1242f1a..7d684044d 100644 --- a/projects/fmcadc2/common/fmcadc2_bd.tcl +++ b/projects/fmcadc2/common/fmcadc2_bd.tcl @@ -11,7 +11,7 @@ create_bd_port -dir I -from 7 -to 0 rx_data_n set axi_ad9625_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9625:1.0 axi_ad9625_core] -set axi_ad9625_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9625_jesd] +set axi_ad9625_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9625_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9625_jesd set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9625_jesd diff --git a/projects/fmcadc2/vc707/Makefile b/projects/fmcadc2/vc707/Makefile index 261bcba5c..3ae995270 100644 --- a/projects/fmcadc2/vc707/Makefile +++ b/projects/fmcadc2/vc707/Makefile @@ -37,6 +37,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/fmcadc2/zc706/Makefile b/projects/fmcadc2/zc706/Makefile index 034ea3b33..352efb7bc 100644 --- a/projects/fmcadc2/zc706/Makefile +++ b/projects/fmcadc2/zc706/Makefile @@ -40,6 +40,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/fmcadc4/common/fmcadc4_bd.tcl b/projects/fmcadc4/common/fmcadc4_bd.tcl index a18f2ca6d..8077399da 100644 --- a/projects/fmcadc4/common/fmcadc4_bd.tcl +++ b/projects/fmcadc4/common/fmcadc4_bd.tcl @@ -14,7 +14,7 @@ set_property -dict [list CONFIG.ID {0}] $axi_ad9680_core_0 set axi_ad9680_core_1 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core_1] set_property -dict [list CONFIG.ID {1}] $axi_ad9680_core_1 -set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9680_jesd] +set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9680_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9680_jesd diff --git a/projects/fmcadc4/zc706/Makefile b/projects/fmcadc4/zc706/Makefile index eddeba7f9..e3d0a21a2 100644 --- a/projects/fmcadc4/zc706/Makefile +++ b/projects/fmcadc4/zc706/Makefile @@ -43,6 +43,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/fmcadc4/zc706/system_bd.tcl b/projects/fmcadc4/zc706/system_bd.tcl index 8e6e65c6c..06ae1973f 100644 --- a/projects/fmcadc4/zc706/system_bd.tcl +++ b/projects/fmcadc4/zc706/system_bd.tcl @@ -28,7 +28,7 @@ set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $mfifo_adc set_property -dict [list CONFIG.DIN_DATA_WIDTH {64}] $mfifo_adc set_property -dict [list CONFIG.ADDRESS_WIDTH {8}] $mfifo_adc -set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_adc] +set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_adc] set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc diff --git a/projects/fmcadc5/common/fmcadc5_bd.tcl b/projects/fmcadc5/common/fmcadc5_bd.tcl index aaaaa83e7..4b3d0c793 100644 --- a/projects/fmcadc5/common/fmcadc5_bd.tcl +++ b/projects/fmcadc5/common/fmcadc5_bd.tcl @@ -19,10 +19,10 @@ set_property -dict [list CONFIG.ID {0}] $axi_ad9625_0_core set axi_ad9625_1_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9625:1.0 axi_ad9625_1_core] set_property -dict [list CONFIG.ID {1}] $axi_ad9625_1_core -set axi_ad9625_0_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9625_0_jesd] +set axi_ad9625_0_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9625_0_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9625_0_jesd set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9625_0_jesd -set axi_ad9625_1_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9625_1_jesd] +set axi_ad9625_1_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9625_1_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9625_1_jesd set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9625_1_jesd diff --git a/projects/fmcadc5/vc707/Makefile b/projects/fmcadc5/vc707/Makefile index 0b5ddbfe3..38905f714 100644 --- a/projects/fmcadc5/vc707/Makefile +++ b/projects/fmcadc5/vc707/Makefile @@ -41,6 +41,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/fmcadc5/vc707/system_bd.tcl b/projects/fmcadc5/vc707/system_bd.tcl index 40dab996c..6ca32626b 100644 --- a/projects/fmcadc5/vc707/system_bd.tcl +++ b/projects/fmcadc5/vc707/system_bd.tcl @@ -10,7 +10,7 @@ set_property -dict [list CONFIG.NUM_OF_CHANNELS {1}] $mfifo_adc set_property -dict [list CONFIG.DIN_DATA_WIDTH {512}] $mfifo_adc set_property -dict [list CONFIG.ADDRESS_WIDTH {6}] $mfifo_adc -set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_adc] +set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_adc] set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc diff --git a/projects/fmcjesdadc1/a5soc/system_bd.qsys b/projects/fmcjesdadc1/a5soc/system_bd.qsys index 67c2527a4..af46dfc16 100644 --- a/projects/fmcjesdadc1/a5soc/system_bd.qsys +++ b/projects/fmcjesdadc1/a5soc/system_bd.qsys @@ -9,14 +9,6 @@ categories="System" /> ]]> + + + @@ -205,14 +200,11 @@ - - - $${FILENAME}_fmcjesdadc1 @@ -221,7 +213,7 @@ @@ -230,7 +222,7 @@ @@ -239,7 +231,7 @@ @@ -248,7 +240,7 @@ @@ -257,7 +249,7 @@ @@ -266,7 +258,7 @@ @@ -275,38 +267,38 @@ + - + end="fmcjesdadc1.cpu_rst" /> + end="fmcjesdadc1.mem_rst" /> diff --git a/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl b/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl index f41f56c89..098001461 100644 --- a/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl +++ b/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl @@ -12,7 +12,7 @@ create_bd_port -dir I -from 3 -to 0 rx_data_n set axi_ad9250_0_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9250:1.0 axi_ad9250_0_core] set axi_ad9250_1_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9250:1.0 axi_ad9250_1_core] -set axi_ad9250_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9250_jesd] +set axi_ad9250_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9250_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9250_jesd set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9250_jesd diff --git a/projects/fmcjesdadc1/kc705/Makefile b/projects/fmcjesdadc1/kc705/Makefile index 71ce938e1..7050c879e 100644 --- a/projects/fmcjesdadc1/kc705/Makefile +++ b/projects/fmcjesdadc1/kc705/Makefile @@ -36,6 +36,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/fmcjesdadc1/vc707/Makefile b/projects/fmcjesdadc1/vc707/Makefile index dcfd2dbef..379caa28b 100644 --- a/projects/fmcjesdadc1/vc707/Makefile +++ b/projects/fmcjesdadc1/vc707/Makefile @@ -36,6 +36,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/fmcjesdadc1/zc706/Makefile b/projects/fmcjesdadc1/zc706/Makefile index 72db888ec..e3c623304 100644 --- a/projects/fmcjesdadc1/zc706/Makefile +++ b/projects/fmcjesdadc1/zc706/Makefile @@ -38,6 +38,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/fmcomms1/ac701/Makefile b/projects/fmcomms1/ac701/Makefile index 238362c27..9c8a6771c 100644 --- a/projects/fmcomms1/ac701/Makefile +++ b/projects/fmcomms1/ac701/Makefile @@ -35,6 +35,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/fmcomms1/common/fmcomms1_bd.tcl b/projects/fmcomms1/common/fmcomms1_bd.tcl index 2694abc46..826ecaaf8 100644 --- a/projects/fmcomms1/common/fmcomms1_bd.tcl +++ b/projects/fmcomms1/common/fmcomms1_bd.tcl @@ -68,7 +68,7 @@ # reference clock - set refclk_clkgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 refclk_clkgen] + set refclk_clkgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 refclk_clkgen] set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {30} ] $refclk_clkgen set_property -dict [list CONFIG.USE_PHASE_ALIGNMENT {false} ] $refclk_clkgen set_property -dict [list CONFIG.JITTER_SEL {Min_O_Jitter} ] $refclk_clkgen diff --git a/projects/fmcomms1/kc705/Makefile b/projects/fmcomms1/kc705/Makefile index 8a42ea764..5d00e2573 100644 --- a/projects/fmcomms1/kc705/Makefile +++ b/projects/fmcomms1/kc705/Makefile @@ -35,6 +35,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/fmcomms1/vc707/Makefile b/projects/fmcomms1/vc707/Makefile index fcb4df7c3..8b7b14948 100644 --- a/projects/fmcomms1/vc707/Makefile +++ b/projects/fmcomms1/vc707/Makefile @@ -35,6 +35,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/fmcomms1/zc702/Makefile b/projects/fmcomms1/zc702/Makefile index 50e606602..c5faab08a 100644 --- a/projects/fmcomms1/zc702/Makefile +++ b/projects/fmcomms1/zc702/Makefile @@ -37,6 +37,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/fmcomms1/zc706/Makefile b/projects/fmcomms1/zc706/Makefile index db02e1958..5170046cd 100644 --- a/projects/fmcomms1/zc706/Makefile +++ b/projects/fmcomms1/zc706/Makefile @@ -37,6 +37,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/fmcomms1/zed/Makefile b/projects/fmcomms1/zed/Makefile index 133c9cef9..79e54721f 100644 --- a/projects/fmcomms1/zed/Makefile +++ b/projects/fmcomms1/zed/Makefile @@ -39,6 +39,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/fmcomms2/ac701/Makefile b/projects/fmcomms2/ac701/Makefile index 5824fd77f..03282725e 100644 --- a/projects/fmcomms2/ac701/Makefile +++ b/projects/fmcomms2/ac701/Makefile @@ -36,6 +36,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/fmcomms2/common/fmcomms2_bd.tcl b/projects/fmcomms2/common/fmcomms2_bd.tcl index 17419f02f..6741c7c8b 100644 --- a/projects/fmcomms2/common/fmcomms2_bd.tcl +++ b/projects/fmcomms2/common/fmcomms2_bd.tcl @@ -168,7 +168,7 @@ ad_cpu_interrupt ps-12 mb-13 axi_ad9361_dac_dma/irq # ila (adc) -set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_adc] +set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_adc] set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc @@ -188,7 +188,7 @@ ad_connect sys_cpu_clk ila_adc/clk # ila (tdd) -set ila_tdd [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_tdd] +set ila_tdd [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_tdd] set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_tdd set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_tdd set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_tdd diff --git a/projects/fmcomms2/common/prcfg_bd.tcl b/projects/fmcomms2/common/prcfg_bd.tcl index e75a63d93..d7313adcc 100644 --- a/projects/fmcomms2/common/prcfg_bd.tcl +++ b/projects/fmcomms2/common/prcfg_bd.tcl @@ -148,7 +148,7 @@ ad_connect up_adc_gpio_out axi_ad9361/up_adc_gpio_out # rx side monitoring -set ila_rx_0 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_rx_0] +set ila_rx_0 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_rx_0] set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_rx_0 set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_rx_0 set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_rx_0 @@ -159,7 +159,7 @@ ad_connect sys_cpu_clk ila_rx_0/clk ad_connect util_ad9361_adc_pack/adc_valid_0 ila_rx_0/probe0 ad_connect util_ad9361_adc_pack/adc_data_0 ila_rx_0/probe1 -set ila_rx_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_rx_1] +set ila_rx_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_rx_1] set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_rx_1 set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_rx_1 set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_rx_1 @@ -205,7 +205,7 @@ ad_connect axi_ad9361/l_clk ila_tx_0/clk ad_connect util_ad9361_adc_fifo/dout_valid_0 ila_tx_0/probe0 ad_connect util_ad9361_adc_fifo/dout_data_0 ila_tx_0/probe1 -set ila_tx_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_tx_1] +set ila_tx_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_tx_1] set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_tx_1 set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_tx_1 set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_tx_1 @@ -216,7 +216,7 @@ ad_connect axi_ad9361/l_clk ila_tx_1/clk ad_connect util_ad9361_adc_fifo/dout_valid_1 ila_tx_1/probe0 ad_connect util_ad9361_adc_fifo/dout_data_1 ila_tx_1/probe1 -set ila_tx_2 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_tx_2] +set ila_tx_2 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_tx_2] set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_tx_2 set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_tx_2 set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_tx_2 @@ -227,7 +227,7 @@ ad_connect axi_ad9361/l_clk ila_tx_2/clk ad_connect util_ad9361_adc_fifo/dout_valid_2 ila_tx_2/probe0 ad_connect util_ad9361_adc_fifo/dout_data_2 ila_tx_2/probe1 -set ila_tx_3 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_tx_3] +set ila_tx_3 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_tx_3] set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_tx_3 set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_tx_3 set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_tx_3 diff --git a/projects/fmcomms2/kc705/Makefile b/projects/fmcomms2/kc705/Makefile index 8a038d42e..ab24ca35e 100644 --- a/projects/fmcomms2/kc705/Makefile +++ b/projects/fmcomms2/kc705/Makefile @@ -36,6 +36,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/fmcomms2/mitx045/Makefile b/projects/fmcomms2/mitx045/Makefile index 6a2874776..ca53855ce 100644 --- a/projects/fmcomms2/mitx045/Makefile +++ b/projects/fmcomms2/mitx045/Makefile @@ -40,6 +40,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/fmcomms2/vc707/Makefile b/projects/fmcomms2/vc707/Makefile index a6db3e1a1..46327e71d 100644 --- a/projects/fmcomms2/vc707/Makefile +++ b/projects/fmcomms2/vc707/Makefile @@ -35,6 +35,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/fmcomms2/zc702/Makefile b/projects/fmcomms2/zc702/Makefile index 5fb3b22c3..439cfe22c 100644 --- a/projects/fmcomms2/zc702/Makefile +++ b/projects/fmcomms2/zc702/Makefile @@ -38,6 +38,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/fmcomms2/zc706/Makefile b/projects/fmcomms2/zc706/Makefile index cdc3bd188..d3c52de44 100644 --- a/projects/fmcomms2/zc706/Makefile +++ b/projects/fmcomms2/zc706/Makefile @@ -37,6 +37,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/fmcomms2/zed/Makefile b/projects/fmcomms2/zed/Makefile index 03edb148a..9fd8dcfc5 100644 --- a/projects/fmcomms2/zed/Makefile +++ b/projects/fmcomms2/zed/Makefile @@ -40,6 +40,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/fmcomms5/zc702/Makefile b/projects/fmcomms5/zc702/Makefile index 8bfcc6aeb..bba74f74a 100644 --- a/projects/fmcomms5/zc702/Makefile +++ b/projects/fmcomms5/zc702/Makefile @@ -36,6 +36,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/fmcomms5/zc706/Makefile b/projects/fmcomms5/zc706/Makefile index bac1ce596..5aee574f5 100644 --- a/projects/fmcomms5/zc706/Makefile +++ b/projects/fmcomms5/zc706/Makefile @@ -36,6 +36,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/fmcomms6/zc706/Makefile b/projects/fmcomms6/zc706/Makefile index 15699ccfb..3846e87f0 100644 --- a/projects/fmcomms6/zc706/Makefile +++ b/projects/fmcomms6/zc706/Makefile @@ -36,6 +36,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/fmcomms7/common/fmcomms7_bd.tcl b/projects/fmcomms7/common/fmcomms7_bd.tcl index e0175ccdc..59e3cce66 100644 --- a/projects/fmcomms7/common/fmcomms7_bd.tcl +++ b/projects/fmcomms7/common/fmcomms7_bd.tcl @@ -26,7 +26,7 @@ create_bd_port -dir I spi2_sdi_i set axi_ad9144_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9144:1.0 axi_ad9144_core] set_property -dict [list CONFIG.QUAD_OR_DUAL_N {1}] $axi_ad9144_core -set axi_ad9144_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9144_jesd] +set axi_ad9144_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9144_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9144_jesd set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9144_jesd @@ -50,7 +50,7 @@ set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $axi_ad9144_upack set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core] -set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9680_jesd] +set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9680_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9680_jesd diff --git a/projects/fmcomms7/zc706/Makefile b/projects/fmcomms7/zc706/Makefile index 95fc249f4..2caa37ee7 100644 --- a/projects/fmcomms7/zc706/Makefile +++ b/projects/fmcomms7/zc706/Makefile @@ -46,6 +46,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/imageon/common/imageon_bd.tcl b/projects/imageon/common/imageon_bd.tcl index ec5784c68..412705ab3 100644 --- a/projects/imageon/common/imageon_bd.tcl +++ b/projects/imageon/common/imageon_bd.tcl @@ -76,7 +76,7 @@ ad_cpu_interrupt ps-12 mb-12 axi_hdmi_rx_dma/irq # debug -set ila_fifo_dma_rx [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_fifo_dma_rx] +set ila_fifo_dma_rx [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_fifo_dma_rx] set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_fifo_dma_rx set_property -dict [list CONFIG.C_NUM_OF_PROBES {4}] $ila_fifo_dma_rx set_property -dict [list CONFIG.C_DATA_DEPTH {4096}] $ila_fifo_dma_rx diff --git a/projects/imageon/zc706/Makefile b/projects/imageon/zc706/Makefile index 7e0d311db..c4981bb84 100644 --- a/projects/imageon/zc706/Makefile +++ b/projects/imageon/zc706/Makefile @@ -34,6 +34,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/imageon/zed/Makefile b/projects/imageon/zed/Makefile index dc58dca51..1148228ee 100644 --- a/projects/imageon/zed/Makefile +++ b/projects/imageon/zed/Makefile @@ -36,6 +36,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl b/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl index 795f26750..58800d076 100644 --- a/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl +++ b/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl @@ -12,6 +12,7 @@ # current monitor interface # clock create_bd_port -dir O adc_clk_o + # data motor 1 create_bd_port -dir I adc_m1_ia_dat_i create_bd_port -dir I adc_m1_ib_dat_i @@ -120,6 +121,7 @@ set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $current_monitor_m1_dma set_property -dict [list CONFIG.CYCLIC {0}] $current_monitor_m1_dma set_property -dict [list CONFIG.DMA_AXI_PROTOCOL_DEST {0}] $current_monitor_m1_dma + set_property -dict [list CONFIG.SYNC_TRANSFER_START {true}] $current_monitor_m1_dma # data packer motor 1 # set current_monitor_m1_pack [ create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 current_monitor_m1_pack ] @@ -134,6 +136,7 @@ set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $current_monitor_m2_dma set_property -dict [list CONFIG.CYCLIC {0}] $current_monitor_m2_dma set_property -dict [list CONFIG.DMA_AXI_PROTOCOL_DEST {0}] $current_monitor_m2_dma + set_property -dict [list CONFIG.SYNC_TRANSFER_START {true}] $current_monitor_m2_dma # data packer motor 2 set current_monitor_m2_pack [ create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 current_monitor_m2_pack ] set_property -dict [ list CONFIG.NUM_OF_CHANNELS {4} ] $current_monitor_m2_pack @@ -159,7 +162,7 @@ set iic_ee2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 iic_ee2 ] # xadc - set xadc_core [ create_bd_cell -type ip -vlnv xilinx.com:ip:xadc_wiz:3.1 xadc_core ] + set xadc_core [ create_bd_cell -type ip -vlnv xilinx.com:ip:xadc_wiz:3.2 xadc_core ] set_property -dict [ list CONFIG.XADC_STARUP_SELECTION {simultaneous_sampling} ] $xadc_core set_property -dict [ list CONFIG.ENABLE_EXTERNAL_MUX {true} ] $xadc_core set_property -dict [ list CONFIG.EXTERNAL_MUX_CHANNEL {VAUXP0_VAUXN0} ] $xadc_core @@ -219,6 +222,7 @@ ad_connect current_monitor_m1/vbus_o current_monitor_m1_pack/adc_data_2 ad_connect current_monitor_m1_pack/adc_data current_monitor_m1_dma/fifo_wr_din ad_connect current_monitor_m1_pack/adc_valid current_monitor_m1_dma/fifo_wr_en + ad_connect current_monitor_m1_dma/fifo_wr_sync current_monitor_m1_pack/adc_sync # motor 2 ad_connect sys_cpu_clk current_monitor_m2/ref_clk @@ -244,6 +248,7 @@ ad_connect current_monitor_m2/vbus_o current_monitor_m2_pack/adc_data_2 ad_connect current_monitor_m2_pack/adc_valid current_monitor_m2_dma/fifo_wr_en ad_connect current_monitor_m2_pack/adc_data current_monitor_m2_dma/fifo_wr_din + ad_connect current_monitor_m2_dma/fifo_wr_sync current_monitor_m2_pack/adc_sync #controller # motor 1 diff --git a/projects/motcon2_fmc/zed/Makefile b/projects/motcon2_fmc/zed/Makefile index e891adcde..e214e56d0 100644 --- a/projects/motcon2_fmc/zed/Makefile +++ b/projects/motcon2_fmc/zed/Makefile @@ -39,6 +39,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/motcon2_fmc/zed/system_constr.xdc b/projects/motcon2_fmc/zed/system_constr.xdc index 728486dfd..a67881ee0 100755 --- a/projects/motcon2_fmc/zed/system_constr.xdc +++ b/projects/motcon2_fmc/zed/system_constr.xdc @@ -24,12 +24,12 @@ set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS25} [get_ports pwm_m1_dl_o] set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS25} [get_ports fmc_m2_en_o] set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS25} [get_ports pwm_m2_ah_o] set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS25} [get_ports pwm_m2_al_o] -set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS25} [get_ports pwm_m2_bh_o] -set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS25} [get_ports pwm_m2_bl_o] -set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS25} [get_ports pwm_m2_ch_o] -set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVCMOS25} [get_ports pwm_m2_cl_o] -set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS25} [get_ports pwm_m2_dh_o] -set_property -dict {PACKAGE_PIN A19 IOSTANDARD LVCMOS25} [get_ports pwm_m2_dl_o] +set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25} [get_ports pwm_m2_bh_o] +set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS25} [get_ports pwm_m2_bl_o] +set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVCMOS25} [get_ports pwm_m2_ch_o] +set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVCMOS25} [get_ports pwm_m2_cl_o] +set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS25} [get_ports pwm_m2_dh_o] +set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS25} [get_ports pwm_m2_dl_o] set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS25 } [get_ports adc_clk_o] set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS25 } [get_ports adc_m1_vbus_dat_i] set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS25 } [get_ports adc_m2_vbus_dat_i] @@ -72,8 +72,8 @@ set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS25 PULLUP true} [get_ports set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS25} [get_ports eth_phy_rst_n] # Ethernet 1 -set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS25} [get_ports eth1_rgmii_rxc] -set_property -dict {PACKAGE_PIN C19 IOSTANDARD LVCMOS25} [get_ports eth1_rgmii_rx_ctl] +set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports eth1_rgmii_rxc] +set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports eth1_rgmii_rx_ctl] set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_rd[0]}] set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_rd[1]}] set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_rd[2]}] @@ -86,16 +86,16 @@ set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {e set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth1_rgmii_td[3]}] # Ethernet 2 -set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports eth2_rgmii_rxc] -set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports eth2_rgmii_rx_ctl] -set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_rd[0]}] -set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_rd[1]}] -set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_rd[2]}] -set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_rd[3]}] +set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS25} [get_ports eth2_rgmii_rxc] +set_property -dict {PACKAGE_PIN C19 IOSTANDARD LVCMOS25} [get_ports eth2_rgmii_rx_ctl] +set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_rd[0]}] +set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_rd[1]}] +set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_rd[2]}] +set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_rd[3]}] set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports eth2_rgmii_txc] set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports eth2_rgmii_tx_ctl] -set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth2_rgmii_td[0]}] -set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth2_rgmii_td[1]}] +set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth2_rgmii_td[0]}] +set_property -dict {PACKAGE_PIN A19 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth2_rgmii_td[1]}] set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth2_rgmii_td[2]}] set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth2_rgmii_td[3]}] diff --git a/projects/pzsdr/ccbrk/Makefile b/projects/pzsdr/ccbrk/Makefile index 49d742665..001dbd654 100644 --- a/projects/pzsdr/ccbrk/Makefile +++ b/projects/pzsdr/ccbrk/Makefile @@ -40,6 +40,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/pzsdr/ccfmc/Makefile b/projects/pzsdr/ccfmc/Makefile index a29f3d69a..aa9dfe4fb 100644 --- a/projects/pzsdr/ccfmc/Makefile +++ b/projects/pzsdr/ccfmc/Makefile @@ -44,6 +44,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/pzsdr/ccpci/Makefile b/projects/pzsdr/ccpci/Makefile index 5668a66a3..fafebeaaa 100644 --- a/projects/pzsdr/ccpci/Makefile +++ b/projects/pzsdr/ccpci/Makefile @@ -37,6 +37,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/pzsdr/common/ccfmc_bd.tcl b/projects/pzsdr/common/ccfmc_bd.tcl index 76ca44c2d..b4da554ca 100644 --- a/projects/pzsdr/common/ccfmc_bd.tcl +++ b/projects/pzsdr/common/ccfmc_bd.tcl @@ -59,7 +59,7 @@ set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_hdmi_dma # audio peripherals -set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen] +set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_audio_clkgen] set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen diff --git a/projects/pzsdr/common/ccpci_bd.tcl b/projects/pzsdr/common/ccpci_bd.tcl index f2961a025..6662565ec 100644 --- a/projects/pzsdr/common/ccpci_bd.tcl +++ b/projects/pzsdr/common/ccpci_bd.tcl @@ -49,7 +49,7 @@ ad_connect pl_gpio1_t axi_gpio/gpio2_io_t # pci-express -set axi_pcie_x4 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_pcie:2.6 axi_pcie_x4] +set axi_pcie_x4 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_pcie:2.7 axi_pcie_x4] set_property -dict [list CONFIG.NO_OF_LANES {X4}] $axi_pcie_x4 set_property -dict [list CONFIG.MAX_LINK_SPEED {5.0_GT/s}] $axi_pcie_x4 set_property -dict [list CONFIG.VENDOR_ID {0x11D4}] $axi_pcie_x4 diff --git a/projects/scripts/adi_project.tcl b/projects/scripts/adi_project.tcl index 92d64577a..f404df885 100644 --- a/projects/scripts/adi_project.tcl +++ b/projects/scripts/adi_project.tcl @@ -7,7 +7,7 @@ variable p_prcfg_list variable p_prcfg_status if {![info exists REQUIRED_VIVADO_VERSION]} { - set REQUIRED_VIVADO_VERSION "2015.2.1" + set REQUIRED_VIVADO_VERSION "2015.4.2" } if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { @@ -47,7 +47,7 @@ proc adi_project_create {project_name {mode 0}} { } if [regexp "_kcu105$" $project_name] { set p_device "xcku040-ffva1156-2-e" - set p_board "xilinx.com:kcu105:part0:1.0" + set p_board "xilinx.com:kcu105:part0:1.1" set sys_zynq 0 } if [regexp "_zed$" $project_name] { @@ -126,6 +126,12 @@ proc adi_project_create {project_name {mode 0}} { } else { write_hwdef -file "$project_name.data/$project_name.hwdef" } + + if {![info exists ::env(ADI_NO_BITSTREAM_COMPRESSION)] && ![info exists ADI_NO_BITSTREAM_COMPRESSION]} { + add_files -norecurse -fileset sources_1 \ + "$ad_hdl_dir/projects/common/xilinx/compression_system_constr.xdc" + } + } proc adi_project_files {project_name project_files} { diff --git a/projects/usb_fx3/common/usb_fx3_bd.tcl b/projects/usb_fx3/common/usb_fx3_bd.tcl index 31f75ad6b..8c1c8f0ad 100644 --- a/projects/usb_fx3/common/usb_fx3_bd.tcl +++ b/projects/usb_fx3/common/usb_fx3_bd.tcl @@ -60,7 +60,7 @@ ad_mem_hp1_interconnect sys_cpu_clk axi_usb_fx3_dma/M_AXI_S2MM set vcc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 vcc] #ad_connect vcc/dout axi_usb_fx3/m_axis_tready -set ila [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila] +set ila [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila] set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila set_property -dict [list CONFIG.C_NUM_OF_PROBES {3}] $ila set_property -dict [list CONFIG.C_PROBE2_WIDTH {15}] $ila diff --git a/projects/usb_fx3/zc706/Makefile b/projects/usb_fx3/zc706/Makefile index f16d3c455..eb786cf55 100644 --- a/projects/usb_fx3/zc706/Makefile +++ b/projects/usb_fx3/zc706/Makefile @@ -32,6 +32,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil diff --git a/projects/usdrx1/a5gt/Makefile b/projects/usdrx1/a5gt/Makefile index 9be0289b1..d461204bb 100644 --- a/projects/usdrx1/a5gt/Makefile +++ b/projects/usdrx1/a5gt/Makefile @@ -8,6 +8,7 @@ M_DEPS += system_project.tcl M_DEPS += ../common/usdrx1_spi.v M_DEPS += ../../scripts/adi_env.tcl +M_DEPS += ../../common/a5gt/a5gt_system_bd.qsys M_DEPS += ../../common/a5gt/a5gt_system_assign.tcl M_DEPS += ../../../library/common/altera/ad_xcvr_rx_rst.v M_DEPS += ../../../library/common/altera/ad_jesd_align.v diff --git a/projects/usdrx1/common/usdrx1_bd.tcl b/projects/usdrx1/common/usdrx1_bd.tcl index d71659a1a..4b9f89177 100644 --- a/projects/usdrx1/common/usdrx1_bd.tcl +++ b/projects/usdrx1/common/usdrx1_bd.tcl @@ -58,7 +58,7 @@ set axi_ad9671_core_3 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9671: set_property -dict [list CONFIG.QUAD_OR_DUAL_N {0}] $axi_ad9671_core_3 set_property -dict [list CONFIG.ID {3}] $axi_ad9671_core_3 -set axi_usdrx1_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_usdrx1_jesd] +set axi_usdrx1_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_usdrx1_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_usdrx1_jesd set_property -dict [list CONFIG.C_LANES {8}] $axi_usdrx1_jesd set_property -dict [list CONFIG.GT_Line_Rate {3.2} ] $axi_usdrx1_jesd @@ -300,7 +300,7 @@ ad_cpu_interrupt ps-13 mb-13 axi_usdrx1_dma/irq # ila -set ila_ad9671 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_ad9671] +set ila_ad9671 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_ad9671] set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_ad9671 set_property -dict [list CONFIG.C_NUM_OF_PROBES {9}] $ila_ad9671 set_property -dict [list CONFIG.C_PROBE0_WIDTH {128}] $ila_ad9671 diff --git a/projects/usdrx1/zc706/Makefile b/projects/usdrx1/zc706/Makefile index 4a0ec0f19..936fbbcfe 100644 --- a/projects/usdrx1/zc706/Makefile +++ b/projects/usdrx1/zc706/Makefile @@ -39,6 +39,8 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil