axi_dmac: Added fix to work with motor_control
parent
dfb94f7b68
commit
acde4f2c9a
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@ -85,25 +85,36 @@ reg [C_BEATS_PER_BURST_WIDTH-1:0] last_burst_len = 'h00;
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assign addr = {address, {C_BYTES_PER_BEAT_WIDTH{1'b0}}};
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reg addr_valid_d1;
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reg last = 1'b0;
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// If we already asserted addr_valid we have to wait until it is accepted before
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// we can disable the address generator.
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always @(posedge clk) begin
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if (resetn == 1'b0) begin
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enabled <= 1'b0;
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end else begin
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if (enable)
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enabled <= 1'b1;
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else if (~addr_valid)
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enabled <= 1'b0;
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end
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if (resetn == 1'b0) begin
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enabled <= 1'b0;
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end else begin
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if (enable)
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enabled <= 1'b1;
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else if (~addr_valid)
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enabled <= 1'b0;
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end
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end
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always @(posedge clk) begin
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if (eot == 1'b1)
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length <= req_last_burst_length;
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else
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length <= MAX_BEATS_PER_BURST - 1;
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if (addr_valid == 1'b0) begin
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if (eot == 1'b1)
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length <= req_last_burst_length;
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else
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length <= MAX_BEATS_PER_BURST - 1;
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end
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end
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always @(posedge clk) begin
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if (resetn == 1'b0) begin
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last <= 1'b0;
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end else if (addr_valid == 1'b0) begin
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last <= eot;
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end
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end
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always @(posedge clk) begin
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@ -124,7 +135,7 @@ always @(posedge clk) begin
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if (addr_valid && addr_ready) begin
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address <= address + MAX_BEATS_PER_BURST;
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addr_valid <= 1'b0;
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if (eot)
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if (last)
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req_ready <= 1'b1;
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end else if (id != request_id && enable) begin
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addr_valid <= 1'b1;
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@ -139,7 +150,7 @@ always @(posedge clk) begin
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addr_valid_d1 <= 1'b0;
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end else begin
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addr_valid_d1 <= addr_valid;
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if (( addr_valid && ~addr_valid_d1) ||
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if ((addr_valid && ~addr_valid_d1) ||
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(sync_id && id != request_id))
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id <= inc_id(id);
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