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axi_logic_analyzer: Added trigger delay register, renamed fifo depth register

main
Adrian Costina 2017-06-06 15:37:00 +03:00
parent 3148c85f73
commit ac55e850a9
2 changed files with 44 additions and 9 deletions
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38
library/axi_logic_analyzer/axi_logic_analyzer.v
View File

@ -53,7 +53,7 @@ module axi_logic_analyzer (
output reg dac_read,
output trigger_out,
output [31:0] trigger_offset,
output [31:0] fifo_depth,
// axi interface
@ -94,6 +94,10 @@ module axi_logic_analyzer (
reg [15:0] io_selection; // 1 - input, 0 - output
reg trigger_out_delayed;
reg [31:0] delay_counter = 'd0;
reg triggered = 'd0;
// internal signals
wire up_clk;
@ -117,7 +121,6 @@ module axi_logic_analyzer (
wire [17:0] fall_edge_enable;
wire [17:0] low_level_enable;
wire [17:0] high_level_enable;
wire [31:0] trigger_delay;
wire trigger_logic; // 0-OR,1-AND,2-XOR,3-NOR,4-NAND,5-NXOR
wire clock_select;
wire [15:0] overwrite_enable;
@ -126,6 +129,9 @@ module axi_logic_analyzer (
wire [15:0] io_selection_s; // 1 - input, 0 - output
wire [15:0] od_pp_n; // 0 - push/pull, 1 - open drain
wire trigger_out_s;
wire [31:0] trigger_delay;
genvar i;
// signal name changes
@ -133,7 +139,7 @@ module axi_logic_analyzer (
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
assign trigger_offset = trigger_delay;
assign trigger_out = trigger_delay == 32'h0 ? trigger_out_s : trigger_out_delayed;
generate
for (i = 0 ; i < 16; i = i + 1) begin
@ -174,8 +180,8 @@ module axi_logic_analyzer (
// if capture is enabled
always @(posedge clk_out) begin
adc_valid_d1 <= adc_valid_d2;
adc_valid <= adc_valid_d1;
adc_valid_d1 <= adc_valid_d2;
adc_valid <= adc_valid_d1;
if (sample_valid_la == 1'b1) begin
adc_data <= data_m1;
adc_valid_d2 <= 1'b1;
@ -218,6 +224,25 @@ module axi_logic_analyzer (
end
end
always @(posedge clk_out) begin
if(trigger_delay == 32'h0) begin
delay_counter <= 32'h0;
end else begin
if (adc_valid == 1'b1) begin
triggered <= trigger_out_s;
trigger_out_delayed <= 1'b0;
if (delay_counter == 32'h0) begin
delay_counter <= trigger_delay;
trigger_out_delayed <= 1'b1;
triggered <= 1'b0;
end else begin
if(triggered == 1'b1) begin
delay_counter <= delay_counter - 1;
end
end
end
end
end
axi_logic_analyzer_trigger i_trigger (
.clk (clk_out),
@ -233,7 +258,7 @@ module axi_logic_analyzer (
.low_level_enable (low_level_enable),
.high_level_enable (high_level_enable),
.trigger_logic (trigger_logic),
.trigger_out (trigger_out));
.trigger_out (trigger_out_s));
axi_logic_analyzer_reg i_registers (
@ -249,6 +274,7 @@ module axi_logic_analyzer (
.fall_edge_enable (fall_edge_enable),
.low_level_enable (low_level_enable),
.high_level_enable (high_level_enable),
.fifo_depth (fifo_depth),
.trigger_delay (trigger_delay),
.trigger_logic (trigger_logic),
.clock_select (clock_select),

15
library/axi_logic_analyzer/axi_logic_analyzer_reg.v
View File

@ -49,6 +49,7 @@ module axi_logic_analyzer_reg (
output [17:0] fall_edge_enable,
output [17:0] low_level_enable,
output [17:0] high_level_enable,
output [31:0] fifo_depth,
output [31:0] trigger_delay,
output trigger_logic,
output clock_select,
@ -83,6 +84,7 @@ module axi_logic_analyzer_reg (
reg [17:0] up_fall_edge_enable = 0;
reg [17:0] up_low_level_enable = 0;
reg [17:0] up_high_level_enable = 0;
reg [31:0] up_fifo_depth = 0;
reg [31:0] up_trigger_delay = 0;
reg up_trigger_logic = 0;
reg up_clock_select = 0;
@ -103,6 +105,7 @@ module axi_logic_analyzer_reg (
up_fall_edge_enable <= 'd0;
up_low_level_enable <= 'd0;
up_high_level_enable <= 'd0;
up_fifo_depth <= 'd0;
up_trigger_delay <= 'd0;
up_trigger_logic <= 'd0;
up_clock_select <= 'd0;
@ -140,7 +143,7 @@ module axi_logic_analyzer_reg (
up_high_level_enable <= up_wdata[17:0];
end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'ha)) begin
up_trigger_delay <= up_wdata;
up_fifo_depth <= up_wdata;
end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'hb)) begin
up_trigger_logic <= up_wdata[0];
@ -157,6 +160,9 @@ module axi_logic_analyzer_reg (
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h10)) begin
up_od_pp_n <= up_wdata[15:0];
end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h11)) begin
up_trigger_delay <= up_wdata;
end
end
end
@ -180,13 +186,14 @@ module axi_logic_analyzer_reg (
5'h7: up_rdata <= {14'h0,up_fall_edge_enable};
5'h8: up_rdata <= {14'h0,up_low_level_enable};
5'h9: up_rdata <= {14'h0,up_high_level_enable};
5'ha: up_rdata <= up_trigger_delay;
5'ha: up_rdata <= up_fifo_depth;
5'hb: up_rdata <= {31'h0,up_trigger_logic};
5'hc: up_rdata <= {31'h0,up_clock_select};
5'hd: up_rdata <= {16'h0,up_overwrite_enable};
5'he: up_rdata <= {16'h0,up_overwrite_data};
5'hf: up_rdata <= {16'h0,up_input_data};
5'h10: up_rdata <= {16'h0,up_od_pp_n};
5'h11: up_rdata <= up_trigger_delay;
default: up_rdata <= 0;
endcase
end else begin
@ -197,7 +204,7 @@ module axi_logic_analyzer_reg (
ad_rst i_core_rst_reg (.preset(!up_rstn), .clk(clk), .rst(reset));
up_xfer_cntrl #(.DATA_WIDTH(252)) i_xfer_cntrl (
up_xfer_cntrl #(.DATA_WIDTH(284)) i_xfer_cntrl (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_cntrl ({ up_od_pp_n, // 16
@ -205,6 +212,7 @@ module axi_logic_analyzer_reg (
up_overwrite_enable, // 16
up_clock_select, // 1
up_trigger_logic, // 1
up_fifo_depth, // 32
up_trigger_delay, // 32
up_high_level_enable, // 18
up_low_level_enable, // 18
@ -223,6 +231,7 @@ module axi_logic_analyzer_reg (
overwrite_enable, // 16
clock_select, // 1
trigger_logic, // 1
fifo_depth, // 32
trigger_delay, // 32
high_level_enable, // 18
low_level_enable, // 18