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constraints: Update constraints 

Xilinx recommends that all synchronizer flip-flops have
their ASYNC_REG property set to true in order to preserve the
synchronizer cells through any logic optimization during synthesis
and implementation.
main
Istvan Csomortani 2017-02-24 13:43:32 +02:00
parent f326c03ff3
commit ac2e5a9dac
21 changed files with 48 additions and 49 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
library/axi_adc_decimate/axi_adc_decimate_constr.xdc
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@ -1,7 +1,7 @@
set_property shreg_extract no [get_cells -hier -filter {name =~ *up_xfer_state*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *d_xfer_toggle*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *up_xfer_toggle*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *ad_rst_sync*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_xfer_state*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *d_xfer_toggle*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_xfer_toggle*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *ad_rst_sync*}]
set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *up_xfer_state_m1_reg && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_xfer_toggle_m1_reg && IS_SEQUENTIAL}]

10
library/axi_adc_trigger/axi_adc_trigger_constr.xdc
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@ -1,8 +1,8 @@
set_property shreg_extract no [get_cells -hier -filter {name =~ *up_xfer_state*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *d_xfer_toggle*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *up_xfer_toggle*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *trigger_a_d*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *trigger_b_d*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_xfer_state*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *d_xfer_toggle*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_xfer_toggle*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *trigger_a_d*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *trigger_b_d*}]
set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *up_xfer_state_m1_reg && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_xfer_toggle_m1_reg && IS_SEQUENTIAL}]

8
library/axi_dac_interpolate/axi_dac_interpolate_constr.xdc
View File

@ -1,8 +1,8 @@
set_property shreg_extract no [get_cells -hier -filter {name =~ *up_xfer_state*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *d_xfer_toggle*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *up_xfer_toggle*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *ad_rst_sync*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_xfer_state*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *d_xfer_toggle*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_xfer_toggle*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *ad_rst_sync*}]
set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *up_xfer_state_m1_reg && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_xfer_toggle_m1_reg && IS_SEQUENTIAL}]

2
library/axi_gpreg/axi_gpreg_constr.xdc
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@ -1,5 +1,5 @@
set_property shreg_extract no [get_cells -hier -filter {name =~ *ad_rst_sync*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *ad_rst_sync*}]
set_false_path -from [get_cells -hier -filter {name =~ *d_count_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *up_count_toggle_m1_reg && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *d_count_hold* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *up_d_count* && IS_SEQUENTIAL}]

6
library/axi_hdmi_tx/axi_hdmi_tx_constr.xdc
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@ -1,7 +1,7 @@
set_property shreg_extract no [get_cells -hier -filter {name =~ *vdma_fs_toggle*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *vdma_raddr_g*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *hdmi_fs_ret_toggle*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *vdma_fs_toggle*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *vdma_raddr_g*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *hdmi_fs_ret_toggle*}]
set_false_path -from [get_cells -hier -filter {name =~ *hdmi_fs_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *vdma_fs_toggle_m1_reg && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *hdmi_raddr_g* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *vdma_raddr_g_m1* && IS_SEQUENTIAL}]

10
library/axi_logic_analyzer/axi_logic_analyzer_constr.xdc
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@ -1,8 +1,8 @@
set_property shreg_extract no [get_cells -hier -filter {name =~ *up_xfer_state*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *d_xfer_toggle*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *d_xfer_state*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *up_xfer_toggle*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *ad_rst_sync*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_xfer_state*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *d_xfer_toggle*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *d_xfer_state*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_xfer_toggle*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *ad_rst_sync*}]
set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_toggle_reg* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *up_xfer_toggle_m1_reg* && IS_SEQUENTIAL}]

4
library/util_adcfifo/util_adcfifo_constr.xdc
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@ -1,6 +1,6 @@
set_property shreg_extract no [get_cells -hier -filter {name =~ *adc_xfer_req_m*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *dma_waddr_rel_t*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *adc_xfer_req_m*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *dma_waddr_rel_t*}]
set_false_path -from [get_cells -hier -filter {name =~ *adc_waddr_rel_t_reg* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *dma_waddr_rel_t_m_reg[0]* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *adc_waddr_rel_reg* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *dma_waddr_rel_reg* && IS_SEQUENTIAL}]

4
library/util_dacfifo/util_dacfifo_constr.xdc
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@ -1,6 +1,6 @@
set_property shreg_extract no [get_cells -hier -filter {name =~ *dac_lastaddr_d*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *dac_xfer_out_m*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *dac_lastaddr_d*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *dac_xfer_out_m*}]
set_false_path -from [get_cells -hier -filter {name =~ *dma_lastaddr_reg* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *dac_lastaddr_d_reg* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *dac_xfer_out_m_reg[0]* && IS_SEQUENTIAL}]

6
library/util_rfifo/util_rfifo_constr.xdc
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@ -1,7 +1,7 @@
set_property shreg_extract no [get_cells -hier -filter {name =~ *din_enable_m*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *din_req_t_m*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *dout_unf_m*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *din_enable_m*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *din_req_t_m*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *dout_unf_m*}]
set_false_path -from [get_cells -hier -filter {name =~ *dout_enable* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *din_enable_m1* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *dout_req_t* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *din_req_t_m1* && IS_SEQUENTIAL}]

6
library/util_wfifo/util_wfifo_constr.xdc
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@ -1,7 +1,7 @@
set_property shreg_extract no [get_cells -hier -filter {name =~ *dout_enable_m*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *dout_req_t_m*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *din_ovf_m*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *dout_enable_m*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *dout_req_t_m*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *din_ovf_m*}]
set_false_path -from [get_cells -hier -filter {name =~ *din_enable* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *dout_enable_m1* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *din_req_t* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *dout_req_t_m1* && IS_SEQUENTIAL}]

1
library/xilinx/axi_dacfifo/axi_dacfifo_constr.xdc
View File

@ -6,7 +6,6 @@ set_property ASYNC_REG TRUE \
[get_cells -hier *dac_bypass_*] \
[get_cells -hier *dma_bypass_*]
set_false_path -to [get_cells -hier -filter {name =~ *_xfer_req_m_reg[0]* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *_xfer_last_m_reg[0]* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *dac_xfer_out_m1* && IS_SEQUENTIAL}]

8
library/xilinx/axi_xcvrlb/axi_xcvrlb_constr.xdc
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@ -1,8 +1,8 @@
set_property shreg_extract no [get_cells -hier -filter {name =~ *d_xfer_state*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *up_xfer_toggle*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *up_rx_rst_done*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *up_tx_rst_done*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *d_xfer_state*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_xfer_toggle*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_rx_rst_done*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_tx_rst_done*}]
set_false_path -to [get_cells -hier -filter {name =~ *up_rx_rst_done_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *up_tx_rst_done_m1_reg && IS_SEQUENTIAL}]

8
library/xilinx/util_adxcvr/util_adxcvr_constr.xdc
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@ -1,8 +1,8 @@
set_property shreg_extract no [get_cells -hier -filter {name =~ *up_rx_rst_done*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *up_tx_rst_done*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *rx_rate*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *tx_rate*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_rx_rst_done*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_tx_rst_done*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *rx_rate*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *tx_rate*}]
set_false_path -to [get_cells -hier -filter {name =~ *up_rx_rst_done_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *up_tx_rst_done_m1_reg && IS_SEQUENTIAL}]

2
projects/ad6676evb/vc707/system_constr.xdc
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@ -35,6 +35,6 @@ create_clock -name rx_div_clk -period 10.00 [get_pins i_system_wrapper/system
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad6676_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
set_property shreg_extract no [get_cells -hier -filter {name =~ *sysref_en_m*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *sysref_en_m*}]
set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m1* && IS_SEQUENTIAL}]

2
projects/ad6676evb/zc706/system_constr.xdc
View File

@ -35,6 +35,6 @@ create_clock -name rx_div_clk -period 10.00 [get_pins i_system_wrapper/system
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad6676_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
set_property shreg_extract no [get_cells -hier -filter {name =~ *sysref_en_m*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *sysref_en_m*}]
set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m1* && IS_SEQUENTIAL}]

2
projects/fmcadc2/vc707/system_constr.xdc
View File

@ -42,6 +42,6 @@ create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9625_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
set_property shreg_extract no [get_cells -hier -filter {name =~ *sysref_en_m*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *sysref_en_m*}]
set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m1* && IS_SEQUENTIAL}]

2
projects/fmcadc2/zc706/system_constr.xdc
View File

@ -42,6 +42,6 @@ create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9625_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
set_property shreg_extract no [get_cells -hier -filter {name =~ *sysref_en_m*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *sysref_en_m*}]
set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m1* && IS_SEQUENTIAL}]

2
projects/fmcadc5/vc707/system_constr.xdc
View File

@ -88,6 +88,6 @@ create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/syste
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9625_0_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]*]
set_property shreg_extract no [get_cells -hier -filter {name =~ *sysref_en_m*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *sysref_en_m*}]
set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m1* && IS_SEQUENTIAL}]

2
projects/fmcjesdadc1/kc705/system_constr.xdc
View File

@ -25,6 +25,6 @@ create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9250_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
set_property shreg_extract no [get_cells -hier -filter {name =~ *sysref_en_m*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *sysref_en_m*}]
set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m1* && IS_SEQUENTIAL}]

2
projects/fmcjesdadc1/vc707/system_constr.xdc
View File

@ -25,6 +25,6 @@ create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9250_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
set_property shreg_extract no [get_cells -hier -filter {name =~ *sysref_en_m*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *sysref_en_m*}]
set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m1* && IS_SEQUENTIAL}]

2
projects/fmcjesdadc1/zc706/system_constr.xdc
View File

@ -25,6 +25,6 @@ create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9250_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
set_property shreg_extract no [get_cells -hier -filter {name =~ *sysref_en_m*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *sysref_en_m*}]
set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m1* && IS_SEQUENTIAL}]