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ad6676evb: Updated VC707 project

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Adrian Costina 2015-09-25 16:07:22 +03:00
parent 33390c85f8
commit ab4b73fd32
3 changed files with 6 additions and 60 deletions
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9
projects/ad6676evb/vc707/Makefile
View File

@ -20,7 +20,8 @@ M_DEPS += ../../common/vc707/vc707_system_mig.prj
M_DEPS += ../../../library/axi_ad6676/axi_ad6676.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
M_DEPS += ../../../library/util_bsplit/util_bsplit.xpr
M_DEPS += ../../../library/util_cpack/util_cpack.xpr
M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr
M_VIVADO := vivado -mode batch -source
@ -49,7 +50,8 @@ clean-all:clean
make -C ../../../library/axi_ad6676 clean
make -C ../../../library/axi_dmac clean
make -C ../../../library/axi_jesd_gt clean
make -C ../../../library/util_bsplit clean
make -C ../../../library/util_cpack clean
make -C ../../../library/util_jesd_gt clean
ad6676evb_vc707.sdk/system_top.hdf: $(M_DEPS)
@ -61,7 +63,8 @@ lib:
make -C ../../../library/axi_ad6676
make -C ../../../library/axi_dmac
make -C ../../../library/axi_jesd_gt
make -C ../../../library/util_bsplit
make -C ../../../library/util_cpack
make -C ../../../library/util_jesd_gt
####################################################################################
####################################################################################

2
projects/ad6676evb/vc707/system_constr.xdc
View File

@ -31,5 +31,3 @@ set_property -dict {PACKAGE_PIN L42 IOSTANDARD LVCMOS18} [get_ports adc_agc4]
# clocks
create_clock -name rx_ref_clk -period 3.30 [get_ports rx_ref_clk_p]
create_clock -name rx_div_clk -period 6.60 [get_pins i_system_wrapper/system_i/axi_ad6676_gt/inst/g_lane_1[0].i_gt_channel_1/i_gtxe2_channel/RXOUTCLK]

55
projects/ad6676evb/vc707/system_top.v
View File

@ -189,11 +189,6 @@ module system_top (
output spi_mosi;
input spi_miso;
// internal registers
reg adc_dwr = 'd0;
reg [63:0] adc_ddata = 'd0;
// internal signals
wire [63:0] gpio_i;
@ -205,46 +200,6 @@ module system_top (
wire rx_ref_clk;
wire rx_sysref;
wire rx_sync;
wire adc_clk;
wire adc_enable_a;
wire [31:0] adc_data_a;
wire adc_enable_b;
wire [31:0] adc_data_b;
// pack & unpack here
always @(posedge adc_clk) begin
case ({adc_enable_b, adc_enable_a})
2'b11: begin
adc_dwr <= 1'b1;
adc_ddata[63:48] <= adc_data_b[31:16];
adc_ddata[47:32] <= adc_data_a[31:16];
adc_ddata[31:16] <= adc_data_b[15: 0];
adc_ddata[15: 0] <= adc_data_a[15: 0];
end
2'b10: begin
adc_dwr <= ~adc_dwr;
adc_ddata[63:48] <= adc_data_b[31:16];
adc_ddata[47:32] <= adc_data_b[15: 0];
adc_ddata[31:16] <= adc_ddata[63:48];
adc_ddata[15: 0] <= adc_ddata[47:32];
end
2'b01: begin
adc_dwr <= ~adc_dwr;
adc_ddata[63:48] <= adc_data_a[31:16];
adc_ddata[47:32] <= adc_data_a[15: 0];
adc_ddata[31:16] <= adc_ddata[63:48];
adc_ddata[15: 0] <= adc_ddata[47:32];
end
default: begin
adc_dwr <= 1'b0;
adc_ddata[63:48] <= 16'd0;
adc_ddata[47:32] <= 16'd0;
adc_ddata[31:16] <= 16'd0;
adc_ddata[15: 0] <= 16'd0;
end
endcase
end
// default logic
@ -292,16 +247,6 @@ module system_top (
.dio_p (gpio_bd));
system_wrapper i_system_wrapper (
.adc_clk (adc_clk),
.adc_data_a (adc_data_a),
.adc_data_b (adc_data_b),
.adc_ddata (adc_ddata),
.adc_dsync (1'b1),
.adc_dwr (adc_dwr),
.adc_enable_a (adc_enable_a),
.adc_enable_b (adc_enable_b),
.adc_valid_a (),
.adc_valid_b (),
.ddr3_addr (ddr3_addr),
.ddr3_ba (ddr3_ba),
.ddr3_cas_n (ddr3_cas_n),