From aa6c94c9938ac93f61cdda75ed31fb26c3b15715 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 22 Dec 2016 14:13:41 -0500 Subject: [PATCH] usdrx1/a5gt: ddr3 use ip constraints --- projects/usdrx1/a5gt/system_constr.sdc | 16 +++++++--------- projects/usdrx1/a5gt/system_project.tcl | 6 ++++++ projects/usdrx1/a5gt/system_top.v | 15 +++++++++++++-- projects/usdrx1/common/usdrx1_qsys.tcl | 1 + 4 files changed, 27 insertions(+), 11 deletions(-) diff --git a/projects/usdrx1/a5gt/system_constr.sdc b/projects/usdrx1/a5gt/system_constr.sdc index fdfd94802..d8320bcbf 100644 --- a/projects/usdrx1/a5gt/system_constr.sdc +++ b/projects/usdrx1/a5gt/system_constr.sdc @@ -11,19 +11,17 @@ set_clock_groups -exclusive \ -group [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] \ -group [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] -set_false_path -to [get_registers {rx_sysref_m1}] +set_false_path -to [get_registers *sysref_en_m1*] -set_false_path -from [get_clocks {sys_clk}] -through [get_nets *altera_jesd204_rx_ctl_inst*]\ +set_false_path -from [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll6~PLL_OUTPUT_COUNTER|divclk}] -through [get_nets *altera_jesd204_rx_ctl_inst*] \ -to [get_clocks {i_system_bd|avl_usdrx1_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}] -set_false_path -from [get_clocks {i_system_bd|avl_usdrx1_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}]\ - -through [get_nets *altera_jesd204_rx_ctl_inst*] -to [get_clocks {sys_clk}] +set_false_path -from [get_clocks {i_system_bd|avl_usdrx1_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}] \ + -through [get_nets *altera_jesd204_rx_ctl_inst*] -to [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll6~PLL_OUTPUT_COUNTER|divclk}] -set_false_path -from [get_clocks {sys_clk}] -through [get_nets *altera_jesd204_rx_csr_inst*]\ +set_false_path -from [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll6~PLL_OUTPUT_COUNTER|divclk}] -through [get_nets *altera_jesd204_rx_csr_inst*] \ -to [get_clocks {i_system_bd|avl_usdrx1_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}] -set_false_path -from [get_clocks {i_system_bd|avl_usdrx1_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}]\ - -through [get_nets *altera_jesd204_rx_csr_inst*] -to [get_clocks {sys_clk}] +set_false_path -from [get_clocks {i_system_bd|avl_usdrx1_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}] \ + -through [get_nets *altera_jesd204_rx_csr_inst*] -to [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll6~PLL_OUTPUT_COUNTER|divclk}] -set_false_path -from [get_clocks {sys_clk}] [get_nets *sysref_en*] \ - -to [get_clocks {i_system_bd|avl_usdrx1_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}] diff --git a/projects/usdrx1/a5gt/system_project.tcl b/projects/usdrx1/a5gt/system_project.tcl index 8432b7f02..369f2e733 100644 --- a/projects/usdrx1/a5gt/system_project.tcl +++ b/projects/usdrx1/a5gt/system_project.tcl @@ -167,5 +167,11 @@ set_instance_assignment -name IO_STANDARD "2.5 V" -to dac_data[11] set_instance_assignment -name IO_STANDARD "2.5 V" -to dac_data[12] set_instance_assignment -name IO_STANDARD "2.5 V" -to dac_data[13] +# disable auto-pack + +set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE" +set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF +set_global_assignment -name QII_AUTO_PACKED_REGISTERS OFF + execute_flow -compile diff --git a/projects/usdrx1/a5gt/system_top.v b/projects/usdrx1/a5gt/system_top.v index 2e7836be1..99797bf10 100644 --- a/projects/usdrx1/a5gt/system_top.v +++ b/projects/usdrx1/a5gt/system_top.v @@ -133,6 +133,9 @@ module system_top ( wire sys_125m_clk; wire sys_25m_clk; wire sys_2m5_clk; + wire sys_cpu_clk; + wire sys_cpu_mem_resetn; + wire sys_cpu_resetn; wire sys_pll_locked; wire eth_tx_clk; wire eth_tx_mode_1g; @@ -152,6 +155,10 @@ module system_top ( wire [ 63:0] gpio_i; wire [ 63:0] gpio_o; + // sys reset + + assign sys_cpu_resetn = sys_resetn & sys_cpu_mem_resetn & sys_pll_locked; + // ethernet transmit clock assign eth_tx_clk = (eth_tx_mode_1g == 1'b1) ? sys_125m_clk : @@ -322,7 +329,9 @@ module system_top ( .sys_125m_clk_clk (sys_125m_clk), .sys_25m_clk_clk (sys_25m_clk), .sys_2m5_clk_clk (sys_2m5_clk), - .sys_clk_clk (sys_clk), + .sys_clk_clk (sys_cpu_clk), + .sys_cpu_clk_clk (sys_cpu_clk), + .sys_cpu_reset_reset_n (sys_cpu_mem_resetn), .sys_ddr3_cntrl_mem_mem_a (ddr3_a), .sys_ddr3_cntrl_mem_mem_ba (ddr3_ba), .sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p), @@ -358,7 +367,9 @@ module system_top ( .sys_gpio_in_export (gpio_i[63:32]), .sys_gpio_out_export (gpio_o[63:32]), .sys_pll_locked_export (sys_pll_locked), - .sys_rst_reset_n (sys_resetn), + .sys_ref_clk_clk (sys_clk), + .sys_ref_rst_reset_n (sys_resetn), + .sys_rst_reset_n (sys_cpu_resetn), .sys_spi_MISO (spi_miso), .sys_spi_MOSI (spi_mosi), .sys_spi_SCLK (spi_clk), diff --git a/projects/usdrx1/common/usdrx1_qsys.tcl b/projects/usdrx1/common/usdrx1_qsys.tcl index dd10d8195..d30af0ead 100644 --- a/projects/usdrx1/common/usdrx1_qsys.tcl +++ b/projects/usdrx1/common/usdrx1_qsys.tcl @@ -6,6 +6,7 @@ set_instance_parameter_value avl_usdrx1_xcvr {ID} {1} set_instance_parameter_value avl_usdrx1_xcvr {TX_OR_RX_N} {0} set_instance_parameter_value avl_usdrx1_xcvr {PCS_CONFIG} {JESD_PCS_CFG1} set_instance_parameter_value avl_usdrx1_xcvr {LANE_RATE} {3200.0} +set_instance_parameter_value avl_usdrx1_xcvr {SYSCLK_FREQUENCY} {50.0} set_instance_parameter_value avl_usdrx1_xcvr {PLLCLK_FREQUENCY} {1600.0} set_instance_parameter_value avl_usdrx1_xcvr {REFCLK_FREQUENCY} {80.0} set_instance_parameter_value avl_usdrx1_xcvr {CORECLK_FREQUENCY} {80.0}