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daq2: A10GX, added extra pipelining in the interconnect in order to improve timing

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Adrian Costina 2017-10-20 13:45:05 +01:00
parent 083962450a
commit aa6af4e522
1 changed files with 9 additions and 0 deletions
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9
projects/daq2/a10gx/system_qsys.tcl
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@ -8,4 +8,13 @@ source $ad_hdl_dir/projects/common/a10gx/a10gx_system_qsys.tcl
source $ad_hdl_dir/projects/common/altera/dacfifo_qsys.tcl
source ../common/daq2_qsys.tcl
set_interconnect_requirement {mm_interconnect_0|rsp_demux_021.src7/sys_ddr3_cntrl_ctrl_amm_0_to_sys_ethernet_dma_rx_mm_write_rsp_width_adapter.sink} {qsys_mm.postTransform.pipelineCount} {1}
set_interconnect_requirement {mm_interconnect_0|rsp_demux_021.src6/sys_ddr3_cntrl_ctrl_amm_0_to_sys_ethernet_dma_tx_mm_read_rsp_width_adapter.sink} {qsys_mm.postTransform.pipelineCount} {1}
set_interconnect_requirement {mm_interconnect_0|rsp_demux_021.src3/sys_ddr3_cntrl_ctrl_amm_0_to_axi_ad9680_dma_m_dest_axi_rd_rsp_width_adapter.sink} {qsys_mm.postTransform.pipelineCount} {1}
set_interconnect_requirement {mm_interconnect_0|rsp_demux_021.src0/sys_ddr3_cntrl_ctrl_amm_0_to_sys_cpu_data_master_rsp_width_adapter.sink} {qsys_mm.postTransform.pipelineCount} {1}
set_interconnect_requirement {mm_interconnect_0|rsp_demux_021.src1/sys_ddr3_cntrl_ctrl_amm_0_to_sys_cpu_instruction_master_rsp_width_adapter.sink} {qsys_mm.postTransform.pipelineCount} {1}
set_interconnect_requirement {mm_interconnect_0|rsp_demux_021.src2/sys_ddr3_cntrl_ctrl_amm_0_to_axi_ad9680_dma_m_dest_axi_wr_rsp_width_adapter.sink} {qsys_mm.postTransform.pipelineCount} {1}
set_interconnect_requirement {mm_interconnect_0|rsp_demux_021.src5/sys_ddr3_cntrl_ctrl_amm_0_to_axi_ad9144_dma_m_src_axi_rd_rsp_width_adapter.sink} {qsys_mm.postTransform.pipelineCount} {1}
set_interconnect_requirement {mm_interconnect_0|sys_ddr3_cntrl_ctrl_amm_0_to_sys_ethernet_dma_rx_mm_write_rsp_width_adapter.src/async_fifo_011.in} {qsys_mm.postTransform.pipelineCount} {1}
set_interconnect_requirement {mm_interconnect_0|rsp_demux_021.src4/sys_ddr3_cntrl_ctrl_amm_0_to_axi_ad9144_dma_m_src_axi_wr_rsp_width_adapter.sink} {qsys_mm.postTransform.pipelineCount} {1}