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up_axi: Same cycle BVALID/READY fails on Altera 

The Qsys interconnect does not handle the assertion of BVALID on the
same cycle as [A]WREADY. Add a single cycle of delay to prevent
deadlocks.

Similar to:
2817ccdb22
("up_axi: altera can not handle same clock assertion of arready and rvalid")

Signed-off-by: Matthew Fornero <matt.fornero@mathworks.com>
main
Matthew Fornero 2016-07-19 09:41:33 -07:00
parent b2203cacce
commit aa3a821456
1 changed files with 4 additions and 1 deletions
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5
library/common/up_axi.v
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@ -129,6 +129,7 @@ module up_axi (
reg [31:0] up_wdata = 'd0; reg [31:0] up_wdata = 'd0;
reg [ 2:0] up_wcount = 'd0; reg [ 2:0] up_wcount = 'd0;
reg up_wack_int = 'd0; reg up_wack_int = 'd0;
reg up_wack_int_d = 'd0;
reg up_axi_arready = 'd0; reg up_axi_arready = 'd0;
reg up_axi_rvalid = 'd0; reg up_axi_rvalid = 'd0;
reg [31:0] up_axi_rdata = 'd0; reg [31:0] up_axi_rdata = 'd0;
@ -163,7 +164,7 @@ module up_axi (
end end
if ((up_axi_bready == 1'b1) && (up_axi_bvalid == 1'b1)) begin if ((up_axi_bready == 1'b1) && (up_axi_bvalid == 1'b1)) begin
up_axi_bvalid <= 1'b0; up_axi_bvalid <= 1'b0;
end else if (up_wack_int == 1'b1) begin end else if (up_wack_int_d == 1'b1) begin
up_axi_bvalid <= 1'b1; up_axi_bvalid <= 1'b1;
end end
end end
@ -198,12 +199,14 @@ module up_axi (
always @(negedge up_rstn or posedge up_clk) begin always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin if (up_rstn == 0) begin
up_wack_int <= 'd0; up_wack_int <= 'd0;
up_wack_int_d <= 'd0;
end else begin end else begin
if ((up_wcount == 3'h7) && (up_wack == 1'b0)) begin if ((up_wcount == 3'h7) && (up_wack == 1'b0)) begin
up_wack_int <= 1'b1; up_wack_int <= 1'b1;
end else if (up_wsel == 1'b1) begin end else if (up_wsel == 1'b1) begin
up_wack_int <= up_wack; up_wack_int <= up_wack;
end end
up_wack_int_d <= up_wack_int;
end end
end end