diff --git a/library/axi_ad9361/axi_ad9361_alt_lvds_rx.v b/library/axi_ad9361/axi_ad9361_alt_lvds_rx.v deleted file mode 100644 index 9f48dd55a..000000000 --- a/library/axi_ad9361/axi_ad9361_alt_lvds_rx.v +++ /dev/null @@ -1,202 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2011(c) Analog Devices, Inc. -// -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without modification, -// are permitted provided that the following conditions are met: -// - Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in -// the documentation and/or other materials provided with the -// distribution. -// - Neither the name of Analog Devices, Inc. nor the names of its -// contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// - The use of this software may or may not infringe the patent rights -// of one or more patent holders. This license does not release you -// from the requirement that you obtain separate licenses from these -// patent holders to use this software. -// - Use of the software either in source or binary form, must be run -// on or directly connected to an Analog Devices Inc. component. -// -// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, -// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. -// -// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module axi_ad9361_alt_lvds_rx ( - - // physical interface (receive) - - rx_clk_in_p, - rx_clk_in_n, - rx_frame_in_p, - rx_frame_in_n, - rx_data_in_p, - rx_data_in_n, - - // data interface - - clk, - rx_frame, - rx_data_0, - rx_data_1, - rx_data_2, - rx_data_3, - rx_locked); - - // physical interface (receive) - - input rx_clk_in_p; - input rx_clk_in_n; - input rx_frame_in_p; - input rx_frame_in_n; - input [ 5:0] rx_data_in_p; - input [ 5:0] rx_data_in_n; - - // data interface - - output clk; - output [ 3:0] rx_frame; - output [ 5:0] rx_data_0; - output [ 5:0] rx_data_1; - output [ 5:0] rx_data_2; - output [ 5:0] rx_data_3; - output rx_locked; - - // internal signals - - wire [27:0] rx_data_s; - - // instantiations - - assign rx_frame[3] = rx_data_s[24]; - assign rx_frame[2] = rx_data_s[25]; - assign rx_frame[1] = rx_data_s[26]; - assign rx_frame[0] = rx_data_s[27]; - assign rx_data_3[5] = rx_data_s[20]; - assign rx_data_3[4] = rx_data_s[16]; - assign rx_data_3[3] = rx_data_s[12]; - assign rx_data_3[2] = rx_data_s[ 8]; - assign rx_data_3[1] = rx_data_s[ 4]; - assign rx_data_3[0] = rx_data_s[ 0]; - assign rx_data_2[5] = rx_data_s[21]; - assign rx_data_2[4] = rx_data_s[17]; - assign rx_data_2[3] = rx_data_s[13]; - assign rx_data_2[2] = rx_data_s[ 9]; - assign rx_data_2[1] = rx_data_s[ 5]; - assign rx_data_2[0] = rx_data_s[ 1]; - assign rx_data_1[5] = rx_data_s[22]; - assign rx_data_1[4] = rx_data_s[18]; - assign rx_data_1[3] = rx_data_s[14]; - assign rx_data_1[2] = rx_data_s[10]; - assign rx_data_1[1] = rx_data_s[ 6]; - assign rx_data_1[0] = rx_data_s[ 2]; - assign rx_data_0[5] = rx_data_s[23]; - assign rx_data_0[4] = rx_data_s[19]; - assign rx_data_0[3] = rx_data_s[15]; - assign rx_data_0[2] = rx_data_s[11]; - assign rx_data_0[1] = rx_data_s[ 7]; - assign rx_data_0[0] = rx_data_s[ 3]; - - altlvds_rx #( - .buffer_implementation ("RAM"), - .cds_mode ("UNUSED"), - .common_rx_tx_pll ("ON"), - .data_align_rollover (4), - .data_rate ("500.0 Mbps"), - .deserialization_factor (4), - .dpa_initial_phase_value (0), - .dpll_lock_count (0), - .dpll_lock_window (0), - .enable_clock_pin_mode ("UNUSED"), - .enable_dpa_align_to_rising_edge_only ("OFF"), - .enable_dpa_calibration ("ON"), - .enable_dpa_fifo ("UNUSED"), - .enable_dpa_initial_phase_selection ("OFF"), - .enable_dpa_mode ("OFF"), - .enable_dpa_pll_calibration ("OFF"), - .enable_soft_cdr_mode ("OFF"), - .implement_in_les ("OFF"), - .inclock_boost (0), - .inclock_data_alignment ("EDGE_ALIGNED"), - .inclock_period (4000), - .inclock_phase_shift (0), - .input_data_rate (500), - .intended_device_family ("Cyclone V"), - .lose_lock_on_one_change ("UNUSED"), - .lpm_hint ("CBX_MODULE_PREFIX=axi_ad9361_alt_lvds_rx"), - .lpm_type ("altlvds_rx"), - .number_of_channels (7), - .outclock_resource ("Regional clock"), - .pll_operation_mode ("NORMAL"), - .pll_self_reset_on_loss_lock ("UNUSED"), - .port_rx_channel_data_align ("PORT_UNUSED"), - .port_rx_data_align ("PORT_UNUSED"), - .refclk_frequency ("250.000000 MHz"), - .registered_data_align_input ("UNUSED"), - .registered_output ("ON"), - .reset_fifo_at_first_lock ("UNUSED"), - .rx_align_data_reg ("RISING_EDGE"), - .sim_dpa_is_negative_ppm_drift ("OFF"), - .sim_dpa_net_ppm_variation (0), - .sim_dpa_output_clock_phase_shift (0), - .use_coreclock_input ("OFF"), - .use_dpll_rawperror ("OFF"), - .use_external_pll ("OFF"), - .use_no_phase_shift ("ON"), - .x_on_bitslip ("ON"), - .clk_src_is_pll ("off")) - i_altlvds_rx ( - .rx_inclock (rx_clk_in_p), - .rx_in ({rx_frame_in_p, rx_data_in_p}), - .rx_outclock (clk), - .rx_out (rx_data_s), - .rx_locked (rx_locked), - .dpa_pll_cal_busy (), - .dpa_pll_recal (1'b0), - .pll_areset (1'b0), - .pll_phasecounterselect (), - .pll_phasedone (1'b1), - .pll_phasestep (), - .pll_phaseupdown (), - .pll_scanclk (), - .rx_cda_max (), - .rx_cda_reset ({7{1'b0}}), - .rx_channel_data_align ({7{1'b0}}), - .rx_coreclk ({7{1'b1}}), - .rx_data_align (1'b0), - .rx_data_align_reset (1'b0), - .rx_data_reset (1'b0), - .rx_deskew (1'b0), - .rx_divfwdclk (), - .rx_dpa_lock_reset ({7{1'b0}}), - .rx_dpa_locked (), - .rx_dpaclock (1'b0), - .rx_dpll_enable ({7{1'b1}}), - .rx_dpll_hold ({7{1'b0}}), - .rx_dpll_reset ({7{1'b0}}), - .rx_enable (1'b1), - .rx_fifo_reset ({7{1'b0}}), - .rx_pll_enable (1'b1), - .rx_readclock (1'b0), - .rx_reset ({7{1'b0}}), - .rx_syncclock (1'b0)); - -endmodule - -// *************************************************************************** -// *************************************************************************** diff --git a/library/axi_ad9361/axi_ad9361_alt_lvds_tx.v b/library/axi_ad9361/axi_ad9361_alt_lvds_tx.v deleted file mode 100644 index 2b96fccb6..000000000 --- a/library/axi_ad9361/axi_ad9361_alt_lvds_tx.v +++ /dev/null @@ -1,186 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2011(c) Analog Devices, Inc. -// -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without modification, -// are permitted provided that the following conditions are met: -// - Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in -// the documentation and/or other materials provided with the -// distribution. -// - Neither the name of Analog Devices, Inc. nor the names of its -// contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// - The use of this software may or may not infringe the patent rights -// of one or more patent holders. This license does not release you -// from the requirement that you obtain separate licenses from these -// patent holders to use this software. -// - Use of the software either in source or binary form, must be run -// on or directly connected to an Analog Devices Inc. component. -// -// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, -// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. -// -// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module axi_ad9361_alt_lvds_tx ( - - // physical interface (transmit) - - tx_clk_out_p, - tx_clk_out_n, - tx_frame_out_p, - tx_frame_out_n, - tx_data_out_p, - tx_data_out_n, - - // data interface - - tx_clk, - clk, - tx_frame, - tx_data_0, - tx_data_1, - tx_data_2, - tx_data_3, - tx_locked); - - // physical interface (transmit) - - output tx_clk_out_p; - output tx_clk_out_n; - output tx_frame_out_p; - output tx_frame_out_n; - output [ 5:0] tx_data_out_p; - output [ 5:0] tx_data_out_n; - - // data interface - - input tx_clk; - input clk; - input [ 3:0] tx_frame; - input [ 5:0] tx_data_0; - input [ 5:0] tx_data_1; - input [ 5:0] tx_data_2; - input [ 5:0] tx_data_3; - output tx_locked; - - // internal registers - - reg [27:0] tx_data_n = 'd0; - reg [27:0] tx_data_p = 'd0; - - // internal signals - - wire core_clk; - wire [27:0] tx_data_s; - - // instantiations - - assign tx_clk_out_n = 1'd0; - assign tx_frame_out_n = 1'd0; - assign tx_data_out_n = 6'd0; - - assign tx_data_s[24] = tx_frame[3]; - assign tx_data_s[25] = tx_frame[2]; - assign tx_data_s[26] = tx_frame[1]; - assign tx_data_s[27] = tx_frame[0]; - assign tx_data_s[20] = tx_data_3[5]; - assign tx_data_s[16] = tx_data_3[4]; - assign tx_data_s[12] = tx_data_3[3]; - assign tx_data_s[ 8] = tx_data_3[2]; - assign tx_data_s[ 4] = tx_data_3[1]; - assign tx_data_s[ 0] = tx_data_3[0]; - assign tx_data_s[21] = tx_data_2[5]; - assign tx_data_s[17] = tx_data_2[4]; - assign tx_data_s[13] = tx_data_2[3]; - assign tx_data_s[ 9] = tx_data_2[2]; - assign tx_data_s[ 5] = tx_data_2[1]; - assign tx_data_s[ 1] = tx_data_2[0]; - assign tx_data_s[22] = tx_data_1[5]; - assign tx_data_s[18] = tx_data_1[4]; - assign tx_data_s[14] = tx_data_1[3]; - assign tx_data_s[10] = tx_data_1[2]; - assign tx_data_s[ 6] = tx_data_1[1]; - assign tx_data_s[ 2] = tx_data_1[0]; - assign tx_data_s[23] = tx_data_0[5]; - assign tx_data_s[19] = tx_data_0[4]; - assign tx_data_s[15] = tx_data_0[3]; - assign tx_data_s[11] = tx_data_0[2]; - assign tx_data_s[ 7] = tx_data_0[1]; - assign tx_data_s[ 3] = tx_data_0[0]; - - always @(negedge clk) begin - tx_data_n <= tx_data_s; - end - - always @(posedge core_clk) begin - tx_data_p <= tx_data_n; - end - - altlvds_tx #( - .center_align_msb ("UNUSED"), - .common_rx_tx_pll ("ON"), - .coreclock_divide_by (1), - .data_rate ("500.0 Mbps"), - .deserialization_factor (4), - .differential_drive (0), - .enable_clock_pin_mode ("UNUSED"), - .implement_in_les ("OFF"), - .inclock_boost (0), - .inclock_data_alignment ("EDGE_ALIGNED"), - .inclock_period (4000), - .inclock_phase_shift (0), - .intended_device_family ("Cyclone V"), - .lpm_hint ("CBX_MODULE_PREFIX=axi_ad9361_alt_lvds_tx"), - .lpm_type ("altlvds_tx"), - .multi_clock ("OFF"), - .number_of_channels (7), - .outclock_alignment ("EDGE_ALIGNED"), - .outclock_divide_by (2), - .outclock_duty_cycle (50), - .outclock_multiply_by (1), - .outclock_phase_shift (0), - .outclock_resource ("Regional clock"), - .output_data_rate (500), - .pll_compensation_mode ("AUTO"), - .pll_self_reset_on_loss_lock ("OFF"), - .preemphasis_setting (0), - .refclk_frequency ("250.000000 MHz"), - .registered_input ("TX_CORECLK"), - .use_external_pll ("OFF"), - .use_no_phase_shift ("ON"), - .vod_setting (0), - .clk_src_is_pll ("off")) - i_altlvds_tx ( - .tx_inclock (tx_clk), - .tx_coreclock (core_clk), - .tx_in (tx_data_p), - .tx_outclock (tx_clk_out_p), - .tx_out ({tx_frame_out_p, tx_data_out_p}), - .tx_locked (tx_locked), - .pll_areset (1'b0), - .sync_inclock (1'b0), - .tx_data_reset (1'b0), - .tx_enable (1'b1), - .tx_pll_enable (1'b1), - .tx_syncclock (1'b0)); - -endmodule - -// *************************************************************************** -// *************************************************************************** diff --git a/library/axi_ad9361/axi_ad9361_dev_if.v b/library/axi_ad9361/axi_ad9361_dev_if.v deleted file mode 100644 index d5b416fc9..000000000 --- a/library/axi_ad9361/axi_ad9361_dev_if.v +++ /dev/null @@ -1,622 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2011(c) Analog Devices, Inc. -// -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without modification, -// are permitted provided that the following conditions are met: -// - Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in -// the documentation and/or other materials provided with the -// distribution. -// - Neither the name of Analog Devices, Inc. nor the names of its -// contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// - The use of this software may or may not infringe the patent rights -// of one or more patent holders. This license does not release you -// from the requirement that you obtain separate licenses from these -// patent holders to use this software. -// - Use of the software either in source or binary form, must be run -// on or directly connected to an Analog Devices Inc. component. -// -// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, -// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. -// -// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// *************************************************************************** -// *************************************************************************** -// This interface includes both the transmit and receive components - -// They both uses the same clock (sourced from the receiving side). - -`timescale 1ns/100ps - -module axi_ad9361_dev_if ( - - // physical interface (receive) - - rx_clk_in_p, - rx_clk_in_n, - rx_frame_in_p, - rx_frame_in_n, - rx_data_in_p, - rx_data_in_n, - - // physical interface (transmit) - - tx_clk_out_p, - tx_clk_out_n, - tx_frame_out_p, - tx_frame_out_n, - tx_data_out_p, - tx_data_out_n, - - // ensm control - - enable, - txnrx, - - // clock (common to both receive and transmit) - - rst, - clk, - l_clk, - - // receive data path interface - - adc_valid, - adc_data, - adc_status, - adc_r1_mode, - adc_ddr_edgesel, - - // transmit data path interface - - dac_valid, - dac_data, - dac_r1_mode, - - // tdd interface - - tdd_enable, - tdd_txnrx, - tdd_mode, - - // delay interface - - up_clk, - up_enable, - up_txnrx, - up_adc_dld, - up_adc_dwdata, - up_adc_drdata, - up_dac_dld, - up_dac_dwdata, - up_dac_drdata, - delay_clk, - delay_rst, - delay_locked); - - // this parameter controls the buffer type based on the target device. - - parameter DEVICE_TYPE = 0; - parameter DAC_IODELAY_ENABLE = 0; - parameter IO_DELAY_GROUP = "dev_if_delay_group"; - - // physical interface (receive) - - input rx_clk_in_p; - input rx_clk_in_n; - input rx_frame_in_p; - input rx_frame_in_n; - input [ 5:0] rx_data_in_p; - input [ 5:0] rx_data_in_n; - - // physical interface (transmit) - - output tx_clk_out_p; - output tx_clk_out_n; - output tx_frame_out_p; - output tx_frame_out_n; - output [ 5:0] tx_data_out_p; - output [ 5:0] tx_data_out_n; - - // ensm control - - output enable; - output txnrx; - - // clock (common to both receive and transmit) - - input rst; - input clk; - output l_clk; - - // receive data path interface - - output adc_valid; - output [47:0] adc_data; - output adc_status; - input adc_r1_mode; - input adc_ddr_edgesel; - - // transmit data path interface - - input dac_valid; - input [47:0] dac_data; - input dac_r1_mode; - - // tdd interface - - input tdd_enable; - input tdd_txnrx; - input tdd_mode; - - // delay interface - - input up_clk; - input up_enable; - input up_txnrx; - input [ 6:0] up_adc_dld; - input [34:0] up_adc_dwdata; - output [34:0] up_adc_drdata; - input [ 9:0] up_dac_dld; - input [49:0] up_dac_dwdata; - output [49:0] up_dac_drdata; - input delay_clk; - input delay_rst; - output delay_locked; - - // internal registers - - reg [ 5:0] rx_data_p = 0; - reg rx_frame_p = 0; - reg [ 1:0] rx_ccnt = 0; - reg rx_calign = 0; - reg rx_align = 0; - reg [11:0] rx_data = 'd0; - reg [ 1:0] rx_frame = 'd0; - reg [11:0] rx_data_d = 'd0; - reg [ 1:0] rx_frame_d = 'd0; - reg rx_error_r1 = 'd0; - reg rx_valid_r1 = 'd0; - reg [23:0] rx_data_r1 = 'd0; - reg rx_error_r2 = 'd0; - reg rx_valid_r2 = 'd0; - reg [47:0] rx_data_r2 = 'd0; - reg adc_p_valid = 'd0; - reg [47:0] adc_p_data = 'd0; - reg adc_p_status = 'd0; - reg adc_n_valid = 'd0; - reg [47:0] adc_n_data = 'd0; - reg adc_n_status = 'd0; - reg adc_valid_int = 'd0; - reg [47:0] adc_data_int = 'd0; - reg adc_status_int = 'd0; - reg adc_valid = 'd0; - reg [47:0] adc_data = 'd0; - reg adc_status = 'd0; - reg [ 2:0] tx_data_cnt = 'd0; - reg [47:0] tx_data = 'd0; - reg tx_frame = 'd0; - reg [ 5:0] tx_data_p = 'd0; - reg [ 5:0] tx_data_n = 'd0; - reg tx_n_frame = 'd0; - reg [ 5:0] tx_n_data_p = 'd0; - reg [ 5:0] tx_n_data_n = 'd0; - reg tx_p_frame = 'd0; - reg [ 5:0] tx_p_data_p = 'd0; - reg [ 5:0] tx_p_data_n = 'd0; - reg up_enable_int = 'd0; - reg up_txnrx_int = 'd0; - reg enable_up_m1 = 'd0; - reg txnrx_up_m1 = 'd0; - reg enable_up = 'd0; - reg txnrx_up = 'd0; - reg enable_int = 'd0; - reg txnrx_int = 'd0; - reg enable_n_int = 'd0; - reg txnrx_n_int = 'd0; - reg enable_p_int = 'd0; - reg txnrx_p_int = 'd0; - - // internal signals - - wire rx_align_s; - wire [ 3:0] rx_frame_s; - wire [ 3:0] tx_data_sel_s; - wire [ 5:0] rx_data_p_s; - wire [ 5:0] rx_data_n_s; - wire rx_frame_p_s; - wire rx_frame_n_s; - - genvar l_inst; - - // receive data path interface - - assign rx_align_s = rx_frame_n_s ^ rx_frame_p_s; - - always @(posedge l_clk) begin - rx_data_p <= rx_data_p_s; - rx_frame_p <= rx_frame_p_s; - rx_ccnt <= rx_ccnt + 1'b1; - if (rx_ccnt == 2'd0) begin - rx_calign <= rx_align; - rx_align <= rx_align_s; - end else begin - rx_calign <= rx_calign; - rx_align <= rx_align | rx_align_s; - end - end - - assign rx_frame_s = {rx_frame_d, rx_frame}; - - always @(posedge l_clk) begin - if (rx_calign == 1'b1) begin - rx_data <= {rx_data_p, rx_data_n_s}; - rx_frame <= {rx_frame_p, rx_frame_n_s}; - end else begin - rx_data <= {rx_data_n_s, rx_data_p_s}; - rx_frame <= {rx_frame_n_s, rx_frame_p_s}; - end - rx_data_d <= rx_data; - rx_frame_d <= rx_frame; - end - - // receive data path for single rf, frame is expected to qualify i/q msb only - - always @(posedge l_clk) begin - rx_error_r1 <= ((rx_frame_s == 4'b1100) || (rx_frame_s == 4'b0011)) ? 1'b0 : 1'b1; - rx_valid_r1 <= (rx_frame_s == 4'b1100) ? 1'b1 : 1'b0; - if (rx_frame_s == 4'b1100) begin - rx_data_r1[11: 0] <= {rx_data_d[11:6], rx_data[11:6]}; - rx_data_r1[23:12] <= {rx_data_d[ 5:0], rx_data[ 5:0]}; - end - end - - // receive data path for dual rf, frame is expected to qualify i/q msb and lsb for rf-1 only - - always @(posedge l_clk) begin - rx_error_r2 <= ((rx_frame_s == 4'b1111) || (rx_frame_s == 4'b1100) || - (rx_frame_s == 4'b0000) || (rx_frame_s == 4'b0011)) ? 1'b0 : 1'b1; - rx_valid_r2 <= (rx_frame_s == 4'b0000) ? 1'b1 : 1'b0; - if (rx_frame_s == 4'b1111) begin - rx_data_r2[11: 0] <= {rx_data_d[11:6], rx_data[11:6]}; - rx_data_r2[23:12] <= {rx_data_d[ 5:0], rx_data[ 5:0]}; - end - if (rx_frame_s == 4'b0000) begin - rx_data_r2[35:24] <= {rx_data_d[11:6], rx_data[11:6]}; - rx_data_r2[47:36] <= {rx_data_d[ 5:0], rx_data[ 5:0]}; - end - end - - // receive data path mux - - always @(posedge l_clk) begin - if (adc_r1_mode == 1'b1) begin - adc_p_valid <= rx_valid_r1; - adc_p_data <= {24'd0, rx_data_r1}; - adc_p_status <= ~rx_error_r1; - end else begin - adc_p_valid <= rx_valid_r2; - adc_p_data <= rx_data_r2; - adc_p_status <= ~rx_error_r2; - end - end - - // transfer to a synchronous common clock - - always @(negedge l_clk) begin - adc_n_valid <= adc_p_valid; - adc_n_data <= adc_p_data; - adc_n_status <= adc_p_status; - end - - always @(posedge clk) begin - adc_valid_int <= adc_n_valid; - adc_data_int <= adc_n_data; - adc_status_int <= adc_n_status; - adc_valid <= adc_valid_int; - if (adc_valid_int == 1'b1) begin - adc_data <= adc_data_int; - end - adc_status <= adc_status_int; - end - - // transmit data path mux (reverse of what receive does above) - // the count simply selets the data muxing on the ddr outputs - - assign tx_data_sel_s = {tx_data_cnt[2], dac_r1_mode, tx_data_cnt[1:0]}; - - always @(posedge clk) begin - if (dac_valid == 1'b1) begin - tx_data_cnt <= 3'b100; - end else if (tx_data_cnt[2] == 1'b1) begin - tx_data_cnt <= tx_data_cnt + 1'b1; - end - if (dac_valid == 1'b1) begin - tx_data <= dac_data; - end - case (tx_data_sel_s) - 4'b1111: begin - tx_frame <= 1'b0; - tx_data_p <= tx_data[ 5: 0]; - tx_data_n <= tx_data[17:12]; - end - 4'b1110: begin - tx_frame <= 1'b1; - tx_data_p <= tx_data[11: 6]; - tx_data_n <= tx_data[23:18]; - end - 4'b1101: begin - tx_frame <= 1'b0; - tx_data_p <= tx_data[ 5: 0]; - tx_data_n <= tx_data[17:12]; - end - 4'b1100: begin - tx_frame <= 1'b1; - tx_data_p <= tx_data[11: 6]; - tx_data_n <= tx_data[23:18]; - end - 4'b1011: begin - tx_frame <= 1'b0; - tx_data_p <= tx_data[29:24]; - tx_data_n <= tx_data[41:36]; - end - 4'b1010: begin - tx_frame <= 1'b0; - tx_data_p <= tx_data[35:30]; - tx_data_n <= tx_data[47:42]; - end - 4'b1001: begin - tx_frame <= 1'b1; - tx_data_p <= tx_data[ 5: 0]; - tx_data_n <= tx_data[17:12]; - end - 4'b1000: begin - tx_frame <= 1'b1; - tx_data_p <= tx_data[11: 6]; - tx_data_n <= tx_data[23:18]; - end - default: begin - tx_frame <= 1'b0; - tx_data_p <= 6'd0; - tx_data_n <= 6'd0; - end - endcase - end - - // transfer data from a synchronous clock (skew less than 2ns) - - always @(negedge clk) begin - tx_n_frame <= tx_frame; - tx_n_data_p <= tx_data_p; - tx_n_data_n <= tx_data_n; - end - - always @(posedge l_clk) begin - tx_p_frame <= tx_n_frame; - tx_p_data_p <= tx_n_data_p; - tx_p_data_n <= tx_n_data_n; - end - - // tdd/ensm control - - always @(posedge up_clk) begin - up_enable_int <= up_enable; - up_txnrx_int <= up_txnrx; - end - - always @(posedge clk or posedge rst) begin - if (rst == 1'b1) begin - enable_up_m1 <= 1'b0; - txnrx_up_m1 <= 1'b0; - enable_up <= 1'b0; - txnrx_up <= 1'b0; - end else begin - enable_up_m1 <= up_enable_int; - txnrx_up_m1 <= up_txnrx_int; - enable_up <= enable_up_m1; - txnrx_up <= txnrx_up_m1; - end - end - - always @(posedge clk) begin - if (tdd_mode == 1'b1) begin - enable_int <= tdd_enable; - txnrx_int <= tdd_txnrx; - end else begin - enable_int <= enable_up; - txnrx_int <= txnrx_up; - end - end - - always @(negedge clk) begin - enable_n_int <= enable_int; - txnrx_n_int <= txnrx_int; - end - - always @(posedge l_clk) begin - enable_p_int <= enable_n_int; - txnrx_p_int <= txnrx_n_int; - end - - // receive data interface, ibuf -> idelay -> iddr - - generate - for (l_inst = 0; l_inst <= 5; l_inst = l_inst + 1) begin: g_rx_data - ad_lvds_in #( - .DEVICE_TYPE (DEVICE_TYPE), - .IODELAY_CTRL (0), - .IODELAY_GROUP (IO_DELAY_GROUP)) - i_rx_data ( - .rx_clk (l_clk), - .rx_data_in_p (rx_data_in_p[l_inst]), - .rx_data_in_n (rx_data_in_n[l_inst]), - .rx_data_p (rx_data_p_s[l_inst]), - .rx_data_n (rx_data_n_s[l_inst]), - .up_clk (up_clk), - .up_dld (up_adc_dld[l_inst]), - .up_dwdata (up_adc_dwdata[((l_inst*5)+4):(l_inst*5)]), - .up_drdata (up_adc_drdata[((l_inst*5)+4):(l_inst*5)]), - .delay_clk (delay_clk), - .delay_rst (delay_rst), - .delay_locked ()); - end - endgenerate - - // receive frame interface, ibuf -> idelay -> iddr - - ad_lvds_in #( - .DEVICE_TYPE (DEVICE_TYPE), - .IODELAY_CTRL (1), - .IODELAY_GROUP (IO_DELAY_GROUP)) - i_rx_frame ( - .rx_clk (l_clk), - .rx_data_in_p (rx_frame_in_p), - .rx_data_in_n (rx_frame_in_n), - .rx_data_p (rx_frame_p_s), - .rx_data_n (rx_frame_n_s), - .up_clk (up_clk), - .up_dld (up_adc_dld[6]), - .up_dwdata (up_adc_dwdata[34:30]), - .up_drdata (up_adc_drdata[34:30]), - .delay_clk (delay_clk), - .delay_rst (delay_rst), - .delay_locked (delay_locked)); - - // transmit data interface, oddr -> obuf - - generate - for (l_inst = 0; l_inst <= 5; l_inst = l_inst + 1) begin: g_tx_data - ad_lvds_out #( - .DEVICE_TYPE (DEVICE_TYPE), - .SINGLE_ENDED (0), - .IODELAY_ENABLE (DAC_IODELAY_ENABLE), - .IODELAY_CTRL (0), - .IODELAY_GROUP (IO_DELAY_GROUP)) - i_tx_data ( - .tx_clk (l_clk), - .tx_data_p (tx_p_data_p[l_inst]), - .tx_data_n (tx_p_data_n[l_inst]), - .tx_data_out_p (tx_data_out_p[l_inst]), - .tx_data_out_n (tx_data_out_n[l_inst]), - .up_clk (up_clk), - .up_dld (up_dac_dld[l_inst]), - .up_dwdata (up_dac_dwdata[((l_inst*5)+4):(l_inst*5)]), - .up_drdata (up_dac_drdata[((l_inst*5)+4):(l_inst*5)]), - .delay_clk (delay_clk), - .delay_rst (delay_rst), - .delay_locked ()); - end - endgenerate - - // transmit frame interface, oddr -> obuf - - ad_lvds_out #( - .DEVICE_TYPE (DEVICE_TYPE), - .SINGLE_ENDED (0), - .IODELAY_ENABLE (DAC_IODELAY_ENABLE), - .IODELAY_CTRL (0), - .IODELAY_GROUP (IO_DELAY_GROUP)) - i_tx_frame ( - .tx_clk (l_clk), - .tx_data_p (tx_p_frame), - .tx_data_n (tx_p_frame), - .tx_data_out_p (tx_frame_out_p), - .tx_data_out_n (tx_frame_out_n), - .up_clk (up_clk), - .up_dld (up_dac_dld[6]), - .up_dwdata (up_dac_dwdata[34:30]), - .up_drdata (up_dac_drdata[34:30]), - .delay_clk (delay_clk), - .delay_rst (delay_rst), - .delay_locked ()); - - // transmit clock interface, oddr -> obuf - - ad_lvds_out #( - .DEVICE_TYPE (DEVICE_TYPE), - .SINGLE_ENDED (0), - .IODELAY_ENABLE (DAC_IODELAY_ENABLE), - .IODELAY_CTRL (0), - .IODELAY_GROUP (IO_DELAY_GROUP)) - i_tx_clk ( - .tx_clk (l_clk), - .tx_data_p (1'b0), - .tx_data_n (1'b1), - .tx_data_out_p (tx_clk_out_p), - .tx_data_out_n (tx_clk_out_n), - .up_clk (up_clk), - .up_dld (up_dac_dld[7]), - .up_dwdata (up_dac_dwdata[39:35]), - .up_drdata (up_dac_drdata[39:35]), - .delay_clk (delay_clk), - .delay_rst (delay_rst), - .delay_locked ()); - - // enable, oddr -> obuf - - ad_lvds_out #( - .DEVICE_TYPE (DEVICE_TYPE), - .SINGLE_ENDED (1), - .IODELAY_ENABLE (DAC_IODELAY_ENABLE), - .IODELAY_CTRL (0), - .IODELAY_GROUP (IO_DELAY_GROUP)) - i_enable ( - .tx_clk (l_clk), - .tx_data_p (enable_p_int), - .tx_data_n (enable_p_int), - .tx_data_out_p (enable), - .tx_data_out_n (), - .up_clk (up_clk), - .up_dld (up_dac_dld[8]), - .up_dwdata (up_dac_dwdata[44:40]), - .up_drdata (up_dac_drdata[44:40]), - .delay_clk (delay_clk), - .delay_rst (delay_rst), - .delay_locked ()); - - // txnrx, oddr -> obuf - - ad_lvds_out #( - .DEVICE_TYPE (DEVICE_TYPE), - .SINGLE_ENDED (1), - .IODELAY_ENABLE (DAC_IODELAY_ENABLE), - .IODELAY_CTRL (0), - .IODELAY_GROUP (IO_DELAY_GROUP)) - i_txnrx ( - .tx_clk (l_clk), - .tx_data_p (txnrx_p_int), - .tx_data_n (txnrx_p_int), - .tx_data_out_p (txnrx), - .tx_data_out_n (), - .up_clk (up_clk), - .up_dld (up_dac_dld[9]), - .up_dwdata (up_dac_dwdata[49:45]), - .up_drdata (up_dac_drdata[49:45]), - .delay_clk (delay_clk), - .delay_rst (delay_rst), - .delay_locked ()); - - // device clock interface (receive clock) - - ad_lvds_clk #( - .DEVICE_TYPE (DEVICE_TYPE)) - i_clk ( - .clk_in_p (rx_clk_in_p), - .clk_in_n (rx_clk_in_n), - .clk (l_clk)); - -endmodule - -// *************************************************************************** -// *************************************************************************** diff --git a/library/axi_ad9361/axi_ad9361_dev_if_alt.v b/library/axi_ad9361/axi_ad9361_dev_if_alt.v deleted file mode 100644 index fd91e4dd1..000000000 --- a/library/axi_ad9361/axi_ad9361_dev_if_alt.v +++ /dev/null @@ -1,349 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2011(c) Analog Devices, Inc. -// -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without modification, -// are permitted provided that the following conditions are met: -// - Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in -// the documentation and/or other materials provided with the -// distribution. -// - Neither the name of Analog Devices, Inc. nor the names of its -// contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// - The use of this software may or may not infringe the patent rights -// of one or more patent holders. This license does not release you -// from the requirement that you obtain separate licenses from these -// patent holders to use this software. -// - Use of the software either in source or binary form, must be run -// on or directly connected to an Analog Devices Inc. component. -// -// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, -// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. -// -// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// *************************************************************************** -// *************************************************************************** -// This interface includes both the transmit and receive components - -// They both uses the same clock (sourced from the receiving side). - -`timescale 1ns/100ps - -module axi_ad9361_dev_if ( - - // physical interface (receive) - - rx_clk_in_p, - rx_clk_in_n, - rx_frame_in_p, - rx_frame_in_n, - rx_data_in_p, - rx_data_in_n, - - // physical interface (transmit) - - tx_clk_out_p, - tx_clk_out_n, - tx_frame_out_p, - tx_frame_out_n, - tx_data_out_p, - tx_data_out_n, - - // ensm control - - enable, - txnrx, - - // clock (common to both receive and transmit) - - rst, - clk, - l_clk, - - // receive data path interface - - adc_valid, - adc_data, - adc_status, - adc_r1_mode, - adc_ddr_edgesel, - - // transmit data path interface - - dac_valid, - dac_data, - dac_r1_mode, - - // tdd interface - - tdd_enable, - tdd_txnrx, - tdd_mode, - - // delay interface - - up_clk, - up_enable, - up_txnrx, - up_adc_dld, - up_adc_dwdata, - up_adc_drdata, - up_dac_dld, - up_dac_dwdata, - up_dac_drdata, - delay_clk, - delay_rst, - delay_locked); - - // this parameter controls the buffer type based on the target device. - - parameter DEVICE_TYPE = 0; - parameter DAC_IODELAY_ENABLE = 0; - parameter IO_DELAY_GROUP = "dev_if_delay_group"; - - // physical interface (receive) - - input rx_clk_in_p; - input rx_clk_in_n; - input rx_frame_in_p; - input rx_frame_in_n; - input [ 5:0] rx_data_in_p; - input [ 5:0] rx_data_in_n; - - // physical interface (transmit) - - output tx_clk_out_p; - output tx_clk_out_n; - output tx_frame_out_p; - output tx_frame_out_n; - output [ 5:0] tx_data_out_p; - output [ 5:0] tx_data_out_n; - - // ensm control - - output enable; - output txnrx; - - // clock (common to both receive and transmit) - - input rst; - input clk; - output l_clk; - - // receive data path interface - - output adc_valid; - output [47:0] adc_data; - output adc_status; - input adc_r1_mode; - input adc_ddr_edgesel; - - // transmit data path interface - - input dac_valid; - input [47:0] dac_data; - input dac_r1_mode; - - // tdd interface - - input tdd_enable; - input tdd_txnrx; - input tdd_mode; - - // delay interface - - input up_clk; - input up_enable; - input up_txnrx; - input [ 6:0] up_adc_dld; - input [34:0] up_adc_dwdata; - output [34:0] up_adc_drdata; - input [ 9:0] up_dac_dld; - input [49:0] up_dac_dwdata; - output [49:0] up_dac_drdata; - input delay_clk; - input delay_rst; - output delay_locked; - - // internal registers - - reg [ 3:0] rx_frame = 'd0; - reg [ 5:0] rx_data_3 = 'd0; - reg [ 5:0] rx_data_2 = 'd0; - reg [ 5:0] rx_data_1 = 'd0; - reg [ 5:0] rx_data_0 = 'd0; - reg rx_error_r2 = 'd0; - reg rx_valid_r2 = 'd0; - reg [23:0] rx_data_r2 = 'd0; - reg adc_valid = 'd0; - reg [47:0] adc_data = 'd0; - reg adc_status = 'd0; - reg tx_data_sel = 'd0; - reg [47:0] tx_data = 'd0; - reg [ 3:0] tx_frame = 'd0; - reg [ 5:0] tx_data_0 = 'd0; - reg [ 5:0] tx_data_1 = 'd0; - reg [ 5:0] tx_data_2 = 'd0; - reg [ 5:0] tx_data_3 = 'd0; - - // internal signals - - wire [ 3:0] rx_frame_inv_s; - wire tx_locked_s; - wire [ 3:0] rx_frame_s; - wire [ 5:0] rx_data_0_s; - wire [ 5:0] rx_data_1_s; - wire [ 5:0] rx_data_2_s; - wire [ 5:0] rx_data_3_s; - wire rx_locked_s; - - // tdd support- - - assign enable = up_enable; - assign txnrx = up_txnrx; - - // defaults - - assign delay_locked = 1'd1; - - // receive data path interface - - assign rx_frame_inv_s = ~rx_frame; - - always @(posedge l_clk) begin - rx_frame <= rx_frame_s; - rx_data_3 <= rx_data_3_s; - rx_data_2 <= rx_data_2_s; - rx_data_1 <= rx_data_1_s; - rx_data_0 <= rx_data_0_s; - if (rx_frame_inv_s == rx_frame_s) begin - rx_error_r2 <= 1'b0; - end else begin - rx_error_r2 <= 1'b1; - end - case (rx_frame) - 4'b1111: begin - rx_valid_r2 <= 1'b1; - rx_data_r2[23:12] <= {rx_data_1, rx_data_3}; - rx_data_r2[11: 0] <= {rx_data_0, rx_data_2}; - end - 4'b1110: begin - rx_valid_r2 <= 1'b1; - rx_data_r2[23:12] <= {rx_data_2, rx_data_0_s}; - rx_data_r2[11: 0] <= {rx_data_1, rx_data_3}; - end - 4'b1100: begin - rx_valid_r2 <= 1'b1; - rx_data_r2[23:12] <= {rx_data_3, rx_data_1_s}; - rx_data_r2[11: 0] <= {rx_data_2, rx_data_0_s}; - end - 4'b1000: begin - rx_valid_r2 <= 1'b1; - rx_data_r2[23:12] <= {rx_data_0_s, rx_data_2_s}; - rx_data_r2[11: 0] <= {rx_data_3, rx_data_1_s}; - end - 4'b0000: begin - rx_valid_r2 <= 1'b0; - rx_data_r2[23:12] <= {rx_data_1, rx_data_3}; - rx_data_r2[11: 0] <= {rx_data_0, rx_data_2}; - end - 4'b0001: begin - rx_valid_r2 <= 1'b0; - rx_data_r2[23:12] <= {rx_data_2, rx_data_0_s}; - rx_data_r2[11: 0] <= {rx_data_1, rx_data_3}; - end - 4'b0011: begin - rx_valid_r2 <= 1'b0; - rx_data_r2[23:12] <= {rx_data_3, rx_data_1_s}; - rx_data_r2[11: 0] <= {rx_data_2, rx_data_0_s}; - end - 4'b0111: begin - rx_valid_r2 <= 1'b0; - rx_data_r2[23:12] <= {rx_data_0_s, rx_data_2_s}; - rx_data_r2[11: 0] <= {rx_data_3, rx_data_1_s}; - end - default: begin - rx_valid_r2 <= 1'b0; - rx_data_r2[23:12] <= 12'd0; - rx_data_r2[11: 0] <= 12'd0; - end - endcase - if (rx_valid_r2 == 1'b1) begin - adc_valid <= 1'b0; - adc_data <= {24'd0, rx_data_r2}; - end else begin - adc_valid <= 1'b1; - adc_data <= {rx_data_r2, adc_data[23:0]}; - end - adc_status <= ~rx_error_r2 & rx_locked_s & tx_locked_s; - end - - // transmit data path mux - - always @(posedge l_clk) begin - tx_data_sel <= dac_valid; - tx_data <= dac_data; - if (tx_data_sel == 1'b1) begin - tx_frame <= 4'b1111; - tx_data_0 <= tx_data[11: 6]; - tx_data_1 <= tx_data[23:18]; - tx_data_2 <= tx_data[ 5: 0]; - tx_data_3 <= tx_data[17:12]; - end else begin - tx_frame <= 4'b0000; - tx_data_0 <= tx_data[35:30]; - tx_data_1 <= tx_data[47:42]; - tx_data_2 <= tx_data[29:24]; - tx_data_3 <= tx_data[41:36]; - end - end - - // interface (transmit) - - axi_ad9361_alt_lvds_tx i_tx ( - .tx_clk_out_p (tx_clk_out_p), - .tx_clk_out_n (tx_clk_out_n), - .tx_frame_out_p (tx_frame_out_p), - .tx_frame_out_n (tx_frame_out_n), - .tx_data_out_p (tx_data_out_p), - .tx_data_out_n (tx_data_out_n), - .tx_clk (rx_clk_in_p), - .clk (l_clk), - .tx_frame (tx_frame), - .tx_data_0 (tx_data_0), - .tx_data_1 (tx_data_1), - .tx_data_2 (tx_data_2), - .tx_data_3 (tx_data_3), - .tx_locked (tx_locked_s)); - - // interface (receive) - - axi_ad9361_alt_lvds_rx i_rx ( - .rx_clk_in_p (rx_clk_in_p), - .rx_clk_in_n (rx_clk_in_n), - .rx_frame_in_p (rx_frame_in_p), - .rx_frame_in_n (rx_frame_in_n), - .rx_data_in_p (rx_data_in_p), - .rx_data_in_n (rx_data_in_n), - .clk (l_clk), - .rx_frame (rx_frame_s), - .rx_data_0 (rx_data_0_s), - .rx_data_1 (rx_data_1_s), - .rx_data_2 (rx_data_2_s), - .rx_data_3 (rx_data_3_s), - .rx_locked (rx_locked_s)); - -endmodule - -// *************************************************************************** -// ***************************************************************************