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altera- serdes changes

main
Rejeesh Kutty 2016-10-28 14:09:04 -04:00
parent d010f3e687
commit a9d03af771
7 changed files with 504 additions and 439 deletions
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7
library/altera/common/ad_serdes_clk.v
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@ -34,9 +34,6 @@
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// serial data output interface: serdes(x8)
// do NOT use this module AS IT IS, the sub modules must be generated inside _hw.tcl file.
// replace __*__ names with the component names
`timescale 1ps/1ps
@ -157,7 +154,7 @@ module __ad_serdes_clk__ #(
generate
if (DEVICE_TYPE == ARRIA10) begin
__alt_serdes_clk_core__ i_core (
__ad_serdes_clk_1__ i_core (
.rst_reset (rst),
.ref_clk_clk (clk_in_p),
.locked_export (up_drp_locked_int_s),
@ -181,7 +178,7 @@ module __ad_serdes_clk__ #(
assign phase = 8'd0;
__alt_serdes_clk_core__ i_core (
__ad_serdes_clk_1__ i_core (
.rst_reset (rst),
.ref_clk_clk (clk_in_p),
.locked_export (up_drp_locked_int_s),

93
library/altera/common/ad_serdes_in.v
View File

@ -38,13 +38,16 @@
`timescale 1ps/1ps
module ad_serdes_in #(
module __ad_serdes_in__ #(
// parameters
parameter DEVICE_TYPE = 0,
parameter DDR_OR_SDR_N = 0,
parameter SERDES_FACTOR = 8,
parameter DATA_WIDTH = 16) (
parameter DATA_WIDTH = 16,
parameter IODELAY_CTRL = 0,
parameter IODELAY_GROUP = "dev_if_delay_group") (
// reset and clocks
@ -83,38 +86,56 @@ module ad_serdes_in #(
// local parameter
localparam C5SOC = 1;
localparam ARRIA10 = 0;
localparam CYCLONE5 = 1;
// internal signals
wire [(DATA_WIDTH-1):0] delay_locked_s;
wire [(DATA_WIDTH-1):0] data_out_s[ 7:0];
wire [(DATA_WIDTH-1):0] data_sel_s[ 7:0];
wire [(DATA_WIDTH-1):0] data_samples_s[0:(SERDES_FACTOR-1)];
wire [(SERDES_FACTOR-1):0] data_out_s[0:(DATA_WIDTH-1)];
// assignments
assign up_drdata = 5'd0;
assign delay_locked = & delay_locked_s;
assign data_s0 = data_sel_s[0];
assign data_s1 = data_sel_s[1];
assign data_s2 = data_sel_s[2];
assign data_s3 = data_sel_s[3];
assign data_s4 = data_sel_s[4];
assign data_s5 = data_sel_s[5];
assign data_s6 = data_sel_s[6];
assign data_s7 = data_sel_s[7];
// instantiations
genvar l_inst, l_order;
generate
for (l_inst = 0; l_inst < DATA_WIDTH; l_inst = l_inst + 1) begin: g_data
for (l_order = 0; l_order < SERDES_FACTOR; l_order = l_order + 1) begin: g_order
assign data_sel_s[l_order][l_inst] = data_out_s[8 - SERDES_FACTOR + l_order][l_inst];
end
genvar n;
genvar i;
if (DEVICE_TYPE == C5SOC ) begin
generate
if (SERDES_FACTOR == 8) begin
assign data_s7 = data_samples_s[7];
assign data_s6 = data_samples_s[6];
assign data_s5 = data_samples_s[5];
assign data_s4 = data_samples_s[4];
end else begin
assign data_s7 = 'd0;
assign data_s6 = 'd0;
assign data_s5 = 'd0;
assign data_s4 = 'd0;
end
endgenerate
assign data_s3 = data_samples_s[3];
assign data_s2 = data_samples_s[2];
assign data_s1 = data_samples_s[1];
assign data_s0 = data_samples_s[0];
generate
for (i = 0; i < SERDES_FACTOR; i = i + 1) begin: g_samples
for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_swap
assign data_samples_s[i][n] = data_out_s[n][((SERDES_FACTOR-1)-i)];
end
end
endgenerate
generate
for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_data
if (DEVICE_TYPE == CYCLONE5) begin
altlvds_rx #(
.buffer_implementation ("RAM"),
.cds_mode ("UNUSED"),
@ -165,16 +186,9 @@ module ad_serdes_in #(
.clk_src_is_pll ("off"))
i_altlvds_rx (
.rx_inclock (clk),
.rx_in (data_in_p[l_inst]),
.rx_in (data_in_p[n]),
.rx_outclock (),
.rx_out ({data_out_s[0][l_inst],
data_out_s[1][l_inst],
data_out_s[2][l_inst],
data_out_s[3][l_inst],
data_out_s[4][l_inst],
data_out_s[5][l_inst],
data_out_s[6][l_inst],
data_out_s[7][l_inst]}),
.rx_out (data_out_s[n]),
.rx_locked (),
.dpa_pll_cal_busy (),
.dpa_pll_recal (1'b0),
@ -205,25 +219,20 @@ module ad_serdes_in #(
.rx_readclock (1'b0),
.rx_reset ({7{1'b0}}),
.rx_syncclock (1'b0));
end
end else begin
alt_serdes_in_core i_core (
if (DEVICE_TYPE == ARRIA10) begin
__ad_serdes_in_1__ i_core (
.clk_export (clk),
.div_clk_export (div_clk),
.hs_phase_export (phase),
.loaden_export (loaden),
.locked_export (locked),
.data_in_export (data_in_p[l_inst]),
.data_s_export ({data_out_s[0][l_inst],
data_out_s[1][l_inst],
data_out_s[2][l_inst],
data_out_s[3][l_inst],
data_out_s[4][l_inst],
data_out_s[5][l_inst],
data_out_s[6][l_inst],
data_out_s[7][l_inst]}),
.delay_locked_export (delay_locked_s[l_inst]));
.data_in_export (data_in_p[n]),
.data_s_export (data_out_s[n]),
.delay_locked_export (delay_locked_s[n]));
end
end
endgenerate

76
library/altera/common/ad_serdes_out.v
View File

@ -34,13 +34,13 @@
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// serial data output interface: serdes(x8)
`timescale 1ps/1ps
module ad_serdes_out #(
module __ad_serdes_out__ #(
parameter DEVICE_TYPE = 0,
parameter DDR_OR_SDR_N = 1,
parameter SERDES_FACTOR = 8,
parameter DATA_WIDTH = 16) (
@ -66,12 +66,13 @@ module ad_serdes_out #(
// local parameter
localparam C5SOC = 1;
localparam ARRIA10 = 0;
localparam CYCLONE5 = 1;
// internal signals
wire [(DATA_WIDTH-1):0] data_in_s[ 7:0];
wire [(DATA_WIDTH-1):0] data_in_s2[ 7:0];
wire [(DATA_WIDTH-1):0] data_samples_s[0:(SERDES_FACTOR-1)];
wire [(SERDES_FACTOR-1):0] data_in_s[0:(DATA_WIDTH-1)];
// defaults
@ -79,26 +80,35 @@ module ad_serdes_out #(
// instantiations
assign data_in_s[0] = data_s0;
assign data_in_s[1] = data_s1;
assign data_in_s[2] = data_s2;
assign data_in_s[3] = data_s3;
assign data_in_s[4] = data_s4;
assign data_in_s[5] = data_s5;
assign data_in_s[6] = data_s6;
assign data_in_s[7] = data_s7;
genvar n;
genvar i;
genvar l_order;
generate
for (l_order = 0; l_order < 8; l_order = l_order + 1) begin: g_order
assign data_in_s2[l_order] = (l_order < 8-SERDES_FACTOR) ? 1'b0 : data_in_s[l_order -8 + SERDES_FACTOR];
if (SERDES_FACTOR == 8) begin
assign data_samples_s[7] = data_s7;
assign data_samples_s[6] = data_s6;
assign data_samples_s[5] = data_s5;
assign data_samples_s[4] = data_s4;
end
endgenerate
genvar l_inst;
assign data_samples_s[3] = data_s3;
assign data_samples_s[2] = data_s2;
assign data_samples_s[1] = data_s1;
assign data_samples_s[0] = data_s0;
generate
for (l_inst = 0; l_inst < DATA_WIDTH; l_inst = l_inst + 1) begin: g_data
if (DEVICE_TYPE == C5SOC) begin
for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_swap
for (i = 0; i < SERDES_FACTOR; i = i + 1) begin: g_samples
assign data_in_s[n][((SERDES_FACTOR-1)-i)] = data_samples_s[i][n];
end
end
endgenerate
generate
for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_data
if (DEVICE_TYPE == CYCLONE5) begin
altlvds_tx #(
.center_align_msb ("UNUSED"),
.common_rx_tx_pll ("ON"),
@ -136,16 +146,9 @@ module ad_serdes_out #(
i_altlvds_tx (
.tx_inclock (clk),
.tx_coreclock (div_clk),
.tx_in ({data_in_s2[0][l_inst],
data_in_s2[1][l_inst],
data_in_s2[2][l_inst],
data_in_s2[3][l_inst],
data_in_s2[4][l_inst],
data_in_s2[5][l_inst],
data_in_s2[6][l_inst],
data_in_s2[7][l_inst]}),
.tx_in (data_in_s[n]),
.tx_outclock (),
.tx_out (data_out_p[l_inst]),
.tx_out (data_out_p[n]),
.tx_locked (),
.pll_areset (1'b0),
.sync_inclock (1'b0),
@ -153,22 +156,17 @@ module ad_serdes_out #(
.tx_enable (loaden),
.tx_pll_enable (1'b1),
.tx_syncclock (1'b0));
end
end else begin
alt_serdes_out_core i_core (
if (DEVICE_TYPE == ARRIA10) begin
__ad_serdes_out_1__ i_core (
.clk_export (clk),
.div_clk_export (div_clk),
.loaden_export (loaden),
.data_out_export (data_out_p[l_inst]),
.data_s_export ({data_in_s2[0][l_inst],
data_in_s2[1][l_inst],
data_in_s2[2][l_inst],
data_in_s2[3][l_inst],
data_in_s2[4][l_inst],
data_in_s2[5][l_inst],
data_in_s2[6][l_inst],
data_in_s2[7][l_inst]}));
.data_out_export (data_out_p[n]),
.data_s_export (data_in_s[n]));
end
end
endgenerate

18
library/axi_ad9361/altera/axi_ad9361_lvds_if.v
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@ -403,7 +403,14 @@ module axi_ad9361_lvds_if #(
.data_s6 (),
.data_s7 (),
.data_in_p (rx_data_in_p),
.data_in_n (rx_data_in_n));
.data_in_n (rx_data_in_n),
.up_clk (1'd0),
.up_dld (6'd0),
.up_dwdata (30'd0),
.up_drdata (),
.delay_clk (1'd0),
.delay_rst (1'd0),
.delay_locked ());
// receive frame interface
@ -427,7 +434,14 @@ module axi_ad9361_lvds_if #(
.data_s6 (),
.data_s7 (),
.data_in_p (rx_frame_in_p),
.data_in_n (rx_frame_in_n));
.data_in_n (rx_frame_in_n),
.up_clk (1'd0),
.up_dld (6'd0),
.up_dwdata (30'd0),
.up_drdata (),
.delay_clk (1'd0),
.delay_rst (1'd0),
.delay_locked ());
// transmit data interface

78
library/axi_ad9361/axi_ad9361.v
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@ -116,32 +116,32 @@ module axi_ad9361 #(
// dma interface
output adc_enable_i0,
output reg adc_valid_i0,
output reg [15:0] adc_data_i0,
output adc_valid_i0,
output [15:0] adc_data_i0,
output adc_enable_q0,
output reg adc_valid_q0,
output reg [15:0] adc_data_q0,
output adc_valid_q0,
output [15:0] adc_data_q0,
output adc_enable_i1,
output reg adc_valid_i1,
output reg [15:0] adc_data_i1,
output adc_valid_i1,
output [15:0] adc_data_i1,
output adc_enable_q1,
output reg adc_valid_q1,
output reg [15:0] adc_data_q1,
output adc_valid_q1,
output [15:0] adc_data_q1,
input adc_dovf,
input adc_dunf,
output adc_r1_mode,
output dac_enable_i0,
output reg dac_valid_i0,
output dac_valid_i0,
input [15:0] dac_data_i0,
output dac_enable_q0,
output reg dac_valid_q0,
output dac_valid_q0,
input [15:0] dac_data_q0,
output dac_enable_i1,
output reg dac_valid_i1,
output dac_valid_i1,
input [15:0] dac_data_i1,
output dac_enable_q1,
output reg dac_valid_q1,
output dac_valid_q1,
input [15:0] dac_data_q1,
input dac_dovf,
input dac_dunf,
@ -193,6 +193,18 @@ module axi_ad9361 #(
// internal registers
reg adc_valid_i0_int = 'd0;
reg adc_valid_q0_int = 'd0;
reg adc_valid_i1_int = 'd0;
reg adc_valid_q1_int = 'd0;
reg [15:0] adc_data_i0_int = 'd0;
reg [15:0] adc_data_q0_int = 'd0;
reg [15:0] adc_data_i1_int = 'd0;
reg [15:0] adc_data_q1_int = 'd0;
reg dac_valid_i0_int = 'd0;
reg dac_valid_q0_int = 'd0;
reg dac_valid_i1_int = 'd0;
reg dac_valid_q1_int = 'd0;
reg up_wack = 'd0;
reg up_rack = 'd0;
reg [31:0] up_rdata = 'd0;
@ -406,22 +418,40 @@ module axi_ad9361 #(
end
endgenerate
assign adc_valid_i0 = adc_valid_i0_int;
assign adc_valid_q0 = adc_valid_q0_int;
assign adc_valid_i1 = adc_valid_i1_int;
assign adc_valid_q1 = adc_valid_q1_int;
always @(posedge clk) begin
adc_valid_i0_int <= tdd_rx_valid_s & adc_valid_i0_s;
adc_valid_q0_int <= tdd_rx_valid_s & adc_valid_q0_s;
adc_valid_i1_int <= tdd_rx_valid_s & adc_valid_i1_s;
adc_valid_q1_int <= tdd_rx_valid_s & adc_valid_q1_s;
end
dac_valid_i0 <= tdd_tx_valid_s & dac_valid_i0_s;
dac_valid_q0 <= tdd_tx_valid_s & dac_valid_q0_s;
dac_valid_i1 <= tdd_tx_valid_s & dac_valid_i1_s;
dac_valid_q1 <= tdd_tx_valid_s & dac_valid_q1_s;
assign adc_data_i0 = adc_data_i0_int;
assign adc_data_q0 = adc_data_q0_int;
assign adc_data_i1 = adc_data_i1_int;
assign adc_data_q1 = adc_data_q1_int;
adc_valid_i0 <= tdd_rx_valid_s & adc_valid_i0_s;
adc_valid_q0 <= tdd_rx_valid_s & adc_valid_q0_s;
adc_valid_i1 <= tdd_rx_valid_s & adc_valid_i1_s;
adc_valid_q1 <= tdd_rx_valid_s & adc_valid_q1_s;
adc_data_i0 <= adc_data_i0_s;
adc_data_q0 <= adc_data_q0_s;
adc_data_i1 <= adc_data_i1_s;
adc_data_q1 <= adc_data_q1_s;
always @(posedge clk) begin
adc_data_i0_int <= adc_data_i0_s;
adc_data_q0_int <= adc_data_q0_s;
adc_data_i1_int <= adc_data_i1_s;
adc_data_q1_int <= adc_data_q1_s;
end
assign dac_valid_i0 = dac_valid_i0_int;
assign dac_valid_q0 = dac_valid_q0_int;
assign dac_valid_i1 = dac_valid_i1_int;
assign dac_valid_q1 = dac_valid_q1_int;
always @(posedge clk) begin
dac_valid_i0_int <= tdd_tx_valid_s & dac_valid_i0_s;
dac_valid_q0_int <= tdd_tx_valid_s & dac_valid_q0_s;
dac_valid_i1_int <= tdd_tx_valid_s & dac_valid_i1_s;
dac_valid_q1_int <= tdd_tx_valid_s & dac_valid_q1_s;
end
// tdd

172
library/axi_ad9361/axi_ad9361_hw.tcl
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@ -13,22 +13,16 @@ set_module_property ELABORATION_CALLBACK p_axi_ad9361
# files
add_fileset quartus_synth QUARTUS_SYNTH "" ""
add_fileset quartus_synth QUARTUS_SYNTH "p_axi_ad9361_fset" ""
set_fileset_property quartus_synth TOP_LEVEL axi_ad9361
add_fileset_file ad_rst.v VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v
add_fileset_file ad_serdes_clk.v VERILOG PATH $ad_hdl_dir/library/altera/common/ad_serdes_clk.v
add_fileset_file ad_serdes_in.v VERILOG PATH $ad_hdl_dir/library/altera/common/ad_serdes_in.v
add_fileset_file ad_serdes_out.v VERILOG PATH $ad_hdl_dir/library/altera/common/ad_serdes_out.v
add_fileset_file ad_cmos_clk.v VERILOG PATH $ad_hdl_dir/library/altera/common/ad_cmos_clk.v
add_fileset_file ad_cmos_in.v VERILOG PATH $ad_hdl_dir/library/altera/common/ad_cmos_in.v
add_fileset_file ad_cmos_out.v VERILOG PATH $ad_hdl_dir/library/altera/common/ad_cmos_out.v
add_fileset_file ad_mul.v VERILOG PATH $ad_hdl_dir/library/altera/common/ad_mul.v
add_fileset_file ad_dcfilter.v VERILOG PATH $ad_hdl_dir/library/altera/common/ad_dcfilter.v
add_fileset_file ad_pnmon.v VERILOG PATH $ad_hdl_dir/library/common/ad_pnmon.v
add_fileset_file ad_dds_sine.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_sine.v
add_fileset_file ad_dds_1.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_1.v
add_fileset_file ad_dds.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds.v
add_fileset_file ad_datafmt.v VERILOG PATH $ad_hdl_dir/library/common/ad_datafmt.v
add_fileset_file ad_dcfilter.v VERILOG PATH $ad_hdl_dir/library/altera/common/ad_dcfilter.v
add_fileset_file ad_iqcor.v VERILOG PATH $ad_hdl_dir/library/common/ad_iqcor.v
add_fileset_file ad_addsub.v VERILOG PATH $ad_hdl_dir/library/common/ad_addsub.v
add_fileset_file ad_tdd_control.v VERILOG PATH $ad_hdl_dir/library/common/ad_tdd_control.v
@ -57,78 +51,32 @@ add_fileset_file axi_ad9361_constr.sdc SDC PATH axi_ad9361_constr.sdc
# parameters
add_parameter ID INTEGER 0
set_parameter_property ID DEFAULT_VALUE 0
set_parameter_property ID DISPLAY_NAME ID
set_parameter_property ID TYPE INTEGER
set_parameter_property ID UNITS None
set_parameter_property ID HDL_PARAMETER true
add_parameter DEVICE_TYPE INTEGER 0
set_parameter_property DEVICE_TYPE DEFAULT_VALUE 0
set_parameter_property DEVICE_TYPE DISPLAY_NAME DEVICE_TYPE
set_parameter_property DEVICE_TYPE TYPE INTEGER
set_parameter_property DEVICE_TYPE UNITS None
set_parameter_property DEVICE_TYPE HDL_PARAMETER true
add_parameter CMOS_OR_LVDS_N INTEGER 0
set_parameter_property CMOS_OR_LVDS_N DEFAULT_VALUE 0
set_parameter_property CMOS_OR_LVDS_N DISPLAY_NAME CMOS_OR_LVDS_N
set_parameter_property CMOS_OR_LVDS_N TYPE INTEGER
set_parameter_property CMOS_OR_LVDS_N UNITS None
set_parameter_property CMOS_OR_LVDS_N HDL_PARAMETER true
add_parameter DAC_DATAPATH_DISABLE INTEGER 0
set_parameter_property DAC_DATAPATH_DISABLE DEFAULT_VALUE 0
set_parameter_property DAC_DATAPATH_DISABLE DISPLAY_NAME DAC_DATAPATH_DISABLE
set_parameter_property DAC_DATAPATH_DISABLE TYPE INTEGER
set_parameter_property DAC_DATAPATH_DISABLE UNITS None
set_parameter_property DAC_DATAPATH_DISABLE HDL_PARAMETER true
add_parameter ADC_DATAPATH_DISABLE INTEGER 0
set_parameter_property ADC_DATAPATH_DISABLE DEFAULT_VALUE 0
set_parameter_property ADC_DATAPATH_DISABLE DISPLAY_NAME ADC_DATAPATH_DISABLE
set_parameter_property ADC_DATAPATH_DISABLE TYPE INTEGER
set_parameter_property ADC_DATAPATH_DISABLE UNITS None
set_parameter_property ADC_DATAPATH_DISABLE HDL_PARAMETER true
add_parameter DEVICE_FAMILY STRING
set_parameter_property DEVICE_FAMILY SYSTEM_INFO {DEVICE_FAMILY}
set_parameter_property DEVICE_FAMILY AFFECTS_GENERATION true
set_parameter_property DEVICE_FAMILY HDL_PARAMETER false
set_parameter_property DEVICE_FAMILY ENABLED false
# axi4 slave interface
add_parameter ID INTEGER 0
add_parameter MODE_1R1T INTEGER 0
add_parameter DEVICE_TYPE INTEGER 0
add_parameter TDD_DISABLE INTEGER 0
add_parameter CMOS_OR_LVDS_N INTEGER 0
add_parameter ADC_DATAPATH_DISABLE INTEGER 0
add_parameter ADC_USERPORTS_DISABLE INTEGER 0
add_parameter ADC_DATAFORMAT_DISABLE INTEGER 0
add_parameter ADC_DCFILTER_DISABLE INTEGER 0
add_parameter ADC_IQCORRECTION_DISABLE INTEGER 0
add_parameter DAC_IODELAY_ENABLE INTEGER 0
add_parameter DAC_DATAPATH_DISABLE INTEGER 0
add_parameter DAC_DDS_DISABLE INTEGER 0
add_parameter DAC_USERPORTS_DISABLE INTEGER 0
add_parameter DAC_IQCORRECTION_DISABLE INTEGER 0
add_parameter IO_DELAY_GROUP STRING "dev_if_delay_group"
add_interface s_axi_clock clock end
add_interface_port s_axi_clock s_axi_aclk clk Input 1
# interfaces
add_interface s_axi_reset reset end
set_interface_property s_axi_reset associatedClock s_axi_clock
add_interface_port s_axi_reset s_axi_aresetn reset_n Input 1
add_interface s_axi axi4lite end
set_interface_property s_axi associatedClock s_axi_clock
set_interface_property s_axi associatedReset s_axi_reset
add_interface_port s_axi s_axi_awvalid awvalid Input 1
add_interface_port s_axi s_axi_awaddr awaddr Input 16
add_interface_port s_axi s_axi_awprot awprot Input 3
add_interface_port s_axi s_axi_awready awready Output 1
add_interface_port s_axi s_axi_wvalid wvalid Input 1
add_interface_port s_axi s_axi_wdata wdata Input 32
add_interface_port s_axi s_axi_wstrb wstrb Input 4
add_interface_port s_axi s_axi_wready wready Output 1
add_interface_port s_axi s_axi_bvalid bvalid Output 1
add_interface_port s_axi s_axi_bresp bresp Output 2
add_interface_port s_axi s_axi_bready bready Input 1
add_interface_port s_axi s_axi_arvalid arvalid Input 1
add_interface_port s_axi s_axi_araddr araddr Input 16
add_interface_port s_axi s_axi_arprot arprot Input 3
add_interface_port s_axi s_axi_arready arready Output 1
add_interface_port s_axi s_axi_rvalid rvalid Output 1
add_interface_port s_axi s_axi_rresp rresp Output 2
add_interface_port s_axi s_axi_rdata rdata Output 32
add_interface_port s_axi s_axi_rready rready Input 1
ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn
# master-slave interface
@ -223,42 +171,11 @@ ad_alt_intf signal up_dac_gpio_out output 32
ad_alt_intf signal up_adc_gpio_in input 32
ad_alt_intf signal up_adc_gpio_out output 32
add_hdl_instance alt_ddio_in altera_gpio
set_instance_parameter_value alt_ddio_in {PIN_TYPE_GUI} {Input}
set_instance_parameter_value alt_ddio_in {SIZE} {1}
set_instance_parameter_value alt_ddio_in {gui_diff_buff} {0}
set_instance_parameter_value alt_ddio_in {gui_io_reg_mode} {DDIO}
add_hdl_instance alt_ddio_out altera_gpio
set_instance_parameter_value alt_ddio_out {PIN_TYPE_GUI} {Output}
set_instance_parameter_value alt_ddio_out {SIZE} {1}
set_instance_parameter_value alt_ddio_out {gui_diff_buff} {0}
set_instance_parameter_value alt_ddio_out {gui_io_reg_mode} {DDIO}
add_hdl_instance alt_serdes_clk_core alt_serdes
set_instance_parameter_value alt_serdes_clk_core {MODE} {CLK}
set_instance_parameter_value alt_serdes_clk_core {DDR_OR_SDR_N} {1}
set_instance_parameter_value alt_serdes_clk_core {SERDES_FACTOR} {4}
set_instance_parameter_value alt_serdes_clk_core {CLKIN_FREQUENCY} {250.0}
add_hdl_instance alt_serdes_in_core alt_serdes
set_instance_parameter_value alt_serdes_in_core {MODE} {IN}
set_instance_parameter_value alt_serdes_in_core {DDR_OR_SDR_N} {1}
set_instance_parameter_value alt_serdes_in_core {SERDES_FACTOR} {4}
set_instance_parameter_value alt_serdes_in_core {CLKIN_FREQUENCY} {250.0}
add_hdl_instance alt_serdes_out_core alt_serdes
set_instance_parameter_value alt_serdes_out_core {MODE} {OUT}
set_instance_parameter_value alt_serdes_out_core {DDR_OR_SDR_N} {1}
set_instance_parameter_value alt_serdes_out_core {SERDES_FACTOR} {4}
set_instance_parameter_value alt_serdes_out_core {CLKIN_FREQUENCY} {250.0}
# updates
proc p_axi_ad9361 {} {
set m_cmos_or_lvds_n [get_parameter_value CMOS_OR_LVDS_N]
set m_device_type [get_parameter_value DEVICE_TYPE]
set m_device_family [get_parameter_value DEVICE_FAMILY]
add_interface device_if conduit end
@ -294,14 +211,57 @@ proc p_axi_ad9361 {} {
add_interface_port device_if enable enable Output 1
add_interface_port device_if txnrx txnrx Output 1
if {$m_device_type == 1} {
if {$m_device_family == "Arria 10"} {
## add_hdl_instance do not work here (pending altera support)
add_hdl_instance alt_serdes_clk_core alt_serdes
set_instance_parameter_value alt_serdes_clk_core {MODE} {CLK}
set_instance_parameter_value alt_serdes_clk_core {DDR_OR_SDR_N} {1}
set_instance_parameter_value alt_serdes_clk_core {SERDES_FACTOR} {4}
set_instance_parameter_value alt_serdes_clk_core {CLKIN_FREQUENCY} {250.0}
add_hdl_instance alt_serdes_in_core alt_serdes
set_instance_parameter_value alt_serdes_in_core {MODE} {IN}
set_instance_parameter_value alt_serdes_in_core {DDR_OR_SDR_N} {1}
set_instance_parameter_value alt_serdes_in_core {SERDES_FACTOR} {4}
set_instance_parameter_value alt_serdes_in_core {CLKIN_FREQUENCY} {250.0}
add_hdl_instance alt_serdes_out_core alt_serdes
set_instance_parameter_value alt_serdes_out_core {MODE} {OUT}
set_instance_parameter_value alt_serdes_out_core {DDR_OR_SDR_N} {1}
set_instance_parameter_value alt_serdes_out_core {SERDES_FACTOR} {4}
set_instance_parameter_value alt_serdes_out_core {CLKIN_FREQUENCY} {250.0}
add_hdl_instance alt_ddio_in altera_gpio
set_instance_parameter_value alt_ddio_in {PIN_TYPE_GUI} {Input}
set_instance_parameter_value alt_ddio_in {SIZE} {1}
set_instance_parameter_value alt_ddio_in {gui_diff_buff} {0}
set_instance_parameter_value alt_ddio_in {gui_io_reg_mode} {DDIO}
add_hdl_instance alt_ddio_out altera_gpio
set_instance_parameter_value alt_ddio_out {PIN_TYPE_GUI} {Output}
set_instance_parameter_value alt_ddio_out {SIZE} {1}
set_instance_parameter_value alt_ddio_out {gui_diff_buff} {0}
set_instance_parameter_value alt_ddio_out {gui_io_reg_mode} {DDIO}
}
if {$m_device_type == 0} {
if {$m_device_family == "Cyclone V"} {
## add_hdl_instance do not work here (pending altera support)
}
}
proc p_axi_ad9361_fset {entityName} {
ad_ip_file ad_serdes_in.v ad_serdes_in.v ad_serdes_in_core
ad_ip_file ad_serdes_out.v ad_serdes_out.v ad_serdes_out_core
ad_ip_file ad_serdes_clk.v ad_serdes_clk.v ad_serdes_clk_core
ad_ip_file ad_cmos_in.v ad_cmos_in.v ad_cmos_in_core
ad_ip_file ad_cmos_out.v ad_cmos_out.v ad_cmos_out_core
add_fileset_file ad_serdes_in.v VERILOG PATH ad_serdes_in.v
add_fileset_file ad_serdes_out.v VERILOG PATH ad_serdes_out.v
add_fileset_file ad_serdes_clk.v VERILOG PATH ad_serdes_clk.v
add_fileset_file ad_cmos_in.v VERILOG PATH ad_cmos_in.v
add_fileset_file ad_cmos_out.v VERILOG PATH ad_cmos_out.v
}

57
library/scripts/adi_ip_alt.tcl
View File

@ -89,3 +89,60 @@ proc ad_generate_module_inst { inst_name mark source_file target_file } {
close $fp_target
}
proc ad_ip_intf_s_axi {aclk arstn} {
add_interface s_axi_clock clock end
add_interface_port s_axi_clock ${aclk} clk Input 1
add_interface s_axi_reset reset end
set_interface_property s_axi_reset associatedClock s_axi_clock
add_interface_port s_axi_reset ${arstn} reset_n Input 1
add_interface s_axi axi4lite end
set_interface_property s_axi associatedClock s_axi_clock
set_interface_property s_axi associatedReset s_axi_reset
add_interface_port s_axi s_axi_awvalid awvalid Input 1
add_interface_port s_axi s_axi_awaddr awaddr Input 16
add_interface_port s_axi s_axi_awprot awprot Input 3
add_interface_port s_axi s_axi_awready awready Output 1
add_interface_port s_axi s_axi_wvalid wvalid Input 1
add_interface_port s_axi s_axi_wdata wdata Input 32
add_interface_port s_axi s_axi_wstrb wstrb Input 4
add_interface_port s_axi s_axi_wready wready Output 1
add_interface_port s_axi s_axi_bvalid bvalid Output 1
add_interface_port s_axi s_axi_bresp bresp Output 2
add_interface_port s_axi s_axi_bready bready Input 1
add_interface_port s_axi s_axi_arvalid arvalid Input 1
add_interface_port s_axi s_axi_araddr araddr Input 16
add_interface_port s_axi s_axi_arprot arprot Input 3
add_interface_port s_axi s_axi_arready arready Output 1
add_interface_port s_axi s_axi_rvalid rvalid Output 1
add_interface_port s_axi s_axi_rresp rresp Output 2
add_interface_port s_axi s_axi_rdata rdata Output 32
add_interface_port s_axi s_axi_rready rready Input 1
}
proc ad_ip_file {ifile ofile flist} {
global ad_hdl_dir
set srcfile [open ${ad_hdl_dir}/library/altera/common/${ifile} r]
set dstfile [open ${ofile} w]
regsub {\..$} $ifile {} imodule
regsub {\..$} $ofile {} omodule
while {[gets $srcfile srcline] >= 0} {
regsub __${imodule}__ $srcline $omodule dstline
set index 0
foreach fword $flist {
incr index
regsub __${imodule}_${index}__ $dstline $fword dstline
}
puts $dstfile $dstline
}
close $srcfile
close $dstfile
}